Abstract: To provide an address programming device free from laser-blowing, a first, thin gate oxide film is formed on a semiconductor substrate, a first gate electrode is formed thereon, a second, thick gate oxide film is formed thereon, and a second gate electrode is formed thereon. Such a device is connected in series to a MOS transistor of the opposite polarity and such arrangements are cross-connected together to form a latch circuit. Data to be programmed and the inverted version thereof are written in the programming device. Programmed information is read depending on the change in weight of the latch when the power supply is turned on.

Abstract: A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak access device constructed in a semiconductor thin film layer located vertically above the strong devices. The strong devices are used in the data read and write paths, and the weak devices are used for latch feed-back and sector data erase. This first embodiment is used for high density and high speed memory applications. In a second embodiment, an SRAM cell comprises thin film inverters and thin film access devices constructed in a semiconductor thin film layer located substantially above logic transistors. The TFT SRAM cell is buried above the logic gates of an Integrated Circuit to consume no extra Silicon real estate. This second embodiment is used for slow access and Look-Up-Tables type memory applications.

Abstract: A semiconductor device comprising: an SOI substrate having a surface semiconductor layer, a gate electrode formed on the surface semiconductor layer via a gate insulating film, first conductive type source/drain regions formed in the surface semiconductor layer of both sides of the gate electrode, a second conductive type drawing diffusion layer formed in the surface semiconductor layer and contacted with at least one of the first conductive type source/drain regions, and a silicide layer which is formed on the surface semiconductor layer to partially or entirely overlie both said at least one of source/drain regions and the drawing diffusion layer, the silicide layer being grounded.

Abstract: A gate array integrated circuit is provided, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel and N-channel transistors have common control terminals. A multiple-bit memory cell is fabricated in the row and includes first and second latches, a read output, a first pass gate coupled between the first latch and the read output, and a second pass gate coupled between the second latch and the read output. The first pass gate includes a first one of the P-channel or N-channel transistors. The second pass gate includes a second one of the same type of the P-channel or N-channel transistors. The first and second same type transistors share a common diffusion region.

Abstract: A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOB transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOB transistors is in-creased, the threshold voltage of the MOB transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOB transistor can be set to 1, thereby allowing a reduction in the memory cell area.

Abstract: An interlayer dielectric film is formed to cover a gate electrode part formed on the surface of a semiconductor substrate. A shared contact hole exposing both of the upper surface of the gate electrode part and the surface of a cobalt silicide film is formed in the interlayer dielectric film. A side wall nitride film is formed on the side surface of the shared contact hole. On the surface of a lower portion of a side wall insulator film located on the bottom of the shared contact hole, a side wall nitride film is formed to cover the surface of a portion of a region of the semiconductor substrate located under the side wall insulator film. A barrier metal layer and a plug are formed in the shared contact hole. Thus, a semiconductor device suppressing a leakage current is obtained.

Abstract: An SRAM includes a plurality of memory cells which are arranged in an extension direction of bit lines, each of which has a long edge and a short edge, an extension direction of the short edge being equal to the extension direction of the bit lines. A distance between polysilicon wirings which are formed in one of the memory cells and which become gates of NMOS transistors arranged in the extension direction of the bit lines, respectively, differs from a distance between the polysilicon wiring and the polysilicon wiring which becomes a gate of an NMOS transistor formed in the other memory cell.

Abstract: The invention concerns a semi-conductor device comprising on a substrate: a first dynamic threshold voltage MOS transistor (10), with a gate (116), and a channel (111) of a first conductivity type, and a current limiter means (20) connected between the gate and the channel of said first transistor. In accordance with the invention, this first transistor is fitted with a first doped zone (160) of the first conductivity type, connected to the channel, and the current limiter means comprises a second doped zone (124) of a second conductivity type, placed against the first doped zone and electrically connected to the first zone by an ohmic connection. Application to the manufacture of CMOS circuits.

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: The invention includes a method of forming a magnetoresistive memory device. A trench is formed in an insulative material, and the trench is partially filled with a first magnetic material to narrow the trench. The narrowed trench is at least partially filled with a conductive material. A second magnetic material is formed over the conductive material. A non-magnetic layer is formed over the second magnetic material. A third magnetic material is formed over the non-magnetic layer. The conductive material and the first and second magnetic materials are incorporated into a sense portion of the magnetoresistive memory device. The third magnetic material is incorporated into a reference portion of the magnetoresistive memory device.

Abstract: A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

Abstract: A semiconductor integrated circuit device comprises a p-channel MISFET and/or an n-channel MISFET, of which an SRAM cell is constituted and which is arranged to have an offset structure, and MISFET for selection of SRAM cells and MISFET constituting a peripheral circuit of SRAM or a logic circuit which is arranged to have a non-offset structure. At least one of MISFET's constituting an SRAM cell is arranged to take a measure against GIDL (gate induced drain leakage) current.

Abstract: First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.

Abstract: The invention includes three-dimensional TFT based stacked CMOS inverters. Particular inverters can have a PFET device stacked over an NFET device. The PFET device can be a semiconductor-on-insulator thin film transistor construction, and can be formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The thin film of semiconductor material can comprise both silicon and germanium. Further, the thin film can contain two different layers. A first of the two layers can have silicon and germanium present in a relaxed crystalline lattice, and a second of the two layers can be a strained crystalline lattice of either silicon alone, or silicon in combination with germanium. The invention also includes computer systems utilizing such CMOS inverters.

Abstract: A semiconductor device, which is capable of improving isolation property of an isolation structure using STI without increasing impurity concentrations of wells, includes a well isolation structure in form of a shallow trench formed on the boundary between first and second wells opposite in conductivity type and adjacent to each other. When a first device region formed in the first well and a second device region formed in the second well are opposed at opposite sides of the well isolation structure, they are disposed at a first width (well isolation distance) than the second width when they are not opposed to each other. One of the device regions may be a dummy region which does not function as a circuit. In this configuration, angle of STI side walls is steeper, and STI width can be made smaller.

Abstract: A SRAM cell includes a single FinFET and two resonant tunnel diodes. The FinFet has multiple channel regions formed from separate fins. The resonant tunnel diodes may be formed from FinFET type fins. In particular, the resonant diodes may includes a thin, undoped silicon region surrounded by a dielectric. The SRAM cell is small and provides fast read/write access times.

Abstract: A semiconductor device has a gate electrode which is formed on a first conductive-type well set in semiconductor substrate, with a gate insulating film lying therebetween; a LDD structure in which, on either side of said gate electrode, there are formed a LDD region and a source/drain region; an interlayer insulating film to cover said gate electrode as well as said LDD regions; and contact sections. A contact section connecting to one side of the source/drain regions having a potential equal to a potential of said first conductive-type well is disposed so as to come into contact with the LDD region lying thereunder; and a contact section connecting to the other side of the source/drain region having a potential different from the potential of said first conductive-type well is disposed so as not to come into contact with the LDD region lying thereunder.

Abstract: A semiconductor storage device with high soft-error immunity is obtained. A semiconductor storage device has SRAM memory cells. NMOS transistors are driver transistors, NMOS transistors are access transistors, and PMOS transistors are load transistors. An NMOS transistor is a transistor for adding a resistance. The NMOS transistor has its gate connected to a power supply. The NMOS transistor has one of its source and drain connected to a storage node and the other connected to the gates of the NMOS transistor and the PMOS transistor. The resistance between the source and drain of the NMOS transistor can be adjusted with the gate length, the gate width, the source/drain impurity concentration, etc., which is, for example, about several tens of kilohms (k &OHgr;).

Abstract: A semiconductor memory device has a SRAM memory cell comprising: a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein a first diffusion region forming the first and third nMOS transistors and a second diffusion region forming the second and fourth nMOS transistors, respectively, are arranged in linear shapes without having any bent part, and driving capabilities of the first and second nMOS transistors are higher than those of the third and fourth nMOS transistors.

Abstract: A static semiconductor memory device capable of preventing soft errors is provided. The static semiconductor memory device includes: a silicon substrate having a p-type well region; a storage node; an n-type-low-concentration impurity region and a high-concentration impurity region formed in the surface of p-type well region and connected to storage node; and a p-type impurity region formed to have contact with high-concentration impurity region.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETS and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: Compact static random access memory (SRAM) cell layouts are provided for implementing one-port and two-port operation. The SRAM cell layouts include a plurality of field effect transistors (FETs). The plurality of FETs defines a storage cell and a pair of wordline FETs coupled to the storage cell. Each of the plurality of FETs has a device structure extending in a single direction. The device structure of each of the plurality of FETs includes a diffusion layer, a polysilicon layer and first metal layer. A local interconnect connects the diffusion layer, the polysilicon layer and the first metal layer. Each of the pair of wordline FETs having a gate input connected to a wordline. The wordline including a single wordline for implementing one-port operation or two separate wordline connections for implementing two-port operation.

Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Abstract: A memory cell (10) is a so-called CMOS type cell. P-wells (W1P, W2P, W3P) and N-wells (W4N, W5N) are formed in a main surface (5S) of a semiconductor substrate (5), and the wells (W2P, W4N, W1P, W5N, W3P) are aligned in this order. Driver transistors (11DN, 12DN) are formed in the wells (W2P, W3P), respectively. Load transistors (11LP, 12LP) are formed in the wells (W4N, W5N), respectively. Two access transistors (11AN, 12AN) are formed in the single well (W1P). N+-type impurity regions (FN30, FN10) constituting one of storage nodes are provided in different wells, and N+-type impurity regions (FN31, FN11) constituting the other of the storage nodes are also provided in different wells.

Abstract: A semiconductor device including a well divided into a plurality of parts by a trench, to effect a reduction in layout area, and a manufacturing method thereof. In the semiconductor device, an element isolation film is formed such as to have to a depth from the main surface of a semiconductor substrate, and the area from the main surface of the substrate to the depth is divided into a plurality of first regions. A first well is formed in each of the first regions. A second well is formed in a second region deeper than the first well in the substrate, and the second well is in contact with some of the first wells.

Abstract: Semiconductor devices are provided that include a memory cell having load transistors, driver transistors, and transfer transistors. The semiconductor device has a first element-forming region that can be provided in, for example, a p-well region. The first element-forming region can include includes a first active region, a second active region, a third active region, a fourth active region and a fifth active region. The third active region, the fourth active region and the fifth active region can be provided between the first active region and the second active region. The first active region and the second active region can be continuous with the third active region, the fourth active region and the fifth active region, respectively. Thus, semiconductor devices can be provided having element-forming regions that can be readily formed. Memory systems and electronic equipment that include such semiconductor devices can also be provided.

Abstract: The present invention is characterized in comprising a semiconductor substrate, an embedded impurity layer of a first conductive type provided in the semiconductor substrate, a first impurity region of the first conductive type that becomes a first well region provided in the semiconductor substrate above the embedded impurity layer, a second impurity region of a second conductive type, which is an opposite conductive type to the first conductive type, that becomes a second well region provided in the semiconductor substrate in proximity to the first impurity region above the embedded impurity layer, and a third impurity region of the second conductive type that is provided around a region including the first impurity region and the second impurity region in the semiconductor substrate, and that becomes a guard ring region that electrically connects to the second impurity region.

Abstract: Each of a plurality of repeating units comprises a plurality of memory cells. A second-conductivity-type well is formed in a surface layer of a semiconductor substrate extending over the plurality of the repeating units. In the second-conductivity-type well, first-conductivity-type channel MOS transistors of the plurality of the repeating units are provided. A second-conductivity-type well tap region is formed in one of the memory cells in each repeating unit and in the second-conductivity-type well. In the memory cell provided with the second-conductivity-type well tap region or in the memory cell adjacent thereto, an interlayer connection member is provided. The interlayer connection member is connected to the source region of one of the first-conductivity-type channel MOS transistors and to the corresponding second-conductivity-type well tap region.

Abstract: N well contact area 13 is integrally formed with second diffused area 12 within the upper parts of a N well and a P well, and P well contact area 14 is integrally formed with first diffused area 11 in the upper parts of the P well and the N well.

Abstract: A semiconductor device includes an SRAM section and a logic circuit section formed on a single semiconductor substrate. First and second gate electrode layers located in a first conductive layer, first and second drain-drain contact layers located in a second conductive layer, first and second drain-gate contact layers located in a third conductive layer become conductive layers for forming a flip-flop of the SRAM section. The logic circuit section has no wiring layer at the same level as the first and second drain-drain contact layers.

Abstract: A semiconductor memory device includes a trench type SRAM(Static Random Access Memory) cell having a higher integration than a stack type SRAM. The SRAM cell memory device is provided with a trench formed in a semiconductor substrate and having four side walls therein, wherein a source and drain region of a drive transistor is formed in two of the four side walls, respectively, a pair of active layers respectively having a source and drain regions of a first load transistor is formed on the substrate adjacent to the side walls, and a gate electrode common to the load transistor is formed on a gate oxide film, whereby the gate electrode of the access transistor is vertically formed toward a direction vertical to the semiconductor substrate instead of being formed on the substrate for thereby decreasing an area to be occupied by transistor.

Abstract: An SRAM includes first and second access PMOS transistors in an N well region; first and second driver NMOS transistors in a P well region; a word line; and first and second bit lines. Active regions extend in the same direction, polysilicon wirings for forming gates of each of the MOS transistors extend in the same direction, and drains of the first and second access PMOS transistors are connected to drains of the first and second driver NMOS transistors using first metal wirings without interposing the polysilicon wirings forming the gates of the first and second driver NMOS transistors therebetween, respectively.

Abstract: A Scalable Two-Transistor Memory (STTM) cell array having a 4F2 unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

Abstract: A semiconductor device monitor structure is described which can detect localized defects due to floating-body effects, particularly on SOI device wafers. The monitor structure includes a plurality of cells containing PFET or NFET devices, disposed at a perimeter of the structure which is bordered by an insulating region such as shallow trench isolation (STI). Each cell includes polysilicon gate structures having a characteristic spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The cells are constructed in accordance with progressively varying ground rules, so that the first distance and second distance are non-uniform between cells. The cells may be bit fail mapped for single-cell failures, thereby enabling detection of localized defects due to floating-body effects.

Abstract: A memory cell has two cross-coupled inverters each formed from a load transistor and a drive transistor. In the memory cell, the gates of the load transistor and the drive transistor are electrically coupled to the same gate line having a poly-metal gate structure. In the memory cell, a potential change at a storage node corresponding to an output node of one inverter is transmitted to the gate of the load transistor of the other inverter through a contact resistance at the interface between a silicon layer and a metal layer of the poly-metal structure.

Abstract: A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via source/drain regions 14b and 16a, is defined in the lower interlayer insulating film 20. A local wiring 24 is buried in the through hole 22 to connect each gate electrode 14c and the source/drain regions 14b and 16a. Further, an upper interlayer insulating film 26 is provided on the local wiring 24 and the lower interlayer insulating film 20. Upper electrode layers 28 are placed on the surface of the upper interlayer insulating film 26.

Abstract: The semiconductor device according to the present invention comprises side wall 9 formed over the sidewall of gate wiring 6 of a logic SRAM region, doped polysilicon 18 electrically connecting silicide layer 13 formed over the surface of diffused layer 11 and silicide layer 15 of gate wiring 6, W plug 26 electrically connecting doped polysilicon 18 and a first layer aluminum wiring, and W plug 25 electrically connecting the silicide layer over the surface of diffused layer 11 in the logic SRAM region and the first layer aluminum wiring.

Abstract: A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized semiconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.

Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

Abstract: A memory cell (10) is a so-called CMOS type cell. P-wells (W1P, W2P, W3P) and N-wells (W4N, W5N) are formed in a main surface (5S) of a semiconductor substrate (5), and the wells (W2P, W4N, W1P, W5N, W3P) are aligned in this order. Driver transistors (11DN, 12DN) are formed in the wells (W2P, W3P), respectively. Load transistors (11LP, 12LP) are formed in the wells (W4N, W5N), respectively. Two access transistors (11AN, 12AN) are formed in the single well (W1P). N+-type impurity regions (FN30, FN10) constituting one of storage nodes are provided in different wells, and N+-type impurity regions (FN31, FN11) constituting the other of the storage nodes are also provided in different wells.

Abstract: A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

Abstract: A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed. In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak access device constructed in a semiconductor thin film layer located vertically above the strong devices. The strong devices are used in the data read and write paths, and the weak devices are used for latch feed-back and sector data erase. This first embodiment is used for high density and high speed memory applications. In a second embodiment, an SRAM cell comprises thin film inverters and thin film access devices constructed in a semiconductor thin film layer located substantially above logic transistors. The TFT SRAM cell is buried above the logic gates of an Integrated Circuit to consume no extra Silicon real estate. This second embodiment is used for slow access and Look-Up-Tables type memory applications.

Abstract: In accordance with the present invention, the gate length and the gate insulation film thickness are different between the p-channel MOS field effect transistors serving as the driver gates and the n-channel MOS field effect transistors forming the flip flop. Namely, the p-channel MOS field effect transistors serving as the driver gates have a larger gate length and a smaller gate oxide film thickness than the n-channel MOS field effect transistors forming the flip flop.

Abstract: An SRAM includes a plurality of memory cells which are arranged in an extension direction of bit lines, each of which has a long edge and a short edge, an extension direction of the short edge being equal to the extension direction of the bit lines. A distance between polysilicon wirings which are formed in one of the memory cells and which become gates of NMOS transistors arranged in the extension direction of the bit lines, respectively, differs from a distance between the polysilicon wiring and the polysilicon wiring which becomes a gate of an NMOS transistor formed in the other memory cell.

Abstract: A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes a first gate-gate electrode layer and a first drain-gate wiring layer. A distance L1 between the edges of the first drain-gate wiring layer and an active region of the first driver transistor is greater than or equal to a distance L2 between the first drain-gate wiring layer and an active region of the first load transistor. This structure provides semiconductor devices in which memory cells having desired characteristics can be readily fabricated. The invention also provides memory systems and electronic apparatuses which include the above semiconductor devices.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.

Abstract: A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.