Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned.

Abstract: It is an object of the present invention to provide a ferroelectric capacitor which maintains high ferroelecticity. A silicon oxide layer 2, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 10 are formed on a silicon substrate 2. The lower electrode 12 is formed by an alloy layer made of iridium and platinum. The alloy layer of the lower electrode 12 can be formed under appropriate lattice constant correspond with a kind and composition of the ferroelectric layer 8. So that, a ferroelectric layer having excellent ferroelectricity can be obtained. Also, it is possible to prevent vacancy of oxygen in the ferroelectric layer 8.

Abstract: A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.

Abstract: A ferroelectric capacitor comprising an Si substrate, a lower electrode including a metal film containing Ir or Rh and epitaxially grown on the Si substrate, and a conductive oxide film having a perovskite crystal structure and epitaxially grown on the metal film, a perovskite type ferroelectric thin film epitaxially grown on the lower electrode, and an upper electrode formed on the ferroelectric thin film. Alternatively, the lower electrode may be formed of a structure which comprises a silicide film represented by a chemical formula MSi2 (wherein M is at least one kind of transition metal selected from nickel, cobalt and manganese) and epitaxially grown on the Si substrate, a metal film containing Ir or Rh and epitaxially grown on the silicide film, and a conductive oxide film having a perovskite crystal structure and epitaxially grown on the metal film.

Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

Abstract: A field insulating film defines a plurality of active regions disposed regularly in terms of two dimension on the surface of a semiconductor substrate. Each active region includes one bit contact region and subsidiary active regions extending from the bit contact region in four directions. A plurality of first word lines are formed which extend as a whole in a first direction on the semiconductor substrate, and a plurality of second word lines are formed which extend as a whole in a second direction on the semiconductor substrate, crossing the first word lines. Two subsidiary active regions cross the first word lines and remaining two subsidiary active regions cross the second word lines. A plurality of bit lines are formed which extend as a whole in the first and second directions on the semiconductor substrate, crossing each other. Each bit contact region is connected to a corresponding one of the bit lines. Four transistors share one bit contact, and these four transistors have different word lines.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: A pair of semiconductor memory cells comprises active regions having rectangular shapes, arranged in uniform intervals in plan view, said active regions constituting channel regions and source/drain regions of switching transistors; word lines arranged so as to be perpendicular to the active regions; and an extraction electrode connected to a bit line through bit a line contact formed in connection to the active regions constituting the pair of switching transistors.

Abstract: A contact in a semiconductor memory device is formed on an active region of a cell array region, rather than on a sloped area between the cell array region and a core region. Preferably, an insulating layer on the active region is etched to form a hole therein and the contact formed through the hole. Preferably, the etching is performed using an etch solution having a high etch selectivity between the insulating layer and a top layer of the active region. Thus, the contact is evenly formed and the area of the cell array region is reduced, thereby enabling cells to be packed on a chip with high density.

Abstract: A cell-quadropole cell structure is disclosed which extends the principle of sharing the bitline-stud between two different cells (arranged in a one-dimensional line, e.g. w-direction) further to the maximal possible degree of a sharing in a two-dimensional area (x- and y-direction) consequently forming a cross of four cells around one bitline-stud with each drain region and buried strap extended to the side and the trench attached forming a hook like structure.

Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contacts (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate.

Abstract: A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline.

Abstract: An integrated circuit device includes a substrate, an insulating layer on the substrate, and a plurality of parallel conductive lines on the insulating layer. An etch barrier is on each of the parallel conductive lines wherein each of the etch barriers comprises a layer of silicon nitride on a respective conductive line and wherein each of the etch barriers further comprises a layer of silicon on the silicon nitride layer. In addition, the device includes a plurality of conductive vias through the insulating layer providing electrical connection to respective surface portions of the substrate, wherein each of the conductive vias is provided in the insulating layer between the etch barriers.

Abstract: An integrated memory circuit comprises a plurality of memory cells and access transistors; and a digit line comprising conductive tabs extending from at least one side of a conductive digit line. The use of one digit line allows for a reduction in internal noise and coupling between digit line pairs. The use of one digit line also allows for a reduction in array size.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate.

Abstract: A memory device is presented including a memory array having both trench capacitor and stacked capacitor DRAM cells. The trench and stacked capacitor DRAM cells are arranged in a configuration which achieves increased cell density while providing adequate electrical isolation between cells. The increased density of the memory array results in an increase in operational performance and a decrease in cost on a per storage bit basis. The memory array includes electrically conductive bit and word lines. The bit lines are arranged in vertical columns. The trench capacitor DRAM cells are arranged in pairs and aligned along the bit lines. Each pair of trench capacitor DRAM cells shares a common electrical contact to the bit line to which the pair is aligned. Capacitors of the stacked capacitor DRAM cells may be formed above the bit lines.

Abstract: The invention includes several aspects related to semiconductor-on-insulator transistors, to memory and other DRAM circuitry and arrays, to transistor gate arrays, and to methods of fabricating such constructions. In one aspect, a semiconductor-on-insulator transistor includes, a) an insulator layer; b) a layer of semiconductor material over the insulator layer; c) a transistor gate provided within the semiconductor material layer; and d) an outer elevation source/drain diffusion region and an inner elevation diffusion region provided within the semiconductor material layer in operable proximity to the transistor gate. In another aspect, DRAM circuitry includes a plurality of memory cells not requiring sequential access, at least a portion of the plurality having more than two memory cells for a single bit line contact.

Abstract: A memory array includes a semiconductor substrate, an isolation trench disposed in the substrate, and a conductor that is disposed in the trench. The array also includes a memory cell that is coupled to the conductor in the trench. The conductor may be a digit line that is coupled to a source/drain region of the memory cell or to a shared source/drain region of a pair of adjacent memory cells.

Abstract: An integrated memory circuit comprises a plurality of memory cells and access transistors; and a digit line comprising conductive tabs extending from at least one side of a conductive digit line. The use of one digit line allows for a reduction in internal noise and coupling between digit line pairs. The use of one digit line also allows for a reduction in array size.

Abstract: A conducting trench in a dielectric layer can function as both (a) a plurality of contacts and (b) an interconnect in a semiconductor device. The conducting trench may be made by depositing a conductor in a trough formed in a dielectric layer of the device.

Abstract: A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer.

Abstract: N type impurity regions are formed at the surface of N well similarly to a DRAM memory cell. Electrode layers corresponding to storage nodes and conductive layers 9a and 9b corresponding to cell plates are formed for predetermined impurity regions among the impurity regions. Conductive layers are isolated from each other electrically in a DC fashion and connected to electrode nodes VA and VB, respectively. The sets of capacitors formed by a predetermined number of memory cell capacitors connected in parallel through the N well are connected in series. As a result, a capacitor with excellent area efficiency which utilizes the characteristics of the memory cell capacitor can be realized.

Abstract: The gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting together the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer. Alternately, the gate resistance is reduced by utilizing a metal line that shorts all of the gate contacts together, and overlies each of the gates. By reducing the gate resistance, the maximum frequency f.sub.MAX of the multi-finger transistor can be increased.

Abstract: A high density semiconductor memory device includes: a semiconductor substrate; and a plurality of memory cell groups formed on the semiconductor substrate, each of the memory cell groups including a plurality of memory cells having one common source/drain region, wherein when a surface of the semiconductor substrate is divided into a plurality of areas which are arranged in a matrix of rows extending in a first direction and columns extending in a second direction intersecting the first direction, the memory cell groups are selectively arranged in the areas such that the memory cell groups are located in every other one of the areas arranged in each of the rows and also in every other one of the areas arranged in each of the columns.

Abstract: A capacitor optimized for use in an implantable medical device such as an implantable defibrillator is disclosed. In its simplest form, the capacitor comprises a thin planar dielectric sheet that has an array of cells open to one or both sides. Metallization is applied to the surface of the cells such that the walls of adjacent cells form a capacitor with the wall that separates the cells serving as the dielectric. The metallization pattern that forms the electrical connection to the cells may be patterned to limit the allowable current flow to each individual cell, thereby providing a fuse in the case of local dielectric failure.

Abstract: A process is disclosed for forming trenches having high surface-area sidewalls with undulating profiles. Such trenches are formed by first implanting multiple vertically separated layers of dopant in a substrate beneath a region where the trench is to be formed. Next, the trench is formed under conditions chosen to selectively attack highly doped substrate regions (i.e., substrate regions where the dopant has been implanted). The resulting trench sidewalls will have undulations corresponding to the positions of the implanted regions. In one case, the implanted layers contain germanium ions, and a trench is aniostropically etched through the layers of germanium. Thereafter, the trench is subjected to oxidizing conditions to form regions of germanium oxide. Finally, the trench is exposed to an aqueous solvent which dissolves germanium oxide, disrupting the silicon lattice, and leaving gaps or undulations in the sidewall.

Abstract: In a DRAM cell arrangement, two memory cells which include an MOS transistor and a memory element are constructed in each case as a transistor pair (10) whose source areas are connected to one another and to a bitline (11). The MOS transistors have a linear arrangement of the drain area, the gate electrode and the source area which is aligned in the direction of the bitlines (11) and which is arranged essentially below a bitline (11). Adjoining the drain area in each case is a terminal area (13) which is arranged to the side of associated bitlines (11) and via which a cell contact to the memory element is formed. The cell arrangement is particularly suitable for buried-bitline-stacked-capacitor (BBSTC) DRAM cells.

Abstract: A semiconductor memory having memory cells is formed on a semiconductor substrate. Each of the memory cells has a transistor and a capacitor. The transistor includes a channel region, a drain region and a source region aligned in a line and being insulated by an insulation film from an adjacent cell. Each of the memory cells has a gate electrode formed on the channel region with a gate insulating film therebetween. A pad electrode makes electrical contact with one of the source and drain regions of the memory cell and extends over the insulation film. A bit line makes electrical contact with the pad electrode above, extends in parallel to the line and is laterally isolated from one of the source and drain regions. A first insulating film is formed on the semiconductor substrate over the bit line.

Abstract: A semiconductor device includes a buried impurity layer (3) formed at a predetermined depth from a main surface of a semiconductor substrate (1) by utilizing ion injection of a conductivity type determining element, and a gettering layer (2) formed in a position adjacent to and not shallower than the buried impurity layer (3) by utilizing ion injection of an element other than a conductivity type determining element.

Abstract: A structure and method are provided which reduce memory cell size by forming self-formed contacts and self-aligned source lines in the array. In one embodiment of the present invention, a plurality of memory cells are formed in an array. Then, a first insulating layer is deposited on the array, and subsequently etched to form spacers on the sidewalls of each memory cell. Conductive plugs are then formed between adjacent spacers. Subsequently, a second insulating layer is deposited over the array. Finally, drain contacts are formed through the second insulating layer to a first set of plugs. Other plugs form source lines for the array. Because the present invention provides a self-formed contact, only the second insulating layer is etched to establish contact between a metal bit line and an underlying diffused drain region. Thus, the present invention ensures appropriate isolation for each memory cell while reducing the area required for contact formation.

Abstract: Dopant distribution and activation in polysilicon is controlled by implanting electrically neutral atomic species which accumulate along polysilicon grain boundaries. Exemplary atomic species include noble gases and Group IV elements other than silicon.

Abstract: A MOS-FET transistor is produced on a substrate made of glass which has a non single crystal semiconductor film (2'). The average diameter of a crystal grain in said film is in the range between 0.5 times and 4 times of thickness of said film, and said average diameter is 250 .ANG.-8000 .ANG., and said film thickness is 500 .ANG.-2000 .ANG.. The density of oxygen in the semiconductor film (2') is less than 2.times.10.sup.19 /cm.sup.3. A photo sensor having PIN structure is also produced on the substrate, to provide an image sensor for a facsimile transmitter together with the transistors. Said film (2') is produced by placing amorphous silicon film on the glass substrate through CVD process using disilane gas, and effecting solid phase growth to said amorphous silicon film by heating the substrate together with said film in nitrogen gas atmosphere. The film (2') thus produced is subject to implantation of dopant for providing a transistor.

Abstract: A dynamic random access memory includes a plurality of DRAM cell units having a bit contact region and DRAM cells formed on an active region, wherein the DRAM cells each comprised of a transistor and a capacitor connected to the transistor are arranged symmetrically to the right and left sides in a bit contact connected with the active region to form the DRAM cell unit; and the DRAM cell units are arranged with a prescribed pitch in the direction of X and arranged in the direction of Y shifted with one third of the pitch toward the direction of X.

Abstract: A dynamic random access memory having an improved layout capable of having a large storage capacity with a small memory cell area as well as preventing the occurrence of short-circuiting by an increase in the process margin, and a method of arranging memory cells of the same. Each active region includes a first diffusion region, a second diffusion region in common with an adjacent memory cell and a channel forming region located between the first and second diffusion regions. First diffusion regions of adjacent active regions are located at positions symmetrical with respect to the common second diffusion region, at a predetermined angle. Each of uniformly spaced bit lines has a protrusion having a predetermined width and length and extending from its one edge in a direction that the word lines extend. At the protrusion, one second diffusion region is disposed. Uniformly spaced word lines cross bit lines. Each capacitor is positioned between two adjacent bit lines and between two adjacent word lines.

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over the integrated circuit. A nitrogen doped polysilicon layer is formed over the pad oxide layer. A thick nitride layer is then formed over the nitrogen doped polysilicon layer. An opening is formed in the nitride layer and the nitrogen doped polysilicon layer exposing a portion of the pad oxide layer. The nitrogen doped polysilicon layer is annealed encapsulating the polysilicon layer in silicon nitride. A field oxide region is then formed in the opening.

Abstract: The invention relates to a semiconductor memory device in which a bit line ring which functions as a bit line is formed at the upper and lower stage of the bit line and a storage node is formed to be overlapped in the same direction with said bit line formed perpendicularly to a word line to improve the integration degree.Therefore, a capacitor area can be increased without an increase of an area of the unit cell to improve the integration degree of a semiconductor memory device and the generation of the bent portion of the active region can be avoided to decrease the distortion.

Abstract: A transferred electron effect device has a semiconductor body with an active region (2) of n conductivity type formed of a semiconductor material having a relatively low mass, high mobility conduction band main minimum and at least one relatively high mass, low mobility conduction band satellite minimum, and an injection zone (3) adjoining the active region (2) for causing electrons to be emitted, under the influence of an applied electric field, from the injection zone (3) into the active region (2) with an energy comparable to that of the relatively high mass, low mobility, conduction band satellite minima of the active region.

Abstract: A diffused layer is formed in a semiconductor substrate in a connecting region wherein a word line and a shunt thereof are connected to each other, and the word line is also connected to the diffused layer. A junction breakdown voltage between the diffused layer and the semiconductor substrate is not higher than the breakdown voltage of a gate insulating film and is not lower than a maximum voltage applied during a burn-in operation. For this reason, charges accumulated in the word line during a wafer process are easily discharged to the semiconductor substrate through the diffused layer. In addition, since the diffused layer connected to the word line is formed in the connecting region wherein the word line and the shunt thereof are connected to each other, an additional region for the diffused layer is not required. Therefore, variations in characteristics of a transistor, or degradation and breakdown of the gate insulating film can be prevented without a decrease in integration density.