Dram Configuration With Transistors And Capacitors Of Pairs Of Cells Along A Straight Line Between Adjacent Bit Lines Patents (Class 257/908)
  • Patent number: 8969942
    Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshitake Yaegashi, Kazuhiro Shimizu, Seiichi Aritome
  • Patent number: 8878274
    Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: November 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: R. Jacob Baker, Kurt D. Beigel
  • Patent number: 8643110
    Abstract: A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, John K. Zahurak
  • Patent number: 8541828
    Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer includes at least a portion of rutile titanium oxide.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: September 24, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Imran Hashim, Edward L. Haywood, Sandra G. Malhotra, Xiangxin Rui, Sunil Shanker
  • Patent number: 8482045
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Patent number: 8471320
    Abstract: A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: June 25, 2013
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Chung-Lin Huang, Ron Fu Chu
  • Patent number: 8309412
    Abstract: A method for forming a semiconductor device includes: etching a hard mask layer and a conductive layer formed on a semiconductor substrate, a lower structure being formed on the semiconductor substrate; forming a sacrificial insulating layer at upper parts of the etched hard mask layer and the etched conductive layer of a peripheral circuit region; forming an isolation insulating layer at an upper part of an isolation insulating layer of a cell region; forming spacers at sidewalls of the etched hard mask layer, the etched conductive layer, and the isolation insulating layer of the cell region, respectively; forming storage electrode contact plugs at both sides of each of the spacers, respectively; and removing the sacrificial insulating layer to expose the semiconductor substrate of the peripheral circuit region, and etching the lower structure to expose the semiconductor substrate of the peripheral circuit region.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: November 13, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Man Cho
  • Patent number: 8294219
    Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: October 23, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Sandra G. Malhotra, Pragati Kumar, Sean Barstow, Tony Chiang, Prashant B. Phatak, Wen Wu, Sunil Shanker
  • Patent number: 8143723
    Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: March 27, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichiroh Ikemasu, Narumi Okawa
  • Patent number: 8053831
    Abstract: A memory cell of memory device, comprises an active region of a memory cell defined in a semiconductor substrate, and a conductive gate electrode in a trench of the active region. The gate electrode is isolated from the semiconductor substrate. An insulation layer is on the active region and on the conductive gate electrode. A conductive contact is in the insulation layer on the active region at a side of the gate electrode and isolated from the gate electrode. The contact has a first width at a top portion thereof and a second width at a bottom portion thereof, the first width being greater than the second width. The contact is formed of a single-crystal material.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Man-Jong Yu
  • Patent number: 8030697
    Abstract: A cell structure of a semiconductor device includes an active region, having a concave portion, and an inactive region that defines the active region. A gate pattern in the active region is arranged perpendicular to the active region. A landing pad on the active region and the inactive region contacts the active region. A bit line pattern on the inactive region intersects the gate pattern perpendicularly, the bit line pattern being electrically connected to the landing pad and having a first protrusion corresponding to the concave portion of the active region.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Hee Cho, Seung-Bae Park
  • Patent number: 7915692
    Abstract: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the sourcedrain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the sourcedrain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 7876610
    Abstract: A plurality of first transistors formed on a substrate share a gate electrode. Isolation regions isolate the plurality of first transistors from one another. In the region where the plurality of first transistors, an impurity region is formed in such a manner that it includes the source and drain regions of the plurality of first transistors and that the depth of the impurity region is greater than the depth of the source and drain regions. The impurity region sets the threshold voltage of the first transistors.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: January 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Gomikawa, Mitsuhiro Noguchi
  • Patent number: 7816717
    Abstract: A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides of the first gate electrode on the semiconductor substrate, and a ferroelectric capacitor provided above the memory transistor, the ferroelectric capacitor including a first electrode film connected to any one of a source and drain of the memory transistor, a second electrode film connected to the other one of the drain and source of the memory transistor, and a ferroelectric film provided between the first electrode film and the second electrode film, the memory cell section having the memory transistor and the ferroelectric capacitor connected in parallel to each other; and a select transistor section, comprising a select transistor provided at an end of t
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: October 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Ozaki
  • Patent number: 7772065
    Abstract: A semiconductor memory device includes diffusion regions formed in an active region; cell contacts connected to the diffusion regions, respectively; pillars connected to the cell contacts, respectively; a bit line connected to the pillar; capacitor contacts connected to the pillars, respectively; and storage capacitors connected to the capacitor contacts, respectively. Accordingly, the pillars exist between the cell contacts and the capacitor contacts, and thus, depths of the capacitor contacts are made correspondingly shorter. Therefore, it becomes possible to prevent occurrence of shorting defects while decreasing resistance values of the capacitor contacts.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: August 10, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Masahiko Ohuchi
  • Patent number: 7763924
    Abstract: A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: July 27, 2010
    Assignee: Nanya Technology Corp.
    Inventor: Wen-Kuei Huang
  • Patent number: 7700984
    Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: April 20, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventor: Mikio Yukawa
  • Patent number: 7692196
    Abstract: The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate. The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: April 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Sang Jeon, Sang-Bom Kang, Dong-Chan Kim, Chul-Sung Kim, Sug-Hun Hong, Sang-Jin Hyun
  • Patent number: 7663175
    Abstract: A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: February 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kazufumi Komura, Takayoshi Nakamura, Keiichi Fujimura, Masahito Hirose, Keigo Nakashima, Masaki Nagato
  • Patent number: 7649259
    Abstract: A semiconductor device includes a first wiring line group made of a metal, wiring lines of the first wiring line group being arranged in parallel with each other, a second wiring line group which is made of a semiconductor and crosses the first wiring line group, wiring lines of the second wiring line group being arranged in parallel with each other and being movable in the vicinity of each intersection with the wiring lines of the first wiring line group, and a plurality of metal regions which are formed to be joined with the wiring lines constituting the second wiring line group, and have a work function different from that of the metal forming the first wiring line group.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: January 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mizuki Ono, Yuichi Motoi
  • Patent number: 7649261
    Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: January 19, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Shinichiroh Ikemasu, Narumi Okawa
  • Patent number: 7635886
    Abstract: A semiconductor memory is disclosed having an electrically conductive region buried in a substrate, and having an array of first and second cells. The first cells are designed as memory cells each having a selection transistor and a storage capacitor and are connected to word lines and first bit lines. The second cells are designed as switchable contacts each having a selection transistor and a resistance element and are connected to a respective one of the word lines and to a second bit line. The resistance element includes a first electrode and a second electrode, which are conductively connected to one another. The second bit line makes it possible to apply a plate voltage to the buried conductive region in low-impedance fashion via the second cells.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: December 22, 2009
    Assignee: Qimonda AG
    Inventor: Michael Bernhard Sommer
  • Patent number: 7615815
    Abstract: A cell region layout of a semiconductor device formed by adding active regions in the outermost portion of a cell region, and a method of forming a contact pad using the same are provided. The layout and the method include a first active region formed at the outermost portion of the cell region, and having the same shape as that of an inner active region located inwardly from the outermost portion of the cell region, and a third active region formed by adding at least two second active regions having shapes different from that of an inner active region. Further, an insulating layer fills a portion below a bit line passing the third active region. A lifting phenomenon occurring where an active region is not formed can be prevented by adding the active regions at the outermost portion of the cell region, and a bridge phenomenon occurring when bit lines or a bit line contact and a gate line electrically contact can be suppressed by filling a portion below a bit line with an insulating layer.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: November 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Cheol-ho Baek
  • Patent number: 7575992
    Abstract: A method of forming a micro pattern in a semiconductor device is disclosed. An oxide film mask is divided into a cell oxide film mask and a peri oxide film mask. Therefore, a connection between the cell and the peri region can be facilitated. A portion of a top surface of a first oxide film pattern between a region in which a word line will be formed and a region in which a select source line will be formed is removed. Accordingly, the space can be increased and program disturbance in the region in which the word line will be formed can be prevented. Furthermore, a pattern having a line of 50 nm and a space of 100 nm or a pattern having a line of 100 nm and a space of 50 nm, which exceeds the limitation of the ArF exposure equipment, can be formed using a pattern, which has a line of 100 nm and a space of 200 nm and therefore has a good process margin and a good critical dimension regularity.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: August 18, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Woo Yung Jung, Jong Hoon Kim
  • Patent number: 7521763
    Abstract: The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Deok-kee Kim, Seong-Dong Kim, Oh-Jung Kwon
  • Patent number: 7517762
    Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: April 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-yoon Kim, Won-seong Lee, Young-woo Park
  • Patent number: 7518182
    Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: April 14, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Todd R. Abbott, Homer M. Manning
  • Patent number: 7485915
    Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: February 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hayato Nasu, Takamasa Usui, Hideki Shibata
  • Patent number: 7462902
    Abstract: A nonvolatile memory is provided. The memory includes a select transistor and a trench transistor. The select transistor is formed on the substrate. The select transistor includes a first gate formed on the substrate and first and second source/drain regions formed in the substrate next to the first gate. The trench transistor is formed in the substrate. The trench transistor includes a second gate formed in the trench of substrate, an electron trapping layer formed between the second gate and the trench and second and third source/drain regions formed in the substrate next to the second gate. The select transistor and the trench transistor share the second source/drain region.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: December 9, 2008
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Ching-Sung Yang, Wei-Zhe Wong, Chih-Chen Cho
  • Patent number: 7456459
    Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: November 25, 2008
    Assignee: Georgia Tech Research Corporation
    Inventor: Lixi Wan
  • Patent number: 7449742
    Abstract: The present memory device includes first and second electrodes, a passive layer between the first and second electrodes; and an active layer between the first and second electrodes, the active layer being of dendrimeric material which provides passages through the active layer.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: November 11, 2008
    Assignee: Spansion LLC
    Inventors: Igor Sokolik, Juri Krieger, Xiaobo Shi, Richard Kingsborough, William Leonard
  • Patent number: 7375376
    Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: May 20, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Masahiko Hayakawa, Kiyoshi Kato, Mitsuaki Osame, Takashi Hirosue, Saishi Fujikawa
  • Patent number: 7288806
    Abstract: The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact locations. An insulative material can be formed over the etch stop and over the bitline contact locations, and trenches can be formed through the insulative material. Conductive material can be provided within the trenches to form bitline interconnect lines which are in electrical contact with the bitline contact locations, and which are electrically isolated from the storage node contact locations by the etch stop. In subsequent processing, openings can be formed through the etch stop to the storage node contact locations. Memory storage devices can then be formed within the openings and in electrical contact with the storage node contact locations.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: October 30, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Fred D. Fishburn
  • Patent number: 7247902
    Abstract: A semiconductor device comprises a first metal layer, which comprises a buried metal layer connected to a diffusion layer within a substrate or to a lower-layer wiring. A first metal wiring layer, a second metal layer having a buried metal layer, and a second metal wiring layer are sequentially connected. Within a groove passing through insulating layers sandwiching the metal wiring layer from above and below the same as well as on one of the insulating layers there is formed a capacitive element C.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: July 24, 2007
    Assignee: Sony Corporation
    Inventor: Keiichi Ohno
  • Patent number: 7230300
    Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: June 12, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masahito Onda, Hirotoshi Kubo, Shouji Miyahara, Hiroyasu Ishida
  • Patent number: 7211840
    Abstract: A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: May 1, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 7211867
    Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: May 1, 2007
    Assignees: Seiko Instruments Inc., Yutaka Hayashi
    Inventors: Yutaka Hayashi, Hisashi Hasegawa, Yoshifumi Yoshida, Jun Osanai
  • Patent number: 7189586
    Abstract: A test key for monitoring GC-DT misalignment is provided. Deep trench capacitors are embedded in an interlacing matrix manner. GC lines are defined on a substrate and passing over the deep trench capacitors. A first bit line contact pattern surrounded by first assistant bit line contact patterns is disposed on the right side of a first deep trench capacitor. A second bit line contact pattern surrounded by second assistant bit line contact patterns is disposed on the left side of a second deep trench capacitor. The test key has a mirror symmetric line. The first assistant bit line contact patterns and second assistant bit line contact patterns are symmetric with respect to the mirror symmetric line. An active area connects the first bit line contact pattern and the second bit line contact pattern. A signal-in bit line is connected to the first bit line contact and a signal-out bit line is connected to the second bit line contact. The rest rows of the bit lines are dummy bit lines and floating.
    Type: Grant
    Filed: November 21, 2004
    Date of Patent: March 13, 2007
    Assignee: Nanya Technology Corp.
    Inventor: Yu-Chang Lin
  • Patent number: 7135731
    Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: November 14, 2006
    Assignee: Nanya Technology Corp.
    Inventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chi-Hui Lin
  • Patent number: 7126154
    Abstract: A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: October 24, 2006
    Assignee: Infineon Technologies AG
    Inventors: Valentine Rosskopf, Susanne Lachenmann, Sibina Sukman-Prähofer, Andreas Felber
  • Patent number: 7034408
    Abstract: A memory device includes a DRAM memory cell array, which is implemented as a 6 F×F array, and peripheral circuitry. The word lines of the memory cell array are implemented as buried word lines, and, in addition, the bit lines including the bit line contacts are made of a bit line layer stack. The peripheral circuitry includes a peripheral transistor including first and second source/drain regions, a channel connecting the first and the second source/drain regions as well as a peripheral gate electrode for controlling an electrical current of the channel. The peripheral gate electrode is made of a peripheral gate stack including a layer stack which is identical with the bit line stack.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: April 25, 2006
    Assignee: Infineon Technologies, AG
    Inventor: Till Schloesser
  • Patent number: 6974987
    Abstract: A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30. In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18. A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: December 13, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisashi Ogawa, Isao Miyanaga, Koji Eriguchi, Takayuki Yamada, Kazuichiro Itonaga, Yoshihiro Mori
  • Patent number: 6974990
    Abstract: A memory cell includes either a bit line contact feature or a word line space feature that are each characterized by a contact hole bounded by insulating side walls. The contact hole is filled with a conductively doped polysilicon plug defining an upper plug surface profile that is substantially free of concavities.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: December 13, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Luan Tran
  • Patent number: 6967348
    Abstract: A signal sharing circuit includes a first pad adapted to receive a signal and a first sharing device associated with a first microelectronic die. The first sharing device is adapted to selectively share the signal with at least a second microelectronic die on one side of the first microelectronic die in response to a first share control signal.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: November 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Aron T. Lunde
  • Patent number: 6947324
    Abstract: A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: September 20, 2005
    Assignee: Marvell International Ltd.
    Inventors: Winston Lee, Peter Lee, Sehat Sutardja
  • Patent number: 6936881
    Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: August 30, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Chenming Hu
  • Patent number: 6930324
    Abstract: An array process diagnosis test structure for an integrated circuit including a transistor array composed of vertical FET memory cell access transistors, which are formed into the depth of a substrate in the form of active webs which run parallel in the lateral direction of the circuit is disclosed. Memory cell storage capacitors in the array test structure are formed in deep trenches on the end faces of those sections of the active webs which form the vertical FET transistors. Word lines are arranged along the webs and along parallel intersecting bit lines of the array, outside of which, and on two mutually opposite edges, are located a first and second word line comb. The wordline combs are offset and connected alternately to different word lines. In addition, a first and a second bit line comb are formed on the two other opposing edges of the transistor array mutually offset and each connected to different bit lines.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: August 16, 2005
    Assignee: Infineon Technologies AG
    Inventors: Bernhard Kowalski, Andreas Felber, Valentin Rosskopf, Till Schloesser, Juergen Lindolf
  • Patent number: 6906371
    Abstract: A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored by the capacitive region. Each memory unit is accessed by an associated wordline and the data stored by the memory unit is read from an associated bitline connected to the memory unit. The memory units are connected to the associated wordline via a wordline contact and connected to the associated bitline via a bitline contact. The memory units are arranged in memory unit clusters that include multiple memory units having a common bitline contact. The wordline contact is configured to provide for orientation of the wordlines in the memory array independent of the orientation of the bitlines. The wordline contact is also configured to provide for at least one wordline layer separated from the memory unit by a height of the wordline contact.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: June 14, 2005
    Assignee: Infineon Technologies AG
    Inventors: Daivid SuitWai Ma, Guenter Gerstmeier
  • Patent number: 6897481
    Abstract: Embodiments include semiconductor devices and methods of manufacture, one of which includes a capacitor unit formed on a silicon substrate. The capacitor unit is divided into a plurality of capacitor subunits which are partitioned from each other by a separating insulation layer. Each of the capacitor subunits includes a first electrode layer composed of an impurity diffusion layer formed in the silicon substrate, a second electrode layer composed of a conductive polysilicon layer and a dielectric layer composed of a silicon oxide layer interposed between the first electrode layer and the second electrode layer. The respective capacitor subunits are connected in parallel to each other through a connector.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: May 24, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Shogo Inaba
  • Patent number: 6890841
    Abstract: An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: May 10, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-hyun Lee, Tae-young Chung, Chang-hyun Cho, Yang-keun Park, Sang-bum Kim