Containers (epo) Patents (Class 257/E25.031)
  • Patent number: 7282793
    Abstract: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Publication number: 20070229143
    Abstract: The invention relates to a power module comprising a substrate (2), whose surfaces are provided with at least one electrically conductive layer (4, 6), at least one active semiconductor chip (8), which is electrically connected to an electrically conductive layer (6), a film (12) consisting of an electrically conductive material, which is in close contact with the surfaces of the semiconductor chips (8) of the electrically conductive layer (6) and the substrate (2) and is provided with planar printed conductors (16).
    Type: Application
    Filed: April 14, 2005
    Publication date: October 4, 2007
    Applicant: Siemens Aktiengesellschaft
    Inventors: Dieter Eckhardt, Carsten Rebberah
  • Patent number: 7230320
    Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: June 12, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Doi, Noriyoshi Urushiwara, Akira Matsushita
  • Patent number: 7227252
    Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: June 5, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Todd O. Bolken, Chad A. Cobbley
  • Patent number: 7151010
    Abstract: Methods for assembling a stack package for a high density IC module on a PCB include the steps of assembling a first layer of the stack package on the PCB, assembling a second layer of the stack package on the first layer and assembling a third layer of the stack package on the second layer, such that each layer is provided in electrical communication with the PCB. Additional layers may be added to the stack package.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: December 19, 2006
    Assignee: Kyocera Wireless Corp.
    Inventors: Cam T. Nguyen, Sherry Xiaoqi Zhu
  • Patent number: 7148567
    Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a–40e, 41a–41e and 42a–42d), a plurality of LEADs (50a–50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a–60e and 61a–61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a–40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a–50d).
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: December 12, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Moriguchi, Shintaro Mori, Fumihiko Terayama, Hirokazu Komoriya
  • Patent number: 7138726
    Abstract: A package includes a first and a second wafer stored therein in a stacked configuration. The first wafer has interconnection conductor material portions extending from a first surface thereof. The interconnection conductor material portions have a maximum height. An interleaf member is located between the first and second wafers. A first recessed portion is formed in the interleaf member, and it has an outer perimeter shape corresponding to an outer perimeter shape of the first wafer. The first recessed portion has a first depth from a top surface of the interleaf member. A second recessed portion is formed in the interleaf member and located at least partially within the first recessed portion, and it has a bottom surface at a second depth from the top surface. The second depth is greater than the first depth. The second depth minus the first depth is greater than the maximum height.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: November 21, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Gonzalo Amador, Sandra Rodriguez
  • Patent number: 7132746
    Abstract: A process and electronic assembly for conducting heat from a semiconductor circuit device mounted to a substrate. The substrate is supported by a housing member equipped with a heat-conductive member. A surface of the device opposite the substrate is bonded to the heat-conductive member with a solder joint formed of indium and optionally one or more alloying constituents that increase the melting temperature of the solder joint above that of indium. The housing member, substrate, and device are assembled so that an indium-containing solder material is present between the heat-conductive member and the surface of the device opposite the substrate. The solder material is then reflowed to form the solder joint. The alloying constituent(s) are preferably introduced into the solder joint during reflow.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: November 7, 2006
    Assignee: Delphi Technologies, Inc.
    Inventors: Scott D. Brandenburg, Bruce A. Myers
  • Patent number: 7109576
    Abstract: A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the substrate and encapsulated in a first encapsulant, and a second die is back bonded to the first encapsulant. The first encapsulant has a planar surface for attaching the second die, and can also include locking features for the second die. The component also includes a second encapsulant encapsulating the second die and forming a protective body for the component. A method for fabricating the component includes the steps of attaching the first die to the substrate, forming the first encapsulant on the first die, attaching the second die to the first encapsulant, and forming the second encapsulant on the second die.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: September 19, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Todd O. Bolken, Chad A. Cobbley
  • Patent number: RE39628
    Abstract: A stackable flex circuit IC package includes a flex circuit comprised of a flexible base with a conductive pattern thereon, and wrapped around at least one end portion of a frame so as to expose the conductive pattern at the edge portion. An IC device is mounted within a central aperture in the frame, and is electrically coupled to the conductive pattern. The IC device is sealed in place within the frame with epoxy. A stack of the IC packages is assembled by disposing a conductive epoxy of anisotropic material between the conductive patterns at the edge portions of adjacent IC packages. Application of pressure in a vertical or Z-axis direction between adjacent IC packages completes electrical connections between the individual conductors of the conductive patterns of adjacent IC packages to interconnect the IC packages of the stack, while at the same time maintaining electrical isolation between adjacent conductors within each of the conductive patterns.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: May 15, 2007
    Assignee: Stakick Group, L.P.
    Inventor: Harlan R. Isaak