Stackable flex circuit IC package and method of making same
A stackable flex circuit IC package includes a flex circuit comprised of a flexible base with a conductive pattern thereon, and wrapped around at least one end portion of a frame so as to expose the conductive pattern at the edge portion. An IC device is mounted within a central aperture in the frame, and is electrically coupled to the conductive pattern. The IC device is sealed in place within the frame with epoxy. A stack of the IC packages is assembled by disposing a conductive epoxy of anisotropic material between the conductive patterns at the edge portions of adjacent IC packages. Application of pressure in a vertical or Z-axis direction between adjacent IC packages completes electrical connections between the individual conductors of the conductive patterns of adjacent IC packages to interconnect the IC packages of the stack, while at the same time maintaining electrical isolation between adjacent conductors within each of the conductive patterns. The IC devices may comprise bare memory chips electrically coupled to the conductive pattern by wire bonds which are encapsulated in the epoxy together with the chip. Alternatively, where the IC devices comprise ball grid array (BGA) devices, such as chip scale packages, μBGAs, flip chips, or the like, the matrix of balls or other conductive elements on the device are disposed within apertures ablated through the flexible base of the flex circuit where they are soldered to the conductive pattern. A method of making the stackable flex circuit IC package secures the frame onto the flex circuit so that the flex circuit is wrapped around at least one end of the frame, secures the IC device to the flex circuit within the opening in the frame, electrically couples the IC device to the conductive pattern on the flex circuit, either by wire bonding in the case of a bare chip or by soldering the matrix of balls or other conductive elements to the conductive pattern of the flex circuit in the case of a BGA device, and then encapsulates the device with epoxy. A stack of the IC packages is formed by placing anisotropic conductive epoxy between the exposed conductive patterns of adjacent IC packages and pressing the IC packages together.
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This is a division of Ser. No. 09/305,584 filed May 5, 1999 now U.S. Pat. No. 6,323,060.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to stacks in which a plurality of integrated circuit (IC) packages arranged in a stack are electrically connected in a desired fashion, and to methods of making such stacks.
2. History of the Prior Art
Various common approaches are used to increase memory capacity on a circuit board. Larger memory IC devices such as chips can be used, if available. The size of the circuit board can be increased in order to hold more IC chips. Vertical plug-in boards can be used to increase the height of the mother board. The memory devices can be stacked in pancake style (sometimes referred to as 3D packaging or Z-Stacking). The Z-Stacking approach interconnects from 2 to as many as 8 chips in a single component which can be mounted on the “footprint” of a single package device. This approach is the most volumetrically efficient. Package chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form have been used for stacking, and are perhaps the easiest to use. Bare chips or dies have also been used, but the process for forming a stack thereof tends to be complex and not well adapted to automation.
In forming a stack of IC chips such as memory chips, the chips must be formed into a stack and at the same time must be electrically interconnected in the desired fashion. Typically, the chips, which are mounted within packages therefor, have most of the electrical contacts thereof coupled in common or in parallel to contacts on a supporting substrate, and several unique contacts which are coupled individually to the substrate to the exclusion of the other chips. The prior art includes various different arrangements for electrically interconnecting the IC chips in a stack. For example, electrical conductors which may comprise thin film metal on an insulating base may be disposed perpendicular to the planes of the planar chips so as to connect those conductors on each chip which are exposed through openings in an insulating layer. Where the chip packages are assembled into a stack, electrical connections may be accomplished by lead frames or solder strips extending along the sides of the stack and attached to the electrical contacts of the chips.
Another common technique for providing the desired electrical interconnections in a chip stack is to form a stack of chips having bonding pads disposed on the chips adjacent the outer edges thereof. After assembling the stack of chips, the chip edges are ground flat and polished before sputtering an insulating layer thereon. The bonding pads on the edges of the chips are masked during the sputtering process to avoid covering them with the insulating layer. Next, a metal layer is sputtered onto the entire edge of the stack in conjunction with photomasking which forms conductive traces of the metal layer in desired locations for connecting the bonding pads.
Further examples of vertical stacks of IC chips and various methods of making such stacks are provided by U.S. Pat. Nos. 4,956,694, 5,313,096 and 5,612,570, which patents are commonly assigned with the present application. U.S. Pat. Nos. 5,612,570, which issued Mar. 18, 1997 and is entitled CHIP STACK AND METHOD OF MAKING THE SAME, describes a chip stack and a method for making the same in which chip packages are first assembled by mounting plastic packaged chips or thin, small outline package chips (TSOPs) within the central apertures of thin, planar frames having a thickness similar to the thickness of the packaged chip. Leads at opposite ends of the package are soldered to conductive pads on the upper surface of the surrounding frame. Each frame also has other conductive pads on the upper and lower surface thereof adjacent the outer edges of the frame, which are coupled to the conductive pads that receive the leads of the packaged chip by conductive traces and vias. A chip stack is then formed by stacking together a plurality of the chip packages and dipping the upper edges of the stack into molten solder to solder together the conductive pads adjacent the outer edges of the frames. The conductive pads adjacent the outer edges of the frame can be interconnected in a stair step arrangement, and pads on opposite sides of each frame can be coupled in offset fashion using vias, in order to achieve desired electrical interconnections of the various chips.
A still further example is provided by copending application Ser. No. 08/935,216, filed Sep. 22, 1987 and entitled CHIP STACK AND METHOD OF MAKING SAME. Such application, which is commonly assigned with the present application, describes formation of a stack of ball grid array IC packages by assembling a ribbon-like structure of thin, planar bases, each with plural terminals and an interconnecting conductive pattern thereon, and with the bases electrically interconnected by flex circuits extending therebetween. A different IC package is mounted on each base by soldering the balls of a ball grid array thereon to the terminals of the base. The bases alternate in orientation, so that alternate IC packages are joined to the tops and bottoms of the bases. The resulting arrangement is then folded over on itself, with IC packages being joined to adjacent bases using adhesive. The resulting chip stack is mounted on a substrate by soldering the balls of the ball grid array at the underside of the lowermost base at the bottom of the stack to the substrate. The conductive patterns on the bases and the interconnecting flex circuits form conductive pads which contact selected terminals of the various IC packages as the pads extend in alternating fashion through the stack between opposite sides of the stack.
A still further example is provided by copending application Ser. No. 08/971,499, filed Nov. 17, 1997 and entitled METHOD OF MAKING CHIP STACKS. Such application, which is commonly assigned with the present application, describes the making of a chip stack which begins with the formation of a plurality of panels having apertures therein and conductive pads on opposite sides thereof. Solder paste is deposited on the conductive pads prior to mounting plastic packaged IC chips within each of the apertures in each of the panels so that opposite leads thereof reside on the conductive pads at opposite sides of the apertures. The plural panels are then assembled into a stack, such as by use of a tooling jig which aligns the various panels and holds them together in compressed fashion. The assembled panel stack is heated so that the conductive paste solders the leads of the packaged chips to the conductive pads and interfacing conductive pads of adjacent panels together, to form a panel stack comprised of a plurality of chip package stacks. Following cleaning of the panel stack to remove solder flux residue, the individual chip package stacks are separated from the panel stack by cutting and breaking the stack. Score lines across the topmost panel and transverse slots within remaining panels therebelow result in the formation of strips of chip package stacks when longitudinal cuts are made through the panel stack. The remaining portions of the uppermost panel within such strips are then snapped along the score lines thereof to separate the individual chip package stacks from the strips.
A still further example is provided by copending application Serial No. 09/073,254, filed May 5, 1998 and entitled CHIP STACK AND METHOD OF MAKING SAME. Such application, which is commonly assigned with the present application, describes a stackable carrier made from plural layers of Kapton or other plastic material, and which may be made using conventional flex circuit techniques. The stackable carrier has a central opening, a plurality of stacking apertures extending through the thickness thereof between opposite surfaces of the carrier and a conductive pattern therein which extends between the central opening and the stacking apertures. An IC device is mounted within the central opening, and is electrically coupled to the conductive pattern such as by wire bonding or by soldering a ball grid array or other arrangement of contacts on the device directly to the conductive pattern, and is encapsulated therein with potting compound using conventional chip-on-board encapsulation technology, to form a single layer integrated circuit element. Conductive elements such as metallic balls are inserted into the stacking apertures, and are mounted therein using solder or conductive epoxy, so as to electrically contact the conductive pattern and form a stackable IC package. A stack of the IC packages is assembled by arranging a stack of the packages so that the metallic balls which protrude from a surface of each package are inserted into the stacking apertures of an adjacent package, where they are electrically and mechanically secured by solder or conductive epoxy. Balls mounted within the stacking apertures of a lowermost one of the IC packages protrude from the bottom surface thereof, so that the completed stack forms a ball grid array product.
The various arrangements and methods described in the patents and patent applications noted above have been found to provide IC package stacks and methods which are advantageous and which are suited for many applications. Nevertheless, the provision of further alternative arrangements and methods would be advantageous. In particular, it would be advantageous to provide IC package stacks and methods of making such stacks which utilize available materials and known process techniques, including particularly flex circuit technology. The assembly of such stacks should lend itself to automated production methods, and thus be competitive with other stacking approaches.
BRIEF SUMMARY OF THE INVENTIONThe foregoing objects and features are achieved in accordance with the invention by an IC package stack and method of making the same which uses available materials and known process techniques and in which automated production methods can be used. A stackable flex circuit IC package in accordance with the invention includes an IC device and a flex circuit comprised of a flexible base with a conductive pattern disposed thereon. The IC device is mounted within a central aperture in a frame, and the flex circuit is wrapped around at least one end portion of the frame so as to expose the conductive pattern thereat. The IC device is electrically coupled to the conductive pattern. The conductive pattern of the flex circuit is comprised of a plurality of spaced-apart conductors. A stack of the stackable flex circuit IC packages may be formed, and the plurality of spaced-apart conductors of the flex circuits of adjacent IC packages are electrically coupled, such as by use of anisotropic conductive epoxy. By pressing the adjacent IC packages together, the conductive epoxy forms connections between the adjacent IC packages in a vertical or Z-axis direction while maintaining the spaced-apart conductors of the conductive pattern within each flex circuit electrically isolated from one another.
When the IC devices comprise bare chips, the chip is electrically coupled to the conductive pattern of the flex circuit using wire bonds coupled between conductive pads of the chip and the conductive pattern of the flex circuit. A potting compound is applied to encapsulate the chip and the wire bonds within the frame. Alternatively, the IC devices may comprise BGA (Ball Grid Array) devices, such as chip scale packages, μBGAs, flip chips, and the like, in which event an array of ball contacts or other conductive elements of the BGA device are disposed within apertures, formed such as by ablation, through the flexible base of the flex circuit. The balls of the grid pattern are soldered to the conductive pattern of the flex circuit to accomplish the electrical coupling. A potting compound is used to underfill a space between the surface of the chip having the ball grid array of contacts and the flexible base of the flex circuit.
Where the stackable flex circuit IC package has a bare chip mounted within a central aperture in the frame, the frame may be of elongated configuration with opposite ends of the flex circuit being mounted on the opposite step down ends of the frame so as to extend thereover and expose the conductive pattern at each of such opposite ends of the frame. Where a stack of the IC packages is assembled, a lowermost one of the packages in the stack may be provided with a plurality of contacts on the conductive pattern at each of the opposite ends to facilitate coupling and electrical interconnection of the stack to a substrate board. Within each IC package, the flex circuit extends across the central aperture in the frame, and the IC device is secured thereto within the aperture. Alternatively, in order to provide a thinner IC package, the flex circuit may be provided with a central aperture therein in the region of the central aperture in the frame. The IC device is disposed in the central aperture of the flex circuit so that a bottom surface of the IC device is generally coplanar with an adjacent lower surface of the flex circuit opposite the frame.
Where the IC package is formed using a BGA device, a central portion of the flex circuit has a plurality of holes ablated or otherwise formed therethrough in an array which corresponds with an array of conductive elements on the device. The conductive pattern is formed on the flex circuit so as to extend between the holes and four opposite edges of the flex circuit. After securing the frame to the flex circuit and the device to the flex circuit and mounting the device within the central aperture in the frame, the array of balls or other conductive elements at the bottom of the device are soldered to the conductive pattern on the flex circuit, with the balls disposed within the apertures in the flex circuit. The four opposite sides of the flex circuit are then wrapped over and bonded such as by adhesive to the frame, exposing the conductive pattern at the four edges of the frame. Upon stacking such IC packages, conductive epoxy such as anisotropic conductive epoxy is applied to the exposed conductive pattern at the four sides of the frame, and the application of pressure between adjacent IC packages completes the electrical interconnections between the individual conductors of the conductive pattern of adjacent IC packages.
A method of making a stackable flex circuit IC package in accordance with the invention includes the steps of providing a flex circuit with a conductive pattern thereon and providing a frame having an opening therein. The frame is secured onto the flex circuit so that the flex circuit is wrapped around at least one end of the frame to expose the conductive pattern at the at least one end. An IC device is secured to the flex circuit within the opening in the frame, and the device is electrically coupled to the conductive pattern on the flex circuit. The device is then encapsulated with epoxy. The flex circuit may be formed by sputtering or otherwise depositing a conductive layer on a layer of thin flexible base, followed by etching of the layer to form a desired conductive pattern. Where a bare chip is used, the electrical interconnection is accomplished by wire bonding the conductive pads of the chip to the conductive pattern of the flex circuit. In that event, the wire bonds are encapsulated as part of the step of encapsulating the chip with epoxy.
Where the IC package uses a BGA device, the step of providing a flex circuit includes forming a matrix of holes through the flexible base to the conductive pattern of the flex circuit. The ball grid array or other conductive elements of the device are disposed within the matrix of holes and coupled to the conductive pattern such as by soldering. A space between the circuit and the device is underfilled with epoxy. Thereafter, a frame having an opening therein is placed over the chip and is attached to the flex circuit, such as by adhesive. The opposite edges of the flex circuit are then folded over the frame and are bonded, again such as by adhesive.
A detailed description of the invention will be made with reference to the accompanying drawings, in which:
While the flex circuit 12 is shown and described as having the conductive pattern 20 on only one side of the flexible base 32, the conductive pattern can be placed on both sides where desired to achieve various chip package configurations. As described hereafter, a laser can be used to ablate holes through the base 32 which covers portions of the conductive pattern 20. When the base 32 is ablated through, the copper of the conductive pattern 20 reflects the laser so as to be unaffected thereby.
As shown in
In a third step 46 of the method of
In a fourth step 48 of the method of
In a fifth step 54 of the method of
In a sixth step 56 of the method of
In a seventh step 60 of the method of
It will be appreciated by those skilled in the art that the stackable flex circuit IC package 10 utilizes readily available materials and well developed process techniques. The essence of the IC package 10 is the flex circuit 12 which routes connections from the chip 50 to peripheral positions at the ends 14 and 16 of the frame 18, allowing the IC package 10 to be stacked.
To enable the stack of IC packages 10 shown in
In a fourth step 132 of the method of
As previously described, the conductive pattern 112 is comprised of the individual conductors 116 as shown in FIG. 19. With the BGA device 104 mounted on the flex circuit 102, the individual balls 106 are soldered to contacts at the ends of the conductors 116. In this manner, the BGA device 104 is electrically coupled to parts of the conductive pattern 112 at the end portions 120, 122, 124 and 126 of the thin flexible base 114 of the flex circuit 102.
As an alternative to soldering the balls 106 to the conductive pattern 112 and then underfilling with epoxy, an anisotropic adhesive can be used. The adhesive is spread on the flex circuit 102, and the BGA device 104 is then placed thereon and cured. This connects the balls 106 to the circuit 102 and bonds the BGA device 104 to the flex circuit.
In a sixth step 140 of the method of
In an eighth and final step 148 of the method of
The arrangement of
While the stackable flex circuit IC packages described herein have a single IC device mounted therein, it will be apparent that packages can be assembled with more than one IC device therein. In such instances, the plural IC devices can be interconnected using multilayered flex circuits. Also, transposer layers can be made as an integral part of the flex circuit of each carrier or as separate boards between carriers when stacking carriers.
While the invention has been shown with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims
1. A stackable integrated circuit chip package, comprising:
- a flex circuit comprising: a flexible base; and a conductive pattern disposed on the flexible base;
- a frame defining a central opening and opposed top and bottom surfaces, the flex circuit being wrapped around at least a portion of and secured to the frame such that the, conductive pattern defines a first portion which extends over a portion of the bottom surface of the frame and a second portion which extends over a portion of the top surface of the frame; and
- an integrated circuit device disposed within the opening of the frame and secured to the flexible base of the flex circuit, the integrated circuit device being electrically connected to the conductive pattern;
- the first and second portions of the conductive pattern each being electrically connectable to another component.
2. The chip package of claim 1 further in combination with a second stackable integrated circuit chip package identically configured to the chip package, the first portion of the conductive pattern of the second chip package being electrically connected to the second portion of the conductive pattern of the chip package to form a chip stack.
3. The chip stack of claim 2 wherein the first portion of the conductive pattern of the second chip package is electrically connected to the second portion of the conductive pattern of the chip package through the use of an anisotropic conductive epoxy.
4. The chip package of claim 1 wherein:
- the integrated circuit device comprises a bare die; and
- the bare die is electrically connected to the second portion of the conductive pattern via at least one conductive wire.
5. The chip package of claim 4 wherein:
- the top surface of the frame defines at least one ramp which is recessed relative to the remainder thereof;
- a portion of the second portion of the conductive pattern extends over the ramp; and
- the bare die is electrically connected via the conductive wire to the portion of the second portion of the conductive pattern which extends over the ramp.
6. The chip package of claim 5 further comprising a potting compound encapsulating the bare die and the at least one conductive wire within the central opening of the frame.
7. The chip package of claim 1 wherein:
- the integrated circuit device comprises a BGA device including a body having an array of contacts disposed thereon;
- the flexible base of the flex circuit includes a plurality of apertures extending therethrough to the first portion of the conductive pattern; and
- the contacts of the BGA device are disposed within respective ones of the apertures and electrically connected to the first portion of the conductive pattern.
8. The chip package of claim 7 wherein the contacts are electrically connected to the first portion of the conductive pattern via solder.
9. The chip package of claim 7 further comprising a potting compound underfilling a gap defined between the body of the BGA device and the flexible base of the flex circuit.
10. The chip stack of claim 1 wherein the flexible base extends across and completely covers one end of the central opening within the frame.
11. A chip stack comprising:
- at least first and second stackable integrated circuit chip packages, each of which comprises: a flex circuit comprising: a flexible base; and a conductive pattern disposed on the flexible base; a frame defining a central opening, the flex circuit being wrapped around at least a portion of and secured to the frame such that the conductive pattern defines a first portion which extends over a portion of the bottom surface of the frame and a second portion which extends over a portion of the top surface of the frame; and an integrated circuit device disposed within the opening of the frame and secured to the flexible base of the flex circuit, the integrated circuit device being electrically connected to the conductive pattern; the first portion of the conductive pattern of the second chip package being electrically connected to the second portion of the conductive pattern of the first chip package.
12. The chip stack of claim 11 wherein the first portion of the conductive pattern of the first chip package is electrically connected to the second portion of the conductive pattern of the second chip package-via an anisotropic epoxy.
13. The chip stack of claim 11 wherein the second chip package includes a plurality of contacts on the first portion of the conductive pattern thereof to facilitate electrical connection to a substrate board.
14. A stackable integrated circuit chip package, comprising:
- a flex circuit comprising: a flexible base having a central aperture therein; and a conductive pattern disposed on the flexible base;
- a frame defining a central opening and opposed top and bottom surfaces, the flex circuit being wrapped around at least a portion of and secured to the frame such that the conductive pattern defines a first portion which extends over a portion of the bottom surface of the frame and a second portion which extends over a portion of the top surface of the frame; and
- an integrated circuit device disposed within the central aperture of the flexible base and the central opening of the frame, the integrated circuit device being electrically connected to the conductive pattern;
- the first and second portions of the conductive pattern each being electrically connectable to another component.
15. The chip package of claim 14 further in combination with a second stackable integrated circuit chip package identically configured to the chip package, the first portion of the conductive pattern of the second chip package being electrically connected to the second portion of the conductive pattern of the chip package to form a chip stack.
16. The chip stack of claim 15 wherein the first portion of the conductive pattern of the second chip package is electrically connected to the second portion of the conductive pattern of the chip package through the use of an anisotropic conductive epoxy.
17. The chip package of claim 14 wherein:
- the integrated circuit device comprises a bare die; and
- the bare die is electrically connected to the second portion of the conductive pattern via at least one conductive wire.
18. The chip package of claim 17 wherein:
- the top surface of the frame defines at least one ramp which is recessed relative to the remainder thereof;
- a portion of the second portion of the conductive pattern extends over the ramp; and
- the bare die is electrically connected via the conductive wire to the portion. of the second portion of the conductive pattern which extends over the ramp.
19. The chip package of claim 18 further comprising a potting compound partially encapsulating the bare die and-the at least one conductive wire within the central aperture of the flexible base and the central opening of the frame.
20. A stacked integrated circuit module comprising:
- a first ball grid array package having a first major surface and a second major surface and emergent from the second major surface there being a first matrix of balls, the first ball grid array package containing an integrated circuit chip;
- a second ball grid array package having a first major surface and a second major surface and containing an integrated circuit chip, the second ball grid array package being disposed in a stacked disposition above the first ball grid array package;
- a flex circuit connected on one side to the first matrix of balls of the first ball grid array package and connected on the other side to a second matrix of balls for the module the flex circuit further comprising a first portion and a second portion with the first and second portions being coplanarly disposed above the first major surface of the first ball grid array package and below the second major surface of the second ball grid array package, the first and second portions being electrically connected to the second ball grid array package.
3411122 | November 1968 | Schiller et al. |
3436604 | April 1969 | Hyltin |
3654394 | April 1972 | Gordon |
3723977 | March 1973 | Schaufele |
3746934 | July 1973 | Stein |
3766439 | October 1973 | Isaacson |
3772776 | November 1973 | Weisenburger |
3983547 | September 28, 1976 | Almasi |
4079511 | March 21, 1978 | Grabbe |
4288841 | September 8, 1981 | Gogal |
4406508 | September 27, 1983 | Sadigh-Behzadi |
4513368 | April 23, 1985 | Houseman |
4587596 | May 6, 1986 | Bunnell |
4645944 | February 24, 1987 | Uya |
4696525 | September 29, 1987 | Coller et al. |
4712129 | December 8, 1987 | Orcutt |
4722691 | February 2, 1988 | Gladd et al. |
4733461 | March 29, 1988 | Nakano |
4758875 | July 19, 1988 | Fujisawa et al. |
4763188 | August 9, 1988 | Johnson |
4821007 | April 11, 1989 | Fields et al. |
4823234 | April 18, 1989 | Konishi et al. |
4833568 | May 23, 1989 | Berhold |
4839717 | June 13, 1989 | Phy et al. |
4862249 | August 29, 1989 | Carlson |
4891789 | January 2, 1990 | Quattrini et al. |
4911643 | March 27, 1990 | Perry et al. |
4953060 | August 28, 1990 | Lauffer et al. |
4956694 | September 11, 1990 | Eide |
4983533 | January 8, 1991 | Go |
4985703 | January 15, 1991 | Kaneyama |
5012323 | April 30, 1991 | Farnworth |
5016138 | May 14, 1991 | Woodman |
5034350 | July 23, 1991 | Marchisi |
5041015 | August 20, 1991 | Travis |
5041902 | August 20, 1991 | McShane |
5057903 | October 15, 1991 | Olla |
5064762 | November 12, 1991 | Nishiguchi |
5068708 | November 26, 1991 | Newman |
5081067 | January 14, 1992 | Shimizu et al. |
5099393 | March 24, 1992 | Bentlage et al. |
5104820 | April 14, 1992 | Go et al. |
5117282 | May 26, 1992 | Salatino |
5122862 | June 16, 1992 | Kajihara et al. |
5138430 | August 11, 1992 | Gow, 3rd et al. |
5138434 | August 11, 1992 | Wood et al. |
5158912 | October 27, 1992 | Kellerman et al. |
5159434 | October 27, 1992 | Kohno et al. |
5159535 | October 27, 1992 | Desai et al. |
5168926 | December 8, 1992 | Watson et al. |
5198888 | March 30, 1993 | Sugano et al. |
5198965 | March 30, 1993 | Curtis et al. |
5214307 | May 25, 1993 | Davis |
5219794 | June 15, 1993 | Satoh et al. |
5222014 | June 22, 1993 | Lin |
5224023 | June 29, 1993 | Smith et al. |
5229916 | July 20, 1993 | Frankeny et al. |
5239198 | August 24, 1993 | Lin et al. |
5240588 | August 31, 1993 | Uchida |
5241454 | August 31, 1993 | Ameen et al. |
5243133 | September 7, 1993 | Engle et al. |
5247423 | September 21, 1993 | Lin et al. |
5252855 | October 12, 1993 | Ogawa et al. |
5252857 | October 12, 1993 | Kane et al. |
5259770 | November 9, 1993 | Bates et al. |
5261068 | November 9, 1993 | Gaskins et al. |
5262927 | November 16, 1993 | Chia et al. |
5276418 | January 4, 1994 | Klosowiak et al. |
5281852 | January 25, 1994 | Normington |
5289062 | February 22, 1994 | Wyland |
5313097 | May 17, 1994 | Haj-Ali-Ahmadi et al. |
4437235 | March 20, 1984 | Burns |
5347428 | September 13, 1994 | Carson et al. |
5357478 | October 18, 1994 | Kikuda et al. |
5361228 | November 1, 1994 | Adachi et al. |
5375041 | December 20, 1994 | McMahon |
5386341 | January 31, 1995 | Olson et al. |
5394303 | February 28, 1995 | Yamaji |
5397916 | March 14, 1995 | Normington |
5428190 | June 27, 1995 | Stopperan |
5438224 | August 1, 1995 | Papageorge et al. |
5448511 | September 5, 1995 | Paurus et al. |
5477082 | December 19, 1995 | Buckley, III et al. |
5484959 | January 16, 1996 | Burns |
5502333 | March 26, 1996 | Bertin et al. |
5523619 | June 4, 1996 | McAllister et al. |
5523695 | June 4, 1996 | Lin |
5572065 | November 5, 1996 | Burns |
5588205 | December 31, 1996 | Roane |
5594275 | January 14, 1997 | Kwon et al. |
5612570 | March 18, 1997 | Eide et al. |
5631193 | May 20, 1997 | Burns |
5642055 | June 24, 1997 | Difrancesco |
5646446 | July 8, 1997 | Nicewarner et al. |
5654877 | August 5, 1997 | Burns |
5657537 | August 19, 1997 | Saia et al. |
5677569 | October 14, 1997 | Choi et al. |
5729894 | March 24, 1998 | Rostoker et al. |
5744827 | April 28, 1998 | Jeong et al. |
5751553 | May 12, 1998 | Clayton |
5763296 | June 9, 1998 | Casati et al. |
5764497 | June 9, 1998 | Mizumo et al. |
5776797 | July 7, 1998 | Nicewarner, Jr. et al. |
5778522 | July 14, 1998 | Burns |
5778552 | July 14, 1998 | Burns |
5783464 | July 21, 1998 | Burns |
5789815 | August 4, 1998 | Tessler et al. |
5801439 | September 1, 1998 | Fujisawa et al. |
5804870 | September 8, 1998 | Burns |
5805422 | September 8, 1998 | Otake et al. |
5835988 | November 10, 1998 | Ishii |
5841721 | November 24, 1998 | Kwon et al. |
5869353 | February 9, 1999 | Levy et al. |
5895970 | April 20, 1999 | Miyoshi |
5899705 | May 4, 1999 | Akram |
5917709 | June 29, 1999 | Johnson et al. |
5922061 | July 13, 1999 | Robinson |
5925934 | July 20, 1999 | Lim |
5926369 | July 20, 1999 | Ingraham et al. |
5949657 | September 7, 1999 | Karabatsos |
5950304 | September 14, 1999 | Khandros et al. |
5953215 | September 14, 1999 | Karabatsos |
5959839 | September 28, 1999 | Gates |
5963427 | October 5, 1999 | Bolleson |
5973395 | October 26, 1999 | Suzuki et al. |
5989982 | November 23, 1999 | Yoshikazu |
5995370 | November 30, 1999 | Nakamori |
6002167 | December 14, 1999 | Hatano et al. |
6002589 | December 14, 1999 | Perino et al. |
6014316 | January 11, 2000 | Eide |
6028352 | February 22, 2000 | Eide |
6028365 | February 22, 2000 | Akram et al. |
6034878 | March 7, 2000 | Osaka et al. |
6040624 | March 21, 2000 | Chambers et al. |
6072233 | June 6, 2000 | Corisis et al. |
6084293 | July 4, 2000 | Ohuchi |
6084294 | July 4, 2000 | Tomita |
6097087 | August 1, 2000 | Farnworth et al. |
6121676 | September 19, 2000 | Solberg |
RE36916 | October 17, 2000 | Moshayedi |
6157541 | December 5, 2000 | Hacke |
6165817 | December 26, 2000 | Akram |
6172874 | January 9, 2001 | Bartilson |
6178093 | January 23, 2001 | Bhatt et al. |
6187652 | February 13, 2001 | Chou et al. |
6205654 | March 27, 2001 | Burns |
6208521 | March 27, 2001 | Nakatsuka |
6222737 | April 24, 2001 | Ross |
6225688 | May 1, 2001 | Kim et al. |
6233650 | May 15, 2001 | Johnson et al. |
6234820 | May 22, 2001 | Perino et al. |
6246114 | June 12, 2001 | Takahashi et al. |
6262895 | July 17, 2001 | Forthun |
6265660 | July 24, 2001 | Tandy |
6266252 | July 24, 2001 | Karabatsos |
6281577 | August 28, 2001 | Oppermann et al. |
6285560 | September 4, 2001 | Lyne |
6288907 | September 11, 2001 | Burns |
6300679 | October 9, 2001 | Mukerji et al. |
6303981 | October 16, 2001 | Moden |
6310392 | October 30, 2001 | Burns |
6313998 | November 6, 2001 | Kledzik |
6316825 | November 13, 2001 | Park et al. |
6323060 | November 27, 2001 | Isaak |
6329708 | December 11, 2001 | Komiyama |
6336262 | January 8, 2002 | Dalal et al. |
6351029 | February 26, 2002 | Isaak |
6360433 | March 26, 2002 | Ross |
6368896 | April 9, 2002 | Farnworth et al. |
6376769 | April 23, 2002 | Chung |
6392162 | May 21, 2002 | Karabatsos |
6410857 | June 25, 2002 | Gonya |
6426240 | July 30, 2002 | Isaak |
6426549 | July 30, 2002 | Isaak |
6426560 | July 30, 2002 | Kawamura et al. |
6433418 | August 13, 2002 | Fujisawa et al. |
6444490 | September 3, 2002 | Bertin et al. |
6444921 | September 3, 2002 | Wang et al. |
6446158 | September 3, 2002 | Karabatsos |
6449159 | September 10, 2002 | Haba |
6452826 | September 17, 2002 | Kim et al. |
6462412 | October 8, 2002 | Kamei et al. |
6465877 | October 15, 2002 | Farnworth et al. |
6465893 | October 15, 2002 | Khandros et al. |
6473308 | October 29, 2002 | Forthun |
6486544 | November 26, 2002 | Hashimoto |
6489178 | December 3, 2002 | Coyle et al. |
6489687 | December 3, 2002 | Hashimoto |
6492718 | December 10, 2002 | Ohmori |
6509639 | January 21, 2003 | Lin |
6514793 | February 4, 2003 | Isaak |
6528870 | March 4, 2003 | Fukatsu et al. |
6552910 | April 22, 2003 | Moon et al. |
6560117 | May 6, 2003 | Moon |
6572387 | June 3, 2003 | Burns et al. |
6576992 | June 10, 2003 | Cady et al. |
6588095 | July 8, 2003 | Pan |
6590282 | July 8, 2003 | Wang et al. |
6600222 | July 29, 2003 | Levardo |
6614664 | September 2, 2003 | Lee |
6620651 | September 16, 2003 | He et al. |
6627984 | September 30, 2003 | Bruce et al. |
6627997 | September 30, 2003 | Eguchi et al. |
6657134 | December 2, 2003 | Spielberger et al. |
6660561 | December 9, 2003 | Forthun |
6677670 | January 13, 2004 | Kondo |
6683377 | January 27, 2004 | Shim et al. |
6690584 | February 10, 2004 | Uzuka et al. |
6699730 | March 2, 2004 | Kim et al. |
6707684 | March 16, 2004 | Andric et al. |
6709893 | March 23, 2004 | Moden et al. |
6768660 | July 27, 2004 | Kong et al. |
6781240 | August 24, 2004 | Choi et al. |
6803651 | October 12, 2004 | Chiang |
6812567 | November 2, 2004 | Kim et al. |
6833984 | December 21, 2004 | Belgacem |
6849949 | February 1, 2005 | Lyu et al. |
6876074 | April 5, 2005 | Kim |
6884653 | April 26, 2005 | Larson |
6891729 | May 10, 2005 | Ko et al. |
6908792 | June 21, 2005 | Bruce et al. |
6914324 | July 5, 2005 | Rapport et al. |
6919626 | July 19, 2005 | Burns |
20010006252 | July 5, 2001 | Kim et al. |
20010013423 | August 16, 2001 | Dalal et al. |
20010015487 | August 23, 2001 | Forthun |
20010035572 | November 1, 2001 | Isaak |
20010040793 | November 15, 2001 | Inaba |
20020006032 | January 17, 2002 | Karabatsos |
20020030995 | March 14, 2002 | Shoji |
20020048849 | April 25, 2002 | Isaak |
20020076919 | June 20, 2002 | Peters et al. |
20020101261 | August 1, 2002 | Karabatsos |
20020139577 | October 3, 2002 | Miller |
20020164838 | November 7, 2002 | Moon et al. |
20020180022 | December 5, 2002 | Emoto |
20030016710 | January 23, 2003 | Kamoto |
20030045025 | March 6, 2003 | Coyle et al. |
20030049886 | March 13, 2003 | Salmon |
20030081392 | May 1, 2003 | Cady et al. |
20030107118 | June 12, 2003 | Pflughaupt et al. |
20030109078 | June 12, 2003 | Takahashi et al. |
20030168725 | September 11, 2003 | Wamer et al. |
20040000708 | January 1, 2004 | Rapport et al. |
20040021211 | February 5, 2004 | Damberg |
20040031972 | February 19, 2004 | Pflughaupt et al. |
20040045159 | March 11, 2004 | DiStefano et al. |
20040065963 | April 8, 2004 | Kamezos |
20040075991 | April 22, 2004 | Haba et al. |
20040099938 | May 27, 2004 | Kang et al. |
20040104470 | June 3, 2004 | Bang et al. |
20040115866 | June 17, 2004 | Bang et al. |
20040150107 | August 5, 2004 | Cha et al. |
20040157352 | August 12, 2004 | Beroz et al. |
20040203190 | October 14, 2004 | Pflughaupt et al. |
20040217461 | November 4, 2004 | Damberg |
20040217471 | November 4, 2004 | Haba |
20040238931 | December 2, 2004 | Haba et al. |
20040245617 | December 9, 2004 | Damberg et al. |
20050018495 | January 27, 2005 | Bhakta et al. |
20050035440 | February 17, 2005 | Mohammed |
20050040508 | February 24, 2005 | Lee |
20050133897 | June 23, 2005 | Baek et al. |
004215467 | November 1992 | DE |
004214102 | December 1992 | DE |
0426-303 | October 1990 | EP |
50-29534 | February 1983 | JP |
359088863 | May 1984 | JP |
60-194548 | October 1985 | JP |
60-254762 | December 1985 | JP |
3641047659 | March 1986 | JP |
62-230027 | August 1987 | JP |
2-239651 | September 1990 | JP |
4-209562 | July 1992 | JP |
4-4368167 | December 1992 | JP |
6-77644 | March 1994 | JP |
63-153849 | June 1998 | JP |
2000/307029 | November 2000 | JP |
2001/077294 | March 2001 | JP |
2001/085592 | March 2001 | JP |
2001/332683 | November 2001 | JP |
2003/037246 | February 2003 | JP |
2003/086761 | March 2003 | JP |
2003/088760 | March 2003 | JP |
2003/309246 | October 2003 | JP |
2003/309247 | October 2003 | JP |
2003/347475 | December 2003 | JP |
2003/347503 | December 2003 | JP |
WO 03/037053 | May 2003 | WO |
- “Design Techniques for Ball Grid Arrays,” William R. Newberry, Xynetix Design Systems, Inc.
- Tessera uZ Ball Stack Package, 4 figures that purport to be directed to the uZ—Ball Stacked Memory, 1 Page.
- Flexible Printed Circuit Technology—A Versatile Interconnection Option. (Website 2 pages) Fjelstad, Joseph. Dec. 3, 2002.
- Die Products: Ideal IC Packaging for Demanding Applications—Advanced packaging that's no bigger than the die itself brings together high performance and high reliability with small size and low cost. (Website 3 pages with 2 figures) Larry Gilg and Chris Windsor. Dec. 23, 2002. Published on Internet.
- Chip Scale Review Online—An Independent Journal Dedicated to the Advancement of Chip-Scale Electronics. (Webiste 9 pages) Fjelstad, Joseph, Pacific Consultants L.L.C., Published Jan. 2001 on Internet.
- Flexible Thinking: Examining the Flexible Circuit Tapes. (Website 2 pages) Fjelstad, Joseph., Published Apr. 20, 2000 on Internet.
- Ron Bauer, Intel. “Stacked-CSP Delivers Flexibility, Reliability, and Space-Saving Capabilities”, Vol. 3, Spring 2002. Published on the Internet.
- Tessera Technologies, Inc.—Semiconductor Intellectual Property, Chip Scale Packaging—Website pages (3), Internet.
- Tessera Introduces uZ ä—Ball Stacked Memory Package for Computing and Portable Electronic Products Joyce Smaragdis, Tessera Public Relations, Sandy Skees, MCA PR (www.tessera.com/news_events/press_coverage.cfm); 2 figures that purport to be directed to the uZ ä—Ball Stacked Memory Package. Published Jul. 17, 2002 in San Jose, CA.
- Chip Scale Packaging and Redistribution, Paul A. Magill, Glenn A. Rinne, J. Daniel Mis, Wayne C. Machon, Joseph W. Baggs, Unitive Electronics Inc.
- Dense-Pac Microsystems, 16 Megabit High Speed CMOS SRAM DPS1MX16MKn3.
- Dense-Pac Microsystems, 256 Megabyte CMOS DRAM DP3ED32MS72RW5.
- Dense-Pac Microsystems, Breaking Space Barriers, 3-D Technology 1993.
- Dense-Pac Microsystems, DPS512X16A3, Ceramic 512K X 16 CMOS SRAM Module.
- IBM Preliminary 168 Pin SDRAM Registered DIMM Functional Desciption & Timing Diagrams.
- 3D Interconnection for Ultra-Dense Multichip Modules, Christian Val, Thomson-CSF DCS Computer Division, Thierry Lemoine, Thomson-CSF RCM Radar Countermeasures Division.
- High Density Memory Packaging Technology High Speed Imaging Applications, Dean Frew, Texas Instruments Incorporated.
- Vertically-Intergrated Package, Alvin Weinberg, Pacesetter, Inc. and W. Kinzy Jones, Florida International University.
- 1992 Proceedings, 42nd Electronic Components & Technology Conference, May 18-20, 1992.
- Research Disclosure, Organic Card Device Carrier, 31318, May 1990, No. 313.
- IBM Technical Disclosure Bulletin, vol. 23, No. 12, May 1981.
- IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978.
- IBM Technical Disclosure Bulletin, vol. 32, No. 3B, Aug. 1989.
- Orthogonal Chip Mount—A 3D Hybrid Waier Scale Integration Technology, International Electron Device Meeting, IEDM Technical Digest, Washington, D.C., Dec. 6-9, 1987.
- Anonymous, Organic Card Device Carrier, Research Disclosure, May 1990, No. 313.
Type: Grant
Filed: Jul 27, 2004
Date of Patent: May 15, 2007
Assignee: Stakick Group, L.P. (Austin, TX)
Inventor: Harlan R. Isaak (San Clemente, CA)
Primary Examiner: Luan Thai
Attorney: Fish & Richardson P.C.
Application Number: 10/900,073
International Classification: H01L 23/495 (20060101); H01L 25/16 (20060101); H01L 23/485 (20060101); H01L 23/498 (20060101);