Abstract: A cascading microwave isolator (cascade) includes a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies. Different operating bandwidths have different corresponding center frequencies. A series coupling is formed between first Josephson device from the set and an nth Josephson device from the set. The series coupling causes the first Josephson device to isolate a signal at a first frequency from a frequency multiplexed microwave signal (multiplexed signal) in a first signal flow direction through the series coupling and the nth Josephson device to isolate a signal at an nth frequency from the multiplexed signal in the first signal flow direction through the series.

Abstract: A cascading selective microwave switch (cascade) includes a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies, wherein different operating bandwidths have different corresponding center frequencies. A series coupling is formed between first Josephson device from the set and an nth Josephson device from the set. the series coupling causes the first Josephson device in an open state to reflect back to an input port of the first Josephson device a signal of a first frequency from a frequency multiplexed microwave signal (multiplexed signal) and the nth Josephson device in a closed state to transmit a signal of an nth frequency in the multiplexed signal from an input port of the nth Josephson device to an output port of the nth Josephson device.

Abstract: A cascading microwave isolator (cascade) includes a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies. Different operating bandwidths have different corresponding center frequencies. A series coupling is formed between first Josephson device from the set and an nth Josephson device from the set. The series coupling causes the first Josephson device to isolate a signal at a first frequency from a frequency multiplexed microwave signal (multiplexed signal) in a first signal flow direction through the series coupling and the nth Josephson device to isolate a signal at an nth frequency from the multiplexed signal in the first signal flow direction through the series.

Abstract: One embodiment describes a superconducting cell array logic circuit system. The system includes a plurality of superconducting cells arranged in an array of at least one row and at least one column. The superconducting cell array logic circuit system can be configured to implement a logic operation on at least one logic input signal received at at least one respective input associated with the respective at least one row to provide at least one logic output signal on at least one respective output associated with the at least one column based on a predetermined selective coupling of the at least one input to the at least one output via the plurality of superconducting cells.

Abstract: Values of quantum bits used for a quantum computer is stabilized and the number of quantum bits per element is set to be 100 or more while ensuring quantum state stability during calculation of the quantum bits, quantum state controllability, and capability of achieving large-scale integration of quantum bits. Quantum calculation is performed as generating a spin vortex 6 centered on each hole 4 formed at a copper oxide superconductor thin film 3 by applying a magnetic field to a quantum bit substrate 1 having the copper oxide superconductor thin film 3 at which a plurality of the holes 4 are doped and irradiating an electromagnetic wave 19 containing quantum calculation data to the quantum bit substrate 1 in a state that a clockwise loop current 5 or a counterclockwise loop current 5 is generated in accordance with a position of each hole 4 and each spin vortex 6.

Abstract: The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.

Abstract: A two terminal switching device includes a first conductive terminal, a second conductive terminal in spaced relation to the first terminal, the first terminal encompassed by the second terminal. The device also includes an electrically insulating spacer that encompasses the first terminal and provides the spaced relation between the second terminal and the first terminal. It also includes a nanotube article comprising at least one carbon nanotube, the nanotube article being arranged to overlap at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals that is capable of applying a first electrical stimulus to at least one of the first and second terminals to change the resistance of the device between the first and second terminals from a relatively low resistance to a relatively high resistance.

Abstract: The application relates to electricity, electro-physics and thermo conductivity of materials, to the phenomena of zero electric resistance, i.e. to hyperconductivity (superconductivity) and zero thermal resistance, i.e. to superthermoconductivity of materials at near-room and higher temperatures. The matter: on the surface of in the volume of non-degenerate or poorly degenerate semiconductor material or layer of such material on semi-insulating or dielectric substrate the electrodes are located forming rectifying contacts to the material. The distance between the electrodes (D) is chosen much smaller comparing to the depth of penetration into the material of the electric field caused by their contact difference of potentials (L), (D<<L) Minimum distance between the electrodes DMIN=20 nanometers, maximum distance between the electrodes DMAX=30 micrometers.

Abstract: It is possible to improve the negative resistance characteristic that can be expected when an SNS (superconductor-normal conductor-superconductor) structure is used as a structure unit for series connection. On the top of a first superconducting electrode, a second superconducting electrode is superimposed so as to sandwich an insulation film between the first and second superconducting electrodes, with parts of cross sections of the second superconducting electrode and insulation film placed on the top. A normal superconducting line electrically connects the first and second superconducting electrodes passing along the cross section of the insulation film, thereby constituting a structure unit having a single weak link. A plurality of such structure units connected in series are prepared. At the both ends of the series the first or second superconducting electrode is an element connected to a leading line.

Abstract: Embodiments in accordance with the present invention relate to the design and manufacturing of inexpensive photovoltaic or thermal receivers for cost-effective solar energy conversion of concentrated light. Particular embodiments in accordance with the present invention disclose the design of a photovoltaic receiver and a low-pressure, low-flow-rate liquid cooler. Embodiment of the present invention also disclose a preferred low-cost and scalable manufacturing approach.

Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.

Abstract: This invention concerns quantum computers in which the qubits are closed systems, in that the particle or particles are confined within the structure. A “site” can be produced by any method of confining an electron or other quantum particle, such as a dopant atom, a quantum dot, a cooper pair box, or any combination of these. In particular the invention concerns a closed three-site quantum particle system. The state in the third site is weakly coupled by coherent tunneling to the first and second states, so that the third state is able to map out the populations of the first and second states as its energy is scanned with respect to the first and second states. In second and third aspects it concerns a readout method for a closed three-state quantum particle system.

Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having Josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having Josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.

Abstract: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

Abstract: A first rectangular groove having a rectangular cross section and a second rectangular groove substantially orthogonal to the first rectangular groove and having a rectangular cross section are formed in a first silicon substrate. A third rectangular groove located at a position facing the first rectangular groove and having a rectangular cross section is formed on a second silicon substrate. A device substrate including a frequency conversion device is provided in the second rectangular groove, so that the frequency conversion device is located where the first and second rectangular grooves are orthogonal to each other.

Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.

Abstract: The present invention generally involves an extra-substrate control system comprising a first substrate, attached to which is at least one superconducting structure, and a second substrate, connected to which is at least one element of circuitry, wherein the superconducting structure and the circuitry interact, so that a change in a state of the superconducting structure can be detected by the circuitry. The present invention also provides a quantum computing apparatus comprising a first substrate, attached to which is one or more layers of material, at least one of which is a superconducting material, a second substrate, deposited on which is a flux shield and on the flux shield is at least one element of circuitry, wherein the superconducting material and the second substrate are separated by a mean distance that is small enough to permit coupling between the element of circuitry and the superconducting material.