Device Consisting Of A Plurality Of Semiconductor Or Other Solid State Components Formed In Or On A Common Substrate, E.g., Integrated Circuit Device (epo) Patents (Class 257/E27.001)

  • Patent number: 9492144
    Abstract: Apparatus and methods are provided directed to a device, including at least one ultrasonic transducer, a multi-level pulser coupled to the at least one ultrasonic transducer; the multi-level pulser including a plurality of input terminals configured to receive respective input voltages, an output terminal configured to provide an output voltage, and a signal path between a first input terminal and the output terminal including a first transistor having a first conductivity type coupled to a first diode and, in parallel, a second transistor having a second conductivity type coupled to a second diode.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: November 15, 2016
    Assignee: Butterfly Network, Inc.
    Inventors: Kailiang Chen, Tyler S. Ralston
  • Patent number: 9018046
    Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Joshipura Jwalant, Nitin Bansal, Amit Katyal, Massimiliano Picca
  • Patent number: 8994143
    Abstract: A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 31, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Bog Kim
  • Patent number: 8946717
    Abstract: A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Masahiko Hayakawa, Shunpei Yamazaki
  • Patent number: 8901715
    Abstract: A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the single-crystalline substrate having a surface area; forming a marking structure on the surface area of the single-crystalline substrate, wherein the marking structure comprises a first semiconductor material; and depositing a semiconductor layer on the marking structure and at least partially on the surface area of the single-crystalline substrate, wherein the semiconductor layer comprises the second semiconductor material, and wherein the marking structure is buried under the second semiconductor material.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies AG
    Inventor: Thomas Popp
  • Patent number: 8901703
    Abstract: The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side. A first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region. The intrinsic region of the first pin diode is larger than that of the second pin diode.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: December 2, 2014
    Assignee: NXP, B.V.
    Inventors: Arnoldus Den Dekker, Johannes Frederik Dijkhuis, Nicolas Jonathan Pulsford, Jozef Thomas Martinus Van Beek, Freddy Roozeboom, Antonius Lucien Adrianus Maria Kemmeren, Johan Hendrik Klootwijk, Maarten Dirk-Johan Nollen
  • Patent number: 8884342
    Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
  • Patent number: 8872303
    Abstract: A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wu-Te Weng, Ji-Shyang Nieh
  • Patent number: 8853792
    Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Murshed M. Chowdhury, James K. Schaeffer
  • Patent number: 8853797
    Abstract: A MEMS device and method, comprising: a substrate; a beam; and a cavity located therebetween; the beam comprising a first beam layer and a second beam layer, the first beam layer being directly adjacent to the cavity, the second beam layer being directly adjacent to the first beam layer; the first beam layer comprising a metal or a metal alloy containing silicon; and the second beam layer comprising a metal or a metal alloy substantially not containing silicon. Preferably the second beam layer is thicker than the first beam layer e.g. at least five times thicker, and the first beam layer comprises a metal or alloy containing between 1% and 2% of silicon. The second beam layer provides desired mechanical and/or optical properties while the first beam layer prevents spiking.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: October 7, 2014
    Assignee: NXP, B.V
    Inventor: Robertus T. F. van Schaijk
  • Patent number: 8816497
    Abstract: An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: August 26, 2014
    Assignee: Transphorm Inc.
    Inventor: Yifeng Wu
  • Patent number: 8809117
    Abstract: Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: August 19, 2014
    Assignee: Taiwain Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Wei-Hung Lin, Kuei-Wei Huang, Chih-Wei Lin, Chun-Cheng Lin, Chung-Shi Liu
  • Patent number: 8803285
    Abstract: A semiconductor device has a capacitive structure formed by sequentially layering, on a wiring or conductive plug, a lower electrode, a capacitive insulation film, and an upper electrode. The semiconductor device has, as the capacitive structure, a thin-film capacitor having a lower electrode structure composed of an amorphous or microcrystalline film or a laminate of these films formed on a polycrystalline film.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroto Ohtake, Naoya Inoue, Ippei Kume, Takeshi Toda, Yoshihiro Hayashi
  • Patent number: 8791032
    Abstract: A method of manufacturing a thin film transistor (TFT), a TFT manufactured by the method, a method of manufacturing an organic light-emitting display apparatus that includes the TFT, a display including the TFT. By including a buffer layer below and an insulating layer above a silicon layer for the TFT, the silicon layer can be crystallized without being exposed to air, so that contamination can be prevented. Also, due to the overlying insulating layer, the silicon layer can be patterned without directly contacting photoresist. The result is a TFT with uniform and improved electrical characteristics, and an improved display apparatus.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 29, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Dong-Hyun Lee, Jin-Wook Seo, Ki-Yong Lee
  • Patent number: 8772074
    Abstract: Provided are an organic light emitting display device and a method for manufacturing the same. The organic light emitting display device comprises a transistor on a substrate, a cathode on the transistor and connected to a source or a drain of the transistor, a bank layer on the cathode and having an opening, a metal buffer layer on the cathode, an organic light emitting layer on the metal buffer layer, and an anode on the organic light emitting layer.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: July 8, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jaehee Park, Heeseok Yang, Howon Choi
  • Patent number: 8766399
    Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Maeda, Yasushi Sekine, Tetsuya Watanabe
  • Patent number: 8729660
    Abstract: The present invention discloses a MEMS (Micro-Electro-Mechanical System) integrated chip with cross-area interconnection, comprising: a substrate; a MEMS device area on the substrate; a microelectronic device area on the substrate; a guard ring separating the MEMS device area and the microelectronic device area; and a conductive layer on the surface of the substrate below the guard ring, or a well in the substrate below the guard ring, as a cross-area interconnection electrically connecting the MEMS device area and the microelectronic device area.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: May 20, 2014
    Assignee: Pixart Imaging Inc.
    Inventors: Hsin-Hui Hsu, Chuan-Wei Wang, Sheng-Ta Lee
  • Patent number: 8716805
    Abstract: A complementary metal oxide semiconductor (CMOS) circuit having integrated functional devices such as nanowires, carbon nanotubes, magnetic memory cells, phase change memory cells, ferroelectric memory cells or the like. The functional devices are integrated with the CMOS circuit. The functional devices are bonded (e.g. by direct bonding, anodic bonding, or diffusion bonding) to a top surface of the CMOS circuit. The functional devices are fabricated and processed on a carrier wafer, and an attachment layer (e.g. SiO2) is deposited over the functional devices. Then, the CMOS circuit and attachment layer are bonded. The carrier wafer is removed (e.g. by etching). The functional devices remain attached to the CMOS circuit via the attachment layer. Apertures are etched through the attachment layer to provide a path for electrical connections between the CMOS circuit and the functional devices.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: May 6, 2014
    Assignee: Toshiba America Research, Inc.
    Inventor: Shinobu Fujita
  • Patent number: 8674362
    Abstract: An exemplary embodiment may include a substrate, an insulating layer on the substrate, and a pixel electrode including a transparent conductive layer on the insulating layer. A portion of a surface of the insulating layer contacting the transparent conductive layer has a plurality of recessed holes formed by etching with an etchant into an interface between the transparent conductive layer of the pixel electrode and the insulating layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Ho Kim, Jong-Hyun Choi
  • Publication number: 20140070359
    Abstract: A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Inventors: Shian-Jyh Lin, Jeng-Ping Lin, Chin-Piao Chang, Jen-Jui Huang
  • Publication number: 20140042585
    Abstract: This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chow PENG, Wen-Shen CHOU, Jaw-Juinn HORNG
  • Patent number: 8637869
    Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Je Hun Lee, Yang Ho Bae, Beom-Seok Cho, Chang Oh Jeong
  • Patent number: 8637370
    Abstract: A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces, a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: January 28, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Purakh Raj Verma, Yi Liang, Dong Yemin
  • Patent number: 8610176
    Abstract: An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 17, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Prayag B. Patel, Pratyush Kamal, Foua Vang, Chock H. Gan, Pr Chidambaram, Chethan Swamynathan
  • Patent number: 8604465
    Abstract: An organic light-emitting diode display device includes a substrate, a display unit on the substrate, a touch unit facing the substrate, and a sealing portion surrounding the display unit. The sealing portion couples the substrate to the touch unit and includes glass frit. The touch unit includes an encapsulation substrate, a first conductive layer on the encapsulation substrate, an insulating layer on a portion of the first conductive layer and the encapsulation substrate, and a second conductive layer on the first conductive layer and the insulating layer. The insulating layer of the touch unit includes an organosilicon compound and has a thermal decomposition temperature of about 360° C. or more.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: December 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Yong Song, Young-Seo Choi, Jin-Hwan Jeon, Oh-June Kwon, Sun-Young Jung, Charles Joo, Ji-Hun Ryu
  • Publication number: 20130320555
    Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien YU-TSENG, Shih-Kai LIN, Chin-Shen LIN, Yu-Sian JIANG, Heng-Kai LIU, Mu-Jen HUANG, Chien-Wen CHEN
  • Patent number: 8598570
    Abstract: An organic transistor array includes gate electrodes provided on a substrate, source and drain electrodes provided above or below the gate electrodes via a gate insulator layer, and an organic semiconductor layer opposing the gate electrodes via the gate insulator layer, and forming a channel region between mutually adjacent source and drain electrodes. The organic transistor array in a plan view is sectioned into sections each forming a single pixel, and each section has a closest packed structure.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: December 3, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Keiichiro Yutani, Takumi Yamaga, Atsushi Onodera
  • Patent number: 8598562
    Abstract: The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: December 3, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 8587059
    Abstract: A semiconductor arrangement includes a MOSFET having a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a source electrode contacting the source region and the body region. The semiconductor arrangement further includes a normally-off JFET having a channel region of the first conductivity type that is coupled between the source electrode and the drift region and extends adjacent the body region so that a p-n junction is formed between the body region and the channel region.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: November 19, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Hans-Joachim Schulze
  • Patent number: 8575609
    Abstract: An organic light emitting display apparatus includes a substrate, a thin film transistor formed on the substrate and comprising an active layer, a gate electrode, a source electrode, and a drain electrode, a first gate insulation layer arranged between the gate electrode and the active layer and including an opening portion, a first electrode arranged between the substrate and the first gate insulation layer to overlap the opening portion, an intermediate layer formed on the first electrode and including an organic light emitting layer, a second electrode formed on the intermediate layer, and a capacitor including a first capacitor electrode that is arranged between the substrate and the first gate insulation layer and a second capacitor electrode that is arranged on an upper surface of the first gate insulation layer.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: November 5, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jong-Hyun Choi
  • Publication number: 20130285197
    Abstract: A semiconductor device includes at least one first semiconductor element and two interconnectors for electrically coupling the at least one first semiconductor element to external. A spacing between the two interconnectors corresponds to a size of a second semiconductor element. The second semiconductor element can be affixed between the two interconnectors.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: Infineon Technologies AG
    Inventors: Ralf Otremba, Marco Seibt, Uwe Kirchner
  • Patent number: 8569881
    Abstract: A semiconductor device includes a baseplate and a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate. The semiconductor device includes a first and a second diode substrate coupled to the baseplate and a first, a second, and a third control substrate coupled to the baseplate. Bond wires couple the first and second IGBT substrates to the first control substrate. Bond wires couple the first and second IGBT substrates to the second control substrate via the first and second diode substrates, and bond wires couple the first and second IGBT substrates to the third control substrate via the second diode substrate.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: October 29, 2013
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Spanke, Waleri Brekel, Ivonne Benzler
  • Patent number: 8563398
    Abstract: Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gregory Costrini, Ramachandra Divakaruni, Jeffrey P. Gambino, Randy W. Mann
  • Patent number: 8563368
    Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: October 22, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young-Wook Lee, Hong-Suk Yoo, Jean-Ho Song, Jae-Hyoung Youn, Woo-Geun Lee, Ki-Won Kim, Jong-In Kim
  • Patent number: 8552559
    Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 8, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Patent number: 8546810
    Abstract: A thin film transistor in which an effect of photo current is small and an On/Off ratio is high is provided. In a bottom-gate bottom-contact (coplanar) thin film transistor, a channel formation region overlaps with a gate electrode, a first impurity semiconductor layer is provided between the channel formation region and a second impurity semiconductor layer which is in contact with a wiring layer. A semiconductor layer which serves as the channel formation region and the first impurity semiconductor layer preferably overlap with each other in a region where they overlap with the gate electrode. The first impurity semiconductor layer and the second impurity semiconductor layer preferably overlap with each other in a region where they do not overlap with the gate electrode.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Yasuhiro Jinbo, Hiromichi Godo, Takafumi Mizoguchi, Shinobu Furukawa
  • Patent number: 8536661
    Abstract: Receptors are selectively attached by introducing blocking materials in the areas outside the active sensor surface area, and/or selectively attaching the bio receptors to one or more active sensor surface areas. Methods for selective attachment include the use of optical attachment using a patterned exposure to assist in the creation of receptor bonding to pre-selected regions of the one or more chips. Blocking agents are attached to regions where blocking the receptor attachment is beneficial. Biased conducting regions may also affect selective attachment. Such controlled blocking may be accomplished using optical patterning exposure with optical assisted bonding of the blocking molecule or lift off processes. Patterned exposure for either attachment assists or liftoff processes employs photo masks. Conducting regions outside of the active sensor gate region are biased, affecting biochemical binding or non binding, and shielding of the semiconductor region outside of the active biosensor region.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: September 17, 2013
    Assignee: University of Hawaii
    Inventor: James W. Holm-Kennedy
  • Patent number: 8536577
    Abstract: The present invention provides an active matrix type display device having a high aperture ratio and a required auxiliary capacitor. A source line and a gate line are overlapped with part of a pixel electrode. This overlapped region functions to be a black matrix. Further, an electrode pattern made of the same material as the pixel electrode is disposed to form the auxiliary capacitor by utilizing the pixel electrode. It allows a required value of auxiliary capacitor to be obtained without dropping the aperture ratio. Also, it allows the electrode pattern to function as a electrically shielding film for suppressing the cross-talk between the source and gate lines and the pixel electrode.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: September 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Satoshi Teramoto
  • Patent number: 8536008
    Abstract: A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: September 17, 2013
    Assignee: Powerchip Technology Corporation
    Inventors: Heiji Kobayashi, Yukihiro Nagai
  • Patent number: 8519398
    Abstract: In a pixel portion, a scan signal line and an auxiliary capacitor line are formed using a second conductive film, and a data signal line is formed using a first conductive film. In a TFT portion, a gate electrode is formed using the first conductive film and electrically connected to the scan signal line formed using the second conductive film through an opening in a gate insulating film. Further, a source electrode and a drain electrode are formed using the second conductive film. In the auxiliary capacitor portion, the auxiliary capacitor line formed using the second conductive film serves as a lower electrode, the pixel electrode serves as an upper electrode, and the passivation film used as a dielectric film is interposed between the capacitor electrodes.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kunio Hosoya
  • Patent number: 8507912
    Abstract: An organic light-emitting display device includes an active layer of a thin film transistor (TFT) formed on a substrate; a gate electrode of the TFT, wherein a first gate electrode including a transparent conductive material, a first insulating layer, and a second gate electrode are sequentially stacked; a pixel electrode disposed on the first insulating layer and including the transparent conductive material; a source electrode and a drain electrode of the TFT, a second insulating layer disposed between the source electrode and the drain electrode; a light reflector including the same material as the source electrode and the drain electrode, and disposed on the pixel electrode; an emission layer disposed on top of the pixel electrode and surrounded by an inner side of the light reflector; and a counter electrode facing towards the pixel electrode, wherein the emission layer is disposed between the pixel electrode and the counter electrode.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sung-Ho Kim
  • Patent number: 8486287
    Abstract: Fabrication methods disclosed herein provide for a nanoscale structure or a pattern comprising a plurality of nanostructures of specific predetermined position, shape and composition, including nanostructure arrays having large area at high throughput necessary for industrial production. The resultant nanostracture patterns are useful for nanostructure arrays, specifically sensor and catalytic arrays.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: July 16, 2013
    Assignee: The Regents of the University of California
    Inventors: Ji Zhu, Jeff Grunes, Yang-Kyu Choi, Jeffrey Bokor, Gabor Somorjai
  • Patent number: 8466467
    Abstract: An organic light-emitting display apparatus includes: an active layer formed on the substrate; a gate electrode, in which a first insulation layer formed on the active layer, a first conductive layer formed on the first insulation layer and comprising a transparent conductive material, and a second conductive layer comprising a metal are sequentially stacked; a pixel electrode, in which a first electrode layer formed on the first insulation layer to be spaced apart from the gate electrode and comprising a transparent conductive material, a second electrode layer formed of a semi-permeable metal and comprising pores, and a third electrode layer comprising a metal are sequentially stacked; source/drain electrodes electrically connected to the active layer with a second insulation layer covering the gate electrode and the pixel electrode interposed therebetween; an electro-luminescence (EL) layer formed on the pixel electrode; and an opposite electrode formed on the EL layer to face the pixel electrode, wherein
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: June 18, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: In-Young Jung
  • Publication number: 20130119507
    Abstract: Semiconductor devices using a group III-V material, and methods of manufacturing the same, include a substrate having a groove, a group III-V material layer filling in the groove and having a height the same as a height of the substrate, a first semiconductor device on the group III-V material layer, and a second semiconductor device on the substrate near the groove. The group III-V material layer is spaced apart from inner side surfaces of the groove.
    Type: Application
    Filed: September 13, 2012
    Publication date: May 16, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-moon LEE, Young-jin CHO
  • Patent number: 8440488
    Abstract: This present invention discloses a manufacturing method and structure for a wafer level image sensor module with fixed focal length. The method includes the following steps. First, a silicon wafer comprising several image sensor chips having a photosensitive area and a lens module array wafer comprising several wafer level lens modules with fixed focal length are provided. Next, the image sensor chips and the wafer level lens modules are sorted in grades according to the different quality grades. According to the sorting results, each of the wafer level lens modules is assigned to be situated above the image sensor chip that has the same grade. At the same time, each of the wafer level lens modules is directed to face the photosensitive area of each image sensor chip. Finally, in the packaging process, the wafer level lens module is surrounded by an encapsulation material.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: May 14, 2013
    Assignee: Kingpak Technology Inc.
    Inventors: Hsiu-Wen Tu, Han-Hsing Chen, Chung-Hsien Hsin, Ming-Hui Chen
  • Publication number: 20130088263
    Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.
    Type: Application
    Filed: September 13, 2012
    Publication date: April 11, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Pascal Fornara
  • Patent number: 8410355
    Abstract: This invention intends to develop a technique for forming an interlayer with excellent optical characteristics and to provide a photoelectric conversion device having high conversion efficiency. To realize this purpose, a series connection through an intermediate layer is formed in the thin-film photoelectric conversion device of the invention, and the interlayer is a transparent oxide layer in its front surface and n pairs of layers stacked therebehind (n is an integer of 1 or more), wherein each of the pair of layers is a carbon layer and a transparent oxide layer stacked in this order. Film thicknesses of each layer are optimized to improve wavelength selectivity and stress resistance while keeping the series resistance.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: April 2, 2013
    Assignee: Kaneka Corporation
    Inventors: Tomomi Meguro, Mitsuru Ichikawa, Fumiyasu Sezaki, Kunta Yoshikawa, Takashi Kuchiyama, Kenji Yamamoto
  • Patent number: 8405169
    Abstract: A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ren Cheng, Yi-Hsien Chang, Allen Timothy Chang, Ching-Ray Chen, Li-Cheng Chu, Hung-Hua Lin, Yuan-Chih Hsieh, Lan-Lin Chao
  • Patent number: 8357957
    Abstract: Provided are a FET-based sensor for detecting an ionic material, an ionic material detecting device including the FET-based sensor, and a method of detecting an ionic material using the FET-based sensor. The FET-based sensor includes: a sensing chamber including a reference electrode and a plurality of sensing FETs; and a reference chamber including a reference electrode and a plurality of reference FETs. The method includes: flowing a first solution into and out of the sensing chamber and the reference chamber of the FET-based sensor; flowing a second solution expected to contain an ionic material into and out of the sensing chamber while continuously flowing the first solution into and out of the reference chamber; measuring a current in a channel region between the source and drain of each of the sensing and reference FETs; and correcting the current of the sensing FETs.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: January 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-sang Lee, Kyu-tae Yoo, Jeo-young Shim, Jin-tae Kim, Yeon-ja Cho
  • Patent number: 8344426
    Abstract: A semiconductor device includes a plurality of first cells having a first cell height, and a plurality of second cells having a second cell height. Each of the first cells has a first MIS transistor of a first conductivity type, and a substrate contact region of a second conductivity type. Each of the second cells has a second MIS transistor of the first conductivity type, a power supply region of the first conductivity type, and a first extended region of the first conductivity type that is silicidated at a surface thereof. The first cell height is greater than the second cell height.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Naoki Kotani, Tokuhiko Tamaki