Including Thermo-electric Or Thermo-magnetic Component With Or Without A Junction Of Dissimilar Material Or Thermo-magnetic Component (epo) Patents (Class 257/E27.008)
  • Patent number: 11915994
    Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
  • Patent number: 11774837
    Abstract: An image displaying device includes a micro-LED-array having several LEDs, a controller electrically connected to the micro-LED-array for driving the LEDs such that they emit light, and a lens-array having several lenses. Each lens is assigned to one of the LEDs. Each lens is arranged in the light path of the light emitted by the corresponding LED such that the light emitted by the LEDs passes through the corresponding lens and is projected onto a screen. The lens-array is configured such that, when seen from the screen, a virtual image of the micro-LED-array is formed behind the micro-LED-array. The lens-array is a meta-lens-array and the lenses are meta-lenses.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: October 3, 2023
    Assignee: OSRAM GMBH
    Inventors: Mathieu Rayer, Boaz Sturlesi
  • Patent number: 11600649
    Abstract: An image sensor is disclosed. The image sensor includes a plurality of photodiodes arranged in first and second directions in a matrix, a plurality of first isolation layers, each two adjacent first isolation layers arranged in the first direction being spaced apart from each other by a first distance, each first isolation layer being interposed between adjacent photodiodes arranged in the second direction, and a plurality of second isolation layers, each two adjacent second isolation layers arranged in the second direction being spaced apart from each other by a second distance, each second isolation layer being interposed between adjacent photodiodes arranged in the first direction.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: March 7, 2023
    Assignee: SK HYNIX INC.
    Inventors: Pyong Su Kwag, Byung Hoon Kim
  • Patent number: 11444239
    Abstract: A magnetoresistive element using combined spin-transfer-torque controlled magnetic bias and VCMA effects comprising a free layer and an adjacent-bias layer separated by a nonmagnetic spacing layer, wherein the free layer has an interfacial perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface, the adjacent-bias layer has a perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface, and the perpendicular anisotropy of the free layer is sufficiently higher than that of the adjacent-bias layer such that the critical switching current to reverse the free layer magnetization direction is at least 3 times as high as the critical switching current to reverse the adjacent-bias layer magnetization direction.
    Type: Grant
    Filed: February 28, 2021
    Date of Patent: September 13, 2022
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • Patent number: 10588232
    Abstract: The invention relates to an electronic component for producing infrared radiation. Said component includes a first element and a second element arranged so as to form a closed vacuum cavity in which at least one resistive element of said electronic component is suspended, the at least one resistive element including metal. Said first and second elements are connected by eutectic solder so as to sealingly close the cavity. Said electronic component comprises connection terminals located outside the closed cavity and connected electrically to the suspended resistive element.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 10, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sergio Nicoletti, Mickaël Brun
  • Patent number: 8987848
    Abstract: A MTJ for a spintronic device that is a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8987847
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8872302
    Abstract: Disclosed is an electronic apparatus in which a thermoelectric conversion element and at least one of a photoelectric conversion element and a transistor or a diode are monolithically integrated, or which prevents interference between a p-type thermoelectric conversion unit and an n-type thermoelectric conversion unit. This electronic apparatus includes a thermoelectric conversion element (100) including a semiconductor layer of stacked heterostructure (38) which performs thermoelectric conversion using Seebeck effect and at least one of a photoelectric conversion element (102) in which at least a portion of the semiconductor layer of stacked heterostructure (38) performs photoelectric conversion and a transistor (104) or a diode having at least a portion of the semiconductor layer of stacked heterostructure (38) as an operating layer.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: October 28, 2014
    Assignees: Eyeviewtech Co., Ltd., 3D-Bio Co., Ltd.
    Inventor: Masayuki Abe
  • Patent number: 8802963
    Abstract: A thermoelectric conversion material is provided, in which only a desired crystal is selectively precipitated. An MxV2O5 crystal is selectively precipitated in vanadium-based glass, wherein M is one metal element selected from the group consisting of iron, arsenic, antimony, bismuth, tungsten, molybdenum, manganese, nickel, copper, silver, an alkali metal and an alkaline earth metal, and 0<x<1.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 12, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Fujieda, Takashi Naito, Takuya Aoyagi
  • Patent number: 8698261
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 15, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8692342
    Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sechung Oh, Jangeun Lee, Woojin Kim, Heeju Shin
  • Publication number: 20130334646
    Abstract: A thermal sensor for use in an IC device is formed of a plurality of metal resistor units connected in series where each of the plurality of metal resistor units are formed on different wiring layers of the IC device connected by via segments and the metal resistor units are in a superimposed alignment with each other forming a stack.
    Type: Application
    Filed: June 18, 2012
    Publication date: December 19, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chung-Hui CHEN
  • Publication number: 20130328614
    Abstract: A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 12, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jaw-Juinn HORNG, Chung-Hui CHEN, Sun-Jay CHANG, Chia-Hsin HU
  • Patent number: 8541855
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni)n composition or the like where n is from 2 to 30. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. There may be a Ta insertion layer between the CoFeB layer and laminated layer to promote (100) crystallization in the CoFeB layer. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: September 24, 2013
    Assignee: MagIC Technologies, Inc.
    Inventors: Guenole Jan, Witold Kula, Ru Ying Tong, Yu Jen Wang
  • Patent number: 8508006
    Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: August 13, 2013
    Assignee: MagIC Technologies, Inc.
    Inventors: Guenole Jan, Ru-Ying Tong, Yu-Jen Wang
  • Patent number: 8465998
    Abstract: A thermoelectric conversion module includes a laminated body including a plurality of thermoelectric components laminated therein. Each of the thermoelectric components includes an insulating layer, and a thermoelectric conversion element section in which a plurality of p-type thermoelectric conversion material layers and a plurality of n-type thermoelectric conversion material layers are arranged on the insulating layer in a series connection. A step eliminating insulating material layer is arranged to eliminate a step between the thermoelectric conversion element section and a vicinity thereof, in a region between the insulating layers adjacent to each other in a laminating direction, around the p-type thermoelectric conversion material layers and n-type thermoelectric conversion material layers constituting the thermoelectric conversion element section. The thermoelectric conversion element section has a serpentine shape.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: June 18, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Sasaki, Takanori Nakamura
  • Patent number: 8421061
    Abstract: It is an object of the present invention to reduce variations in behavior of each memory element. In addition, it is another object of the present invention to obtain a semiconductor device, on which the memory element is mounted, which is superior in terms of performance and reliability. A memory element of the present invention includes in its structure a first conductive layer; a semiconductor layer; an organic compound layer; and a second conductive layer, where the semiconductor layer and the organic compound layer are interposed between the first conductive layer and the second conductive layer, and the semiconductor layer is formed to be in contact with the first conductive layer and/or the second conductive layer. With such a structure, variations in behavior of each memory element are reduced.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: April 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mikio Yukawa, Nozomu Sugisawa
  • Patent number: 8399941
    Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has an easy cone magnetic anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: March 19, 2013
    Assignee: Grandis, Inc.
    Inventors: Dmytro Apalkov, Mohamad Towfik Krounbi
  • Publication number: 20130015549
    Abstract: An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 17, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20120211857
    Abstract: A pyroelectric detector includes a substrate, a support member and a pyroelectric detection element, which includes a capacitor, first and second reducing gas barrier layers, an insulating layer, a plug and a second electrode wiring layer. The first reducing gas barrier layer covers at least a second electrode and a pyroelectric body of the capacitor, and has a first opening that overlaps the second electrode in plan view. The insulating layer covers at least the first reducing gas barrier layer, and has a second opening that overlaps the first opening in plan view. The plug is disposed in the first and second openings and connected to the second electrode. The second electrode wiring layer is formed on the insulating layer and connected to the plug. The second reducing gas barrier layer is formed on the insulating layer and the second electrode wiring layer and covers at least the plug.
    Type: Application
    Filed: February 13, 2012
    Publication date: August 23, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Takafumi NODA
  • Publication number: 20120146184
    Abstract: A memcapacitor device includes a memcapacitive matrix interposed between a first electrode and a second electrode. The memcapacitive matrix includes deep level dopants having a first decay time constant and shallow level dopants having a second decay time constant. The second decay time constant is substantially shorter than the first decay time constant. The capacitance of the memcapacitor device depends upon an initial voltage applied across the memcapacitive matrix and a time dependent change in capacitance of the memcapacitor device depends upon the first decay time constant. A method for forming a memcapacitive device is also provided.
    Type: Application
    Filed: August 28, 2009
    Publication date: June 14, 2012
    Inventors: Matthew Pickett, Julien Borghetti, Jianhua Yang
  • Patent number: 8120133
    Abstract: A micro-electromechanical actuator employs metal for the hot arm and silicon for at least the flexible portion of the cold arm. The cold arm made of silicon is coupled to a metal wire that moves with it and is used to carry the signal to be switched when at least two of such actuators are formed into a switch. Arrays of such switches on a first chip may be cooperatively arranged with a second chip that is flip-chip bonded to the first chip, the second chip having thereon wires routing the electrical control currents to the various hot arms for heating them as well as the signals to be switched by the various switches.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: February 21, 2012
    Assignee: Alcatel Lucent
    Inventor: Flavio Pardo
  • Patent number: 7982278
    Abstract: A thermoelectric module has a first substrate, a second substrate spaced from the first substrate, a plurality of P type thermoelectric elements and N type thermoelectric elements arranged in the space between the first and second substrates, and a plurality of electrodes which connect the P type and N type thermoelectric elements in series. Each electrode is connected to a respective one of the plurality of P type thermoelectric elements at a first connection and a respective one of the plurality of N type thermoelectric elements in the space, and a sealant is located at an edge portion of the space. Each one of a series of first or outer electrodes closest to the edge portion of the space has a concave portion that is concaved in a direction departing from the edge portion of the space and is at a position between the first connection and the second connection.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: July 19, 2011
    Assignee: Kyocera Corporation
    Inventors: Kouji Tokunaga, Kenichi Tajima
  • Patent number: 7972877
    Abstract: A method of fabricating a light emitting diode package structure is provided. First, a first circuit substrate having a first surface and a corresponding second surface and a second circuit substrate having a third surface and a corresponding fourth surface are provided. The second surface and the third surface respectively have a plurality of electrodes. Then, a plurality of N-type semiconductor materials and a plurality of P-type semiconductor materials alternatively arranged on the electrodes are formed. Then, the first circuit substrate and the second circuit substrate are assembled. The two type semiconductor materials are located between the electrodes of the first circuit substrate and the second circuit substrate. The two type semiconductor materials are electrically connected to the first circuit substrate and the second circuit substrate through the electrodes. Finally, an LED chip is arranged on the first surface and electrically connected to the first circuit substrate.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: July 5, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Ji Dai, Chun-Kai Liu, Chih-Kuang Yu
  • Patent number: 7973374
    Abstract: Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a metal film spaced from a semiconductor substrate at a predetermined interval and in which a plurality of etching holes are formed. A bottom metal pattern disposed on and/or over a space between the semiconductor substrate and metal film and top metal pattern formed on and/or over the bottom metal pattern may be provided. A pillar may be formed on and/or over the semiconductor substrate and may support one side of a low surface of the bottom metal pattern. A pad may be formed on and/or over the semiconductor substrate, and an air layer corresponding to the bottom metal pattern may be inserted therein. According to embodiments, a pyro-electric switch transistor using a bi-metal with different coefficients of thermal expansion may be provided.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 5, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Eun-Soo Jeong
  • Patent number: 7902617
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second plurality of openings substantially adjacent to the first plurality of openings through the first surface of the substrate, and then forming an n-type TFTEC material within the second plurality of openings.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventor: Rajashree Baskaran
  • Patent number: 7883919
    Abstract: A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gareth Geoffrey Hougham, S. Jay Chey, James Patrick Doyle, Xiao Hu Liu, Christopher V. Jahnes, Paul Alfred Lauro, Nancy C. LaBianca, Michael J. Rooks
  • Patent number: 7833816
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second plurality of openings substantially adjacent to the first plurality of openings through the first surface of the substrate, and then forming an n-type TFTEC material within the second plurality of openings.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventor: Rajashree Baskaran
  • Patent number: 7728401
    Abstract: A thin-film semiconductor device comprises a temperature sensor formed of a thin-film semiconductor and sensing a temperature as current, and a current-voltage converter formed of a thin-film semiconductor and having temperature dependence in which its current-voltage characteristic is different from that of the temperature sensor. A temperature sensed by the temperature sensor is converted to a voltage by the current-voltage converter.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: June 1, 2010
    Assignee: NEC Corporation
    Inventor: Kenichi Takatori
  • Patent number: 7709951
    Abstract: Methods, apparatus and assemblies for enhancing heat transfer in electronic components using a flexible thermal pillow. The flexible thermal pillow has a thermally conductive material sealed between top and bottom conductive layers, with the bottom layer having a flexible reservoir residing on opposing sides of a central portion of the pillow that has a gap. The pillow may have roughened internal surfaces to increase an internal surface area within the pillow for enhanced heat dissipation. In an electronic assembly, the central portion of the pillow resides between a heat sink and heat-generating component for the thermal coupling there-between. During thermal cycling, the flexible reservoir of the pillow expands to retain thermally conductive material extruded from the gap, and then contracts to force such extruded material back into the gap. An external pressure source may contact the pillow for further forcing the extruded thermally conductive material back into the gap.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: William L. Brodsky, Peter J. Brofman, James A. Busby, Bruce J. Chamberlin, Scott A. Cummings, David L. Edwards, Thomas J. Fleischman, Michael J. Griffin, IV, Sushumna Iruvanti, David C. Long, Jennifer V. Muncy, Robin A. Susko
  • Patent number: 7679203
    Abstract: A method of forming a thermoelectric device may include forming a plurality of islands of thermoelectric material on a deposition substrate. The plurality of islands of thermoelectric material may be bonded to a header substrate so that the plurality of islands are between the deposition substrate and the header substrate. More particularly, the islands of thermoelectric material may be epitaxial islands of thermoelectric material having crystal structures aligned with a crystal structure of the deposition substrate. Related structures are also discussed.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: March 16, 2010
    Assignee: Nextreme Thermal Solutions, Inc.
    Inventors: Jayesh Bharathan, David A. Koester, Randall G. Alley, Rama Venkatasubramanian, Pratima Addepalli, Bing Shen, Cynthia Watkins
  • Patent number: 7659562
    Abstract: An electric field read/write head, a method of manufacturing the same, and a data read/write device including the electric field read/write head are provided. The data read/write device includes an electric field read/write head which reads and writes data to and from a recording medium. The electric field read/write head includes a semiconductor substrate, a resistance region, source and drain regions, and a write electrode. The semiconductor substrate includes a first surface and a second surface with adjoining edges. The resistance region is formed to extend from a central portion at one end of the first surface to the second surface. The source region and the drain region are formed at either side of the resistance region and are separated from the first surface. The write electrode is formed on the resistance region with an insulating layer interposed between the write electrode and the resistance region.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: February 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-soo Ko, Ju-hwan Jung, Yong-su Kim, Seung-bum Hong, Hong-sik Park
  • Patent number: 7655944
    Abstract: Embodiments of systems and methods for estimating channel temperatures of a field effect transistor structure are disclosed. One method embodiment, among others, comprises receiving geometrical values corresponding to a field effect transistor (FET) structure, and associating the geometrical values of the FET structure to elliptical cylinder and prolate spheroidal coordinates to provide a closed form expression.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: February 2, 2010
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Ali Mohamed Darwish
  • Patent number: 7615771
    Abstract: Solid-state memories are disclosed that are comprised of cross-point memory arrays. The cross-point memory arrays include a first plurality of electrically conductive lines and a second plurality of electrically conductive lines that cross over the first plurality of electrically conductive lines. The memory arrays also include a plurality of memory cells located between the first and second conductive lines. The memory cells are formed from a metallic material, such as FeRh, having the characteristic of a first order phase transition due to a change in temperature. The first order phase transition causes a corresponding change in resistivity of the metallic material.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: November 10, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Robert E. Fontana, Jr., Eric E. Fullerton, Stefan Maat, Jan-Ulrich Thiele
  • Patent number: 7586125
    Abstract: A light emitting diode (LED) package structure including a first substrate, an LED chip, a second substrate, and a thermoelectric cooling device is provided. The first substrate has a first surface and a corresponding second surface. The LED chip suitable for emitting a light is arranged on the first surface of the first substrate, and is electrically connected to the first substrate. The second substrate is below the first substrate, and has a third surface and a corresponding fourth surface. The third surface faces the second surface. The thermoelectric cooling device is arranged between the second surface of the first substrate and the third surface of the second substrate for conducting heat generated by the LED chip during operation.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: September 8, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Ji Dai, Chun-Kai Liu, Chih-Kuang Yu
  • Patent number: 7556979
    Abstract: A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: Gareth Geoffrey Hougham, S. Jay Chey, James Patrick Doyle, Xiao Hu Liu, Christopher V. Jahnes, Paul Alfred Lauro, Nancy C. LaBianca, Michael J. Rooks
  • Publication number: 20090152666
    Abstract: A thermoelectric semiconductor device includes a plurality of alternating P-type and N-type semiconductor elements disposed between first and second ceramic layers, first conductor elements attached to the first ceramic layer and interconnecting cold junctions of the P-type and N-type semiconductor elements, and second conductor elements attached to the second ceramic layer and interconnecting hot junctions of the P-type and N-type semiconductor elements.
    Type: Application
    Filed: January 23, 2009
    Publication date: June 18, 2009
    Inventor: Chin-Kuang Luo
  • Patent number: 7504658
    Abstract: The present invention relates to a sensor element which has a semiconductor structure based on a Group III-nitride. The semiconductor sensor element serves for determining the pressure, the temperature, a force, a deflection or an acceleration. It has a substrate base 1, disposed thereon, a homogeneous semiconductor layer based on a Group III-nitride, the surface of the homogeneous semiconductor layer 2 orientated towards the substrate base 1 having at least partially a spacing from the surface of the substrate base orientated towards the homogeneous semiconductor layer 2, 2f, and being distinguished in that at least two electrical conducting contacts 5 for conducting an electrical output signal, which can be generated by the homogeneous semiconductor layer 2, 2f, are disposed on, at or under the homogeneous semiconductor layer 2, 2f or are integrated in the latter.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: March 17, 2009
    Inventors: Mike Kunze, Ingo Daumiller, Peter Benkart, Erhard Kohn
  • Publication number: 20080185030
    Abstract: A substrate is provided including a growth surface that is offcut relative to a plane defined by a crystallographic orientation of the substrate at an offcut angle of about 5 degrees to about 45 degrees. A thermoelectric film is epitaxially grown on the growth surface. A crystallographic orientation of the thermoelectric film may be tilted about 5 degrees to about 30 degrees relative to the growth surface. The growth surface of the substrate may also be patterned to define a plurality of mesas protruding therefrom prior to epitaxial growth of the thermoelectric film. Related methods and thermoelectric devices are also discussed.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 7, 2008
    Inventors: Jonathan Pierce, Robert P. Vaudo
  • Publication number: 20080135413
    Abstract: A method of delivering a treatment substance to a target substance in a treatment zone is disclosed. The method comprises providing a treatment substance responsive to an electric or magnetic field such that the treatment substance experiences a kinetic force when disposed in said field, providing an electric or magnetic field extending through a treatment zone, and disposing the treatment substance in the electric or magnetic field such that the treatment substance moves towards the treatment zone and contributes to a reaction with the target substance. A corresponding system is also disclosed.
    Type: Application
    Filed: December 11, 2006
    Publication date: June 12, 2008
    Inventors: David G. Thomas, David Reynolds
  • Patent number: 7372110
    Abstract: A display housing a sound element and a driving circuit that may be built in on the same substrate as the display panel. Thin-film transistors PTFT constituting pixels and a sound wave generation device SPO1 having a laminated structure of a heat generation layer 700, a heat insulation layer 701 and a heat radiation layer 702 are formed on a thin-film transistor (TFT) substrate 500 on which polysilicon thin-film transistors PTFT are formed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: May 13, 2008
    Assignee: Hitachi Displays, Ltd.
    Inventor: Mutsuko Hatano
  • Publication number: 20080079109
    Abstract: A thermoelectric device includes: a first insulator substrate; a plurality of first pads of copper foil attached to the first insulator substrate; a second insulator substrate; a plurality of second pads of copper foil attached to the second insulator substrate; and a plurality of alternately disposed p-type and n-type semiconductor elements disposed between the first and second insulator substrates. Each of the p-type and n-type semiconductor elements has two opposite ends that are respectively bonded to a respective one of the first pads of copper foil and a respective one of the second pads of copper foil through a copper brazing material.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventor: Chin-Kuang Luo
  • Patent number: 7332756
    Abstract: A semiconductor structure having a damascene gate structure and a resistive device on a semiconductor substrate is disclosed. The structure includes a first dielectric layer having a first opening and a second opening formed on the semiconductor substrate, and one or more sidewall spacers formed on inner sides of the first opening, in which a portion of the semiconductor substrate is exposed. In addition, the structure includes a coating layer formed on inner sides and a bottom surface of the second opening, a damascene gate structure surrounded by the sidewall spacers formed in the first opening, and a resistive device formed on the coating layer in the second opening.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: February 19, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung Long Cheng, Kong-Beng Thei, Harry Haklay Chuang
  • Patent number: 7307328
    Abstract: A semiconductor device is disclosed. In one embodiment the semiconductor device includes a semiconductor body of which is integrated a temperature sensor for measuring the temperature prevailing in the semiconductor body. The temperature sensor has a MOS transistor and a bipolar transistor. The MOS transistor is integrated into the semiconductor body nd configured such that the substhreshold current intensity of the MOS transistor is proportional to the temperature to be measured. The subthreshold current of the MOS transistor is amplified by the bipolar transistor.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: December 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Norbert Krischke, Markus Zundel
  • Patent number: 7170163
    Abstract: A semiconductor device mounting structure includes a bus bar of which a first end part is connected to a high-temperature power-purpose semiconductor device and a second end is connected to another device that is required to be kept at a lower temperature than the semiconductor device. The bus bar includes a ribbonlike part zigzagging between the first and second ends. The ribbonlike part of the bus bar can improve the cooling effect by increasing the length of the path through which the heat travels in the lengthwise direction of the bus bar. Thus, the heat emitted from the semiconductor device is prevented from being transferred to a peripheral circuit element through the bus bar used for supplying electric power to the circuit element from the semiconductor device.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: January 30, 2007
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Yoshinori Murakami
  • Patent number: 7081677
    Abstract: A thermoelectric module is constituted by a pair of substrates having electrodes, which are arranged opposite to each other with a prescribed space therebetween, in which a prescribed number of thermoelectric elements are arranged in such a way that a p-type and an n-type are alternately arranged, so that the thermoelectric elements are connected in series or in parallel together with the electrodes. Herein, one substrate is a heat absorption side, and other substrate is a heat radiation side. In addition, a current density in a current transmission area of the heat-absorption-side electrode is set to 50 A/mm2 or less, and a height of the thermoelectric element is set to 0.7 mm or less. Furthermore, a temperature-controlled semiconductor module can be realized by combining a thermoelectric module with a semiconductor component such as a semiconductor laser.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: July 25, 2006
    Assignee: Yamaha Corporation
    Inventors: Masayoshi Yamashita, Naoki Kamimura, Fumiyasu Tanoue, Katsuhiko Onoue, Toshiharu Hoshi