Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.
Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.
Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped.
Abstract: A quantum electronic circuit device includes a housing having an internal resonant cavity, a qubit disposed within a volume of the internal resonant cavity and a non-superconducting metallic material mechanically and thermally coupled to the qubit within the internal resonant cavity and contiguously extending to the exterior of the housing.
January 31, 2012
August 1, 2013
INTERNATIONAL BUSINESS MACHINES CORPORATION
Stefano Poletto, Chad T. Rigetti, Matthias Steffen
Abstract: A pressure detection apparatus (30) detects, among a plurality of superconductor thin films (11 to 14) having different critical pressures at which a transition from a superconductor to an insulator occurs, the superconductor thin films (12 to 14) that have undergone the transition to the insulator with ammeters (242, 252, 262); and to detect, as an internal pressure of a housing (10), the maximum critical pressure among the critical pressures of the detected superconductor thin films (12 to 14).
Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.
August 28, 2009
Date of Patent:
December 11, 2012
The Chugoku Electric Power Co., Inc., Hitachi Ltd., Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
Abstract: A qubit implementation based on exciton condensation in capacitively coupled Josephson junction chains is disclosed. The qubit may be protected in the sense that unwanted terms in its effective Hamiltonian may be exponentially suppressed as the chain length increases. Also disclosed is an implementation of a universal set of quantum gates, most of which offer exponential error suppression.
Abstract: An active device array substrate is provided. The active device array substrate comprises a substrate, multiple first lines, second lines, active devices, pixel electrodes and common lines. The first lines and second lines are disposed on the substrate and they form multiple pixel regions on the substrate. The active devices are respectively disposed in the pixel regions and each of the active devices is electrically connected to a first line and a second line, respectively. The pixel electrodes are respectively disposed in the pixel regions and each of the pixel electrodes is electrically connected to an active device, respectively. The common lines and first lines are roughly parallel and they are staggeringly disposed on the substrate. Each of the common lines has multiple branches which extend outside from their edges of two sides, and each of these branches is partly overlapped with the second lines.
Abstract: A quantum computing structure comprising a superconducting phase-charge qubit, wherein the superconducting phase-charge qubit comprises a superconducting loop with at least one Josephson junction. The quantum computing structure also comprises a first mechanism for controlling a charge of the superconducting phase-charge qubit and a second mechanism for detecting a charge of the superconducting phase-charge qubit, wherein the first mechanism and the second mechanism are each capacitively connected to the superconducting phase-charge qubit.
September 3, 2004
Date of Patent:
February 26, 2008
D-Wave Systems Inc.
Mohammad H. S. Amin, Jeremy P. Hilton, Geordie Rose
Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
November 12, 2002
Date of Patent:
August 17, 2004
Northrop Grumman Corporation
Quentin P. Herr, Lynn A. Abelson, George L. Kerber