Abstract: A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.

Abstract: Coulomb blockade in metal nanoparticles isolated by a tunneling barrier is considered to be a potential solution to low power, robust, high-speed electronic switching device operating at single-electron transport. However, the switching voltage equal to the threshold voltage to overcome coulomb blockade for these devices is typically in the 10 mV range and/or operating at currents well below 1 nA, which inhibits their application as a practical device. Theoretically, a one dimensional nanoparticle necklace is predicted to be an ideal structure to achieve higher switching voltages. The present invention provides a single-electron device composed of a necklace of about 5000 nanoparticles. The linear necklace is self-assembled by interfacial phenomena along a triple-phase line of fiber, a substrate and electrolyte containing nanoparticles. The I-V measurements on the system show both coulomb blockade and staircase, with high currents and high threshold voltage of 1-3 V.

Abstract: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.

Abstract: The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting nanowire. The present invention provides structures and devices comprising conductive nanowire segments and conductance constricting nanowire segments having accurately selected phases including crystalline and amorphous states, compositions, morphologies and physical dimensions, including selected cross sectional dimensions, shapes and lengths along the length of a nanowire. Further, the present invention provides methods of processing nanowires capable of patterning a nanowire to form a plurality of conductance constricting segments having selected positions along the length of a nanowire, including conductance constricting segments having reduced cross sectional dimensions and conductance constricting segments comprising one or more insulating materials such as metal oxides.

Abstract: A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.

Abstract: A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the method comprises providing an electrical signal, e.g. a current, in an input ring magnetically coupled to a computational element, which generates a magnetic field in the computational element and sensing the change in the current and/or voltage of an output element magnetically coupled to the computational element. The electrical input signal can be an AC signal or a DC signal. The computational element is electromagnetically coupled with other adjacent computational elements and/or with the interface elements. The corresponding magnetic flux between the computational elements and/or the interface elements acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements.

Abstract: A photon receptor having a sensitivity threshold of a single photon is readily fabricated on a nanometric scale for compact and/or large-scale array devices. The fundamental receptor element is a quantum dot of a direct semiconductor, as for example in a semiconductor (such as GaAs) isolated from a parallel or adjacent gate electrodes by Nano-scale gap(s). Source and drain electrodes are separated from the photoelectric material by a smaller gap such that photoelectrons created when a photon impinges on the photoelectric material it will release a single electron under a bias (applied between the source and drain to the drain) to the drain electrode, rather than directly to the gate electrode. The drain electrode is connected to the gate electrode by a detection circuit configured to count each photoelectron that flows to the gate electrode.

Abstract: A method (and structure) of coupling a qubit includes locating the qubit near a transmission line approximately at a location corresponding to a node at a predetermined frequency.

Abstract: A fabricating method of Single Electron Transistor includes processing steps as follows: first, deposit the sealing material of gas molecule or atom state on the top-opening of the nano cylindrical pore, which having formed on the substrate, so that the diameter of said top-opening gradually reduce to become a reduced nano-aperture, whose opening diameter is smaller than that of said top-opening; then, keep the substrate in horizontal direction and tilt or rotate said substrate into tilt angle or rotation angle in coordination with tilt angle with the reduced nano-aperture as center respectively, and pass the deposit material of gas molecular or atom state through the reduced nano-aperture respectively. Thereby a Single Electron Transistor including island electrode, drain electrode, source electrode and gate electrode of nano-quantum dot with nano-scale is directly fabricated on the surface of said substrate.

Abstract: A hot electron transistor includes an emitter electrode, a base electrode, a collector electrode, and a first tunneling structure disposed and serving as a transport of electrons between the emitter and base electrodes. The first tunneling structure includes at least a first amorphous insulating layer and a different, second insulating layer such that the transport of electrons includes transport by means of tunneling. The transistor further includes a second tunneling structure disposed between the base and collector electrodes. The second tunneling structure serves as a transport of at least a portion of the previously mentioned electrons between the base and collector electrodes by means of ballistic transport such that the portion of the electrons is collected at the collector electrode. An associated method for reducing electron reflection at interfaces in a thin-film transistor is also disclosed.

Abstract: A control quantum bit circuit and a target quantum bit circuit each have a quantum box electrode including a superconductor, a counter electrode coupled to the quantum box electrode through a tunnel barrier, and a gate electrode coupled to the quantum box electrode through a gate capacitor. The quantum box electrode of the control quantum bit circuit is coupled to the quantum box electrode of the target quantum bit circuit through a box-electrode coupling capacitor.