Abstract: Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include a first superconducting structure and a second superconducting structure disposed on a plane parallel to a silicon wafer surface. A non-superconducting structure may be disposed between the first superconducting structure and the second superconducting structure. A direction of current flow through the non-superconducting structure may be parallel to the silicon wafer surface.

Abstract: A three-terminal device that exhibits transistor-like functionality at cryogenic temperatures may be formed from a single layer of superconducting material. A main current-carrying channel of the device may be toggled between superconducting and normal conduction states by applying a control signal to a control terminal of the device. Critical-current suppression and device geometry are used to propagate a normal-conduction hotspot from a gate constriction across and along a portion of the main current-carrying channel. The three-terminal device may be used in various superconducting signal-processing circuitry.

Abstract: A memory system includes a word-line coupled to memory cells in a row, and a bit-line coupled to memory cells in a column. Each of the memory cells includes a memory storage element including a Josephson junction configured to be in either a first state or a second state in response to an application of a word-line current to the Josephson junction. A read operation is performed on the at least one memory storage element by an application of a bit-line current to the bit-line. At least one inductive-shunt, coupled in parallel to the at least one memory storage element, is configured to, after the read operation, remove at least a substantial portion of the bit-line current provided to the at least one memory storage element without requiring removal of an entirety of the bit-line current applied to the bit-line during the read operation.

Abstract: Computing bus devices that enable quantum information to be coherently transferred between conventional qubit pairs are disclosed. A concrete realization of such a quantum bus acting between conventional semiconductor double quantum dot qubits is described. The disclosed device measures the joint (fermion) parity of the two qubits by using the Aharonov-Casher effect in conjunction with an ancillary superconducting flux qubit that facilitates the measurement. Such a parity measurement, together with the ability to apply Hadamard gates to the two cubits, allows for the production of states in which the qubits are maximally entangled, and for teleporting quantum states between the quantum systems.

Abstract: Computing bus devices that enable quantum information to be coherently transferred between topological and conventional qubits are disclosed. A concrete realization of such a topological quantum bus acting between a topological qubit in a Majorana wire network and a conventional semiconductor double quantum dot qubit is described. The disclosed device measures the joint (fermion) parity of the two different qubits by using the Aharonov-Casher effect in conjunction with an ancillary superconducting flux qubit that facilitates the measurement. Such a parity measurement, together with the ability to apply Hadamard gates to the two qubits, allows for the production of states in which the topological and conventional qubits are maximally entangled, and for teleporting quantum states between the topological and conventional quantum systems.

Abstract: An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the ?=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two ?-quasiparticles, which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the ?=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a ?/8 gate may be effected.

Abstract: Methods are provided of forming a Josephson junction (JJ) quantum bit (qubit). In one embodiment, the method comprises forming a JJ trilayer on a substrate. The JJ trilayer is comprised of a dielectric layer sandwiched between a bottom superconductor material layer and a top superconductor material layer. The method further comprises performing a thermal hardening process on the JJ trilayer to control diffusion of the dielectric layer into the bottom superconductor material layer and the top superconductor material layer, and etching openings in the JJ trilayer to form one or more JJ qubits.

Abstract: A Josephson quantum computing device and an integrated circuit using Josephson quantum computing devices which can realize a NOT gate operation controlled with 2 bits will be provided. The Josephson quantum computing device (1) comprises: a superconducting ring member (10) having a ?-junction (6) and a 0-junction (7); and a quantum state detecting member (20) constituted by a superconducting quantum interference device arranged outside of the superconducting ring member, wherein a bonding and an antibonding state brought about by a tunneling effect between a | ? > and a | ? > state as two states degenerate in energy of the superconducting ring member (10) are regarded as quantum bits. The bonding and antibonding states as the quantum bits are read out by the quantum state detecting member (20). The two bit controlled NOT gate operation can be performed by the two quantum bits comprising said quantum bits.

Abstract: A pressure detection apparatus (30) detects, among a plurality of superconductor thin films (11 to 14) having different critical pressures at which a transition from a superconductor to an insulator occurs, the superconductor thin films (12 to 14) that have undergone the transition to the insulator with ammeters (242, 252, 262); and to detect, as an internal pressure of a housing (10), the maximum critical pressure among the critical pressures of the detected superconductor thin films (12 to 14).

Abstract: A quantum information processing system includes a first composite quantum system, a second composite quantum system, a plurality of electromagnetic field sources coupled to the system and an adjustable electromagnetic coupling between the first composite quantum system and the second composite quantum system.

Abstract: A device includes a volume bounded by electromagnetically conducting walls, an aperture in a bounding wall of the electromagnetically conducting walls, a plurality of quantum systems disposed within the volume and an electromagnetic field source coupled to the volume via the aperture.

Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.

Abstract: Computing bus devices that enable quantum information to be coherently transferred between conventional qubit pairs are disclosed. A concrete realization of such a quantum bus acting between conventional semiconductor double quantum dot qubits is described. The disclosed device measures the joint (fermion) parity of the two qubits by using the Aharonov-Casher effect in conjunction with an ancillary superconducting flux qubit that facilitates the measurement. Such a parity measurement, together with the ability to apply Hadamard gates to the two cubits, allows for the production of states in which the qubits are maximally entangled, and for teleporting quantum states between the quantum systems.

Abstract: A novel Josephson junction and a novel Josephson junction device are provided which eliminates the need to form an insulating barrier layer. The Josephson junction (1) comprises a superconductor layer (2) and a ferromagnetic layer (3) formed on a middle part (2C) of the superconductor layer (2). The ferromagnetic layer (3) may consist of an electrically conductive or insulating ferromagnetic layer, and may be an electrically conductive ferromagnetic layer formed via an insulating layer. With the superconductor layer (2) formed of a high temperature superconductor, a Josephson junction (1) is provided having large IcRN product. The Josephson junction (1) can be used as a junction for a variety of Josephson devices.

Abstract: Computing bus devices that enable quantum information to be coherently transferred between topological and conventional qubits are disclosed. A concrete realization of such a topological quantum bus acting between a topological qubit in a Majorana wire network and a conventional semiconductor double quantum dot qubit is described, The disclosed device measures the joint (fermion) parity of the two different qubits by using the Aharonov-Casher effect in conjunction. with an ancillary superconducting flux qubit that facilitates the measurement. Such a parity measurement, together with the ability to apply Hadamard gates to the two qubits, allows for the production of states in which the topological and conventional qubits are maximally entangled, and for teleporting quantum states between the topological and conventional quantum systems.

Abstract: An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the ?=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two ?-quasiparticles. which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the ?=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a ?/8 gate may be effected.

Abstract: A new family of superconducting materials with critical temperature up to 55 K have recently been discovered, comprising a crystal structure with atomic layers of iron and arsenic alternating with atomic layers of rare-earth oxide or alkaline earth. The present invention identifies structures for integrated circuit elements (including Josephson junctions) in these and related materials. These superconducting circuit elements will operate at a higher temperature than low-temperature superconductors such as niobium, and may be easier to manufacture than prior-art high-temperature superconductors based on copper-oxides.

Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.

Abstract: It is possible to improve the negative resistance characteristic that can be expected when an SNS (superconductor-normal conductor-superconductor) structure is used as a structure unit for series connection. On the top of a first superconducting electrode, a second superconducting electrode is superimposed so as to sandwich an insulation film between the first and second superconducting electrodes, with parts of cross sections of the second superconducting electrode and insulation film placed on the top. A normal superconducting line electrically connects the first and second superconducting electrodes passing along the cross section of the insulation film, thereby constituting a structure unit having a single weak link. A plurality of such structure units connected in series are prepared. At the both ends of the series the first or second superconducting electrode is an element connected to a leading line.

Abstract: Disclosed herein is a protocol that enables the ?/8-gate in chiral topological superconductors in which superconducting stiffness ? has been suppressed. The protocol enables a topologically protected ?/8-gate in any pure Ising system that can be fabricated into genus=1 surface. By adding the ?/8-gate to previously known techniques, a design for universal topologically protected quantum computation which may be implemented using rather conventional materials may be obtained.

Abstract: A method (and structure) of quantum computing. Two independent magnitudes of a three-state physical (quantum) system are set to simultaneously store two real, independent numbers as a qubit. The three-state physical (quantum) system has a first energy level, a second energy level, and a third energy level capable of being degenerate with respect to one another, thereby forming basis states for the qubit.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

Abstract: Terahertz radiation source and method of producing terahertz radiation, said source comprising a junction stack, said junction stack comprising a crystalline material comprising a plurality of self-synchronized intrinsic Josephson junctions; an electrically conductive material in contact with two opposing sides of said crystalline material; and a substrate layer disposed upon at least a portion of both the crystalline material and the electrically-conductive material, wherein the crystalline material has a c-axis which is parallel to the substrate layer, and wherein the source emits at least 1 mW of power.

Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.

Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.

Abstract: A qubit implementation based on exciton condensation in capacitively coupled Josephson junction chains is disclosed. The qubit may be protected in the sense that unwanted terms in its effective Hamiltonian may be exponentially suppressed as the chain length increases. Also disclosed is an implementation of a universal set of quantum gates, most of which offer exponential error suppression.

Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.

Abstract: A quantum processor may employ a heterogeneous qubit-coupling architecture to reduce the average number of intermediate coupling steps that separate any two qubits in the quantum processor, while limiting the overall susceptibility to noise of the qubits. The architecture may effectively realize a small-world network where the average qubit has a low connectivity (thereby allowing it to operate substantially quantum mechanically) but each qubit is within a relatively low number of intermediate coupling steps from any other qubit. To realize such, some of the qubits may have a relatively high connectivity, and may thus operate substantially classically.

Abstract: An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.

Abstract: An architecture for a quantum processor may include a set of superconducting flux qubits operated as computation qubits and a set of superconducting flux qubits operated as latching qubits. Latching qubits may include a first closed superconducting loop with serially coupled superconducting inductors, interrupted by a split junction loop with at least two Josephson junctions; and a clock signal input structure configured to couple clock signals to the split junction loop. Flux-based superconducting shift registers may be formed from latching qubits and sets of dummy latching qubits. The devices may include clock lines to clock signals to latch the latching qubits. Thus, latching qubits may be used to program and configure computation qubits in a quantum processor.

Abstract: A novel Josephson junction and a novel Josephson junction device are provided which eliminates the need to form an insulating barrier layer. The Josephson junction (1) comprises a superconductor layer (2) and a ferromagnetic layer (3) formed on a middle part (2C) of the superconductor layer (2). The ferromagnetic layer (3) may consist of an electrically conductive or insulating ferromagnetic layer, and may be an electrically conductive ferromagnetic layer formed via an insulating layer. With the superconductor layer (2) formed of a high temperature superconductor, a Josephson junction (1) is provided having large IcRN product. The Josephson junction (1) can be used as a junction for a variety of Josephson devices.

Abstract: A Bi-based oxide superconductor thin film whose c-axis is oriented parallel to the substrate and whose a-axis (or b-axis) is oriented perpendicular to the substrate, is manufactured in order to obtain a high performance layered Josephson junction using a Bi-based oxide superconductor. The method of manufacturing an a-axis oriented Bi-based oxide superconductor thin film, involves an epitaxial growth process using an LaSrAlO4 single crystal substrate of a (110) plane or a LaSrGaO4 single crystal substrate of a (110) plane, for which the lattice constant matches well with a (100) plane of a Bi-2223 oxide superconductor. By this method, rather than the normally easily obtained Bi-2212, an a-axis oriented film of Bi-2223 showing an extremely high superconductive transition temperature even for a Bi-based oxide superconductor can be selectively manufactured.

Abstract: Multiple substrates that carry quantum devices are coupled to provide quantum mechanical communicators therebetween, for example, using superconducting interconnects, vias, solder and/or magnetic flux. Such may advantageously reduce a footprint of a device such as a quantum processor.

Abstract: A system employs a plurality of physical qubits, each having a respective bias operable to up to six differentiable inputs to solve a Quadratic Unconstrained Binary Optimization problem. Some physical qubit couplers are operated as intra-logical qubit couplers to ferromagnetically couple respective pairs of the physical qubits as a logical qubit, where each logical qubit represents a variable from the Quadratic Unconstrained Binary Optimization problem.

Abstract: A multilayer structure with zirconium-oxide tunnel barriers. In one embodiment, the multilayer structure includes a first niobium (Nb) layer, a second niobium (Nb) layer, and a plurality of zirconium-oxide tunnel barriers sandwiched between the first niobium (Nb) layer and the second niobium (Nb) layer, wherein the plurality of zirconium-oxide tunnel barriers is formed with N layers of zirconium-oxide, N being an integer greater than 1, and M layers of zirconium, M being an integer no less than N, such that between any two neighboring layers of zirconium-oxide, a layer of zirconium is sandwiched therebetween.

Abstract: An integrated circuit for quantum computing may include a superconducting shield to limit magnetic field interactions.

Abstract: A method for reading out the state of a mesoscopic phase device. In the method the mesoscopic phase device is coherently coupled to a mesoscopic charge device using a phase shift device and the quantum state of the mesoscopic charge device is measured. A method for reading out the quantum state of a qubit in a heterogeneous quantum register. The heterogeneous quantum register includes a first plurality of phase qubits and a second plurality of charge qubits. In the method a first phase qubit or a first charge qubit in the heterogeneous quantum register is selected. The first phase qubit or the first charge qubit is coherently connected to a mesoscopic charge device for a duration tc. The quantum state of the mesoscopic charge device is read out after the duration tc has elapsed.

Abstract: A high-temperature superconductive device is disclosed, including a ramp-edge junction. The ramp-edge junction includes a first electrode layer (5) that defines the size of the ramp-edge junction and a second electrode layer (6). The width of the second electrode layer (6) is greater than the width of the first electrode layer (5). The first electrode layer (5) and the second electrode layer (6) touch in part, and are separated via a first insulation layer (7) in remaining part. Because the ramp-edge junction includes the first electrode layer (5) and the second electrode layer (6), the inductance of the ramp-edge junction can be reduced with the critical current density Jc being kept at a high level.

Abstract: A method for preparing film oxides deposited on a substrate with a resulting grain boundary junction that is atomistically straight. A bicrystal substrate having a straight grain boundary is prepared as a template. The Miller indices h1, k1, h2, k2 of the two grains of the substrate are chosen such that the misorientation angle of the film is equal to arctan k1/h1+arctan k2/h2. The film is grown on the substrate using a layer-by-layer growth mode.

Abstract: A superconductor integrated circuit (1) includes an anodization ring (35) disposed around a perimeter of a tunnel junction region (27) for preventing a short-circuit between an outside contact (41) and the base electrode layer (18). The tunnel junction region (27) includes a junction contact (31) with a diameter of approximately 1.00 ?m or less defined by a top surface of the counter electrode layer (24). The base electrode layer (18) includes an electrode isolation region (36) disposed approximately 0.8 ?m in horizontal distance from the junction contact (31) for providing device isolation.