Abstract: A method of fabricating a device including a superconductive layer includes depositing a seed layer on a substrate at a first temperature, the seed layer being a nitride of a first metal, reducing the temperature of the substrate to a second temperature that is lower than the first temperature, increasing the temperature of the substrate to a third temperature that is higher than the first temperature to form a modified seed layer, and depositing a metal nitride superconductive layer directly on the modified seed layer at the third temperature, the superconductive layer being a nitride of a different second metal.

Abstract: A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer.

Abstract: Disclosed herein is a topologically protected ?/8-gate which becomes universal when combined with the gates available through quasi-particle braiding and planar quasi-particle interferometry. A twisted interferometer, and a planar ?/8-gate in CTS, implemented with the help of the twisted interferometer, are disclosed. Embodiments are described in the context of state X (CTS) supported by an ISH, although the concept of a twisted-interferometer is more general and has relevance to all anionic, i.e. quasiparticle systems.

Abstract: Disclosed is a triple-gate or multi-gate component based on the quantum mechanical tunnel effect. The component comprises at least two tunneling electrodes on a substrate that are separated by a gap through which electrons can tunnel. The component comprises an arrangement for applying an electric field to the gap, which is such that the path of an electron tunneling between the tunneling electrodes is elongated as a result of the deflection caused by this field. In general, an arrangement can also be provided for applying an electric field to the gap, this electric field having a field component that is perpendicular to the direction of the tunnel current between the tunneling electrodes and is parallel to the substrate. Since the tunnel current between the tunneling electrodes exponentially depends on the distance traveled by the electrons in the gap, such an electric field has a penetration effect on the tunneling probability and thus on the tunnel current to be controlled.

Abstract: A method is provided for constructing a nanodevice. The method includes: fabricating an electrode on a substrate; forming a nanogap across the electrode; dispersing a plurality of nanoobjects onto the substrate using electrophoresis; and pushing one of the nanoobjects onto the electrode using a tip of an atomic force microscope, such that the nanoobject lies across the nanogap formed in the electrode. In addition, remaining nanoobjects may also be pushed away from the electrode using the atomic force microscope, thereby completing construction of a nanodevice.

Abstract: The present invention involves a quantum computing structure, comprising: one or more logical qubits, which is encoded into a plurality of superconducting qubits; and each of the logical qubits comprises at least one operating qubit and at least one ancilla qubit. Also provided is a method of quantum computing, comprising: performing encoded quantum computing operations with logical qubits that are encoded into superconducting operating qubits and superconducting ancilla qubits. The present invention further involves a method of error correction for a quantum computing structure comprising: presenting a plurality of logical qubits, each of which comprises an operating physical qubit and an ancilla physical qubit, wherein the logical states of the plurality of logical qubits are formed from a tensor product of the states of the operating and ancilla qubits; and wherein the states of the ancilla physical qubits are suppressed; and applying strong pulses to the grouping of logical qubits.

Abstract: A lateral CMOS-compatible RF-DMOS transistor (RFLDMOST) with low ‘on’ resistance, characterised in that disposed in the region of the drift space (20) which is between the highly doped drain region (5) and the control gate (9) and above the low doped drain region LDDR (22, 26) of the transistor is a doping zone (24) which is shallow in comparison with the penetration depth of the source/drain region (3, 5), of inverted conductivity type to the LDDR (22, 26) (hereinafter referred to as the inversion zone) which has a surface area-related nett doping which is lower than the nett doping of the LDDR (22, 26) and does not exceed a nett doping of 8E12 At/cm2.

Abstract: A control quantum bit circuit and a target quantum bit circuit each have a quantum box electrode including a superconductor, a counter electrode coupled to the quantum box electrode through a tunnel barrier, and a gate electrode coupled to the quantum box electrode through a gate capacitor. The quantum box electrode of the control quantum bit circuit is coupled to the quantum box electrode of the target quantum bit circuit through a box-electrode coupling capacitor.