Three Or More Electrode Devices (epo) Patents (Class 257/E39.019)
  • Patent number: 11522128
    Abstract: A metasurface unit cell for use in constructing a metasurface array is provided. The unit cell may include a ground plane layer comprising a first conductive material, and a phase change material layer operably coupled to the ground plane layer. The phase change material layer may include a phase change material configured to transition between an amorphous phase and a crystalline phase in response to a stimulus. The unit cell may further include a patterned element disposed adjacent to the phase change material layer and includes a second conductive material. In response to the phase change material transitioning from a first phase to a second phase, the metasurface unit cell may resonate to generate an electromagnetic signal having a defined wavelength. The first phase may be the amorphous phase or the crystalline phase and the second phase may be the other of the amorphous phase or the crystalline phase.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 6, 2022
    Assignee: The Johns Hopkins University
    Inventors: David B. Shrekenhamer, Jeffrey P. Maranchi, Joseph A. Miragliotta, Keith S. Caruso
  • Patent number: 7723715
    Abstract: A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a first area of electrical communication with the phase-change material. A second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, and the second area being laterally spacedly disposed from the first area. Additionally, the radial memory device includes a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer having an opening therethrough, the phase-change material being disposed in the opening, wherein the phase-change material is disposed at least partially above the second electrode. Further, a method of making a memory device is disclosed.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: May 25, 2010
    Assignee: Ovonyx, Inc.
    Inventors: Wolodymyr Czubatyj, Tyler Lowrey, Isamu Asano
  • Patent number: 7307275
    Abstract: The present invention involves a quantum computing structure, comprising: one or more logical qubits, which is encoded into a plurality of superconducting qubits; and each of the logical qubits comprises at least one operating qubit and at least one ancilla qubit. Also provided is a method of quantum computing, comprising: performing encoded quantum computing operations with logical qubits that are encoded into superconducting operating qubits and superconducting ancilla qubits. The present invention further involves a method of error correction for a quantum computing structure comprising: presenting a plurality of logical qubits, each of which comprises an operating physical qubit and an ancilla physical qubit, wherein the logical states of the plurality of logical qubits are formed from a tensor product of the states of the operating and ancilla qubits; and wherein the states of the ancilla physical qubits are suppressed; and applying strong pulses to the grouping of logical qubits.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: December 11, 2007
    Assignees: D-Wave Systems Inc., The University of Toronto
    Inventors: Daniel Lidar, Lian-Ao Wu, Alexandre Blais
  • Patent number: 7304348
    Abstract: A lateral CMOS-compatible RF-DMOS transistor (RFLDMOST) with low ‘on’ resistance, characterised in that disposed in the region of the drift space (20) which is between the highly doped drain region (5) and the control gate (9) and above the low doped drain region LDDR (22, 26) of the transistor is a doping zone (24) which is shallow in comparison with the penetration depth of the source/drain region (3, 5), of inverted conductivity type to the LDDR (22, 26) (hereinafter referred to as the inversion zone) which has a surface area-related nett doping which is lower than the nett doping of the LDDR (22, 26) and does not exceed a nett doping of 8E12 At/cm2.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: December 4, 2007
    Assignee: IHP GmbH - Innovations for High Performance Microelectronics/Institut fur Innovative Mikroelektronik
    Inventors: Karl-Ernst Ehwald, Holger Rücker, Bernd Heinemann
  • Patent number: 7145170
    Abstract: A control quantum bit circuit and a target quantum bit circuit each have a quantum box electrode including a superconductor, a counter electrode coupled to the quantum box electrode through a tunnel barrier, and a gate electrode coupled to the quantum box electrode through a gate capacitor. The quantum box electrode of the control quantum bit circuit is coupled to the quantum box electrode of the target quantum bit circuit through a box-electrode coupling capacitor.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: December 5, 2006
    Assignees: NEC Corporation, Riken
    Inventors: Tsuyoshi Yamamoto, Yasunobu Nakamura, Jaw-Shen Tsai