Bulk Negative Resistance Effect Devices, E.g., Gunn-effect Devices, Processes, Or Apparatus Peculiar To Manufacture Or Treatment Of Such Devices, Or Of Parts Thereof (epo) Patents (Class 257/E47.001)
  • Patent number: 10573375
    Abstract: Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Yue-Song He, Rusli Kurniawan, Richard G. Smolen, Christopher J. Pass, Andy L. Lee, Jeffrey T. Watt, Anwen Liu, Alok Nandini Roy
  • Patent number: 9691769
    Abstract: A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongjun Kim, Keeshik Park, Jungwoo Song, Sang-Jun Lee, Donggyun Han, Jaerok Kahng
  • Patent number: 9029233
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: May 12, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ronald John Kuse, Tony Chiang, Michael Miller, Prashant Phatak, Jinhong Tong
  • Patent number: 9012881
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ronald J. Kuse, Tony P. Chiang, Imran Hashim
  • Patent number: 8993374
    Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Davide Erbetta, Luca Fumagalli
  • Patent number: 8980683
    Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min Yong Lee, Young Ho Lee, Seung Beom Baek, Jong Chul Lee
  • Patent number: 8975613
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ronald John Kuse, Tony Chiang, Michael Miller, Prashant Phatak, Jinhong Tong
  • Patent number: 8957400
    Abstract: The memory cell includes a memory area which is formed in a phase-change material pattern based on chalcogenide. An electric p/n-type junction is series-connected between electrodes. The p/n junction is formed in a crystalline area by the interface between first and second doped areas of the phase-change material pattern. The memory area is formed in one of the two doped areas, at a distance from the junction.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: February 17, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Luca Perniola, Giovanni Betti Beneventi
  • Patent number: 8952349
    Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo
  • Patent number: 8946668
    Abstract: Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: February 3, 2015
    Assignee: NEC Corporation
    Inventors: Yukishige Saito, Kimihiko Ito, Hiromitsu Hada
  • Patent number: 8932901
    Abstract: A memory device includes a substrate and a memory array on the substrate. The memory array includes memory cells including stressed phase change materials in a layer of encapsulation materials. The memory cells may include memory cell structures such as mushroom-type memory cell structures, bridge-type memory cell structures, active-in-via type memory cell structures, and pore-type memory cell structures. The stressed phase change materials may comprise GST (GexSbxTex) materials in general and Ge2Sb2Te5 in particular. To manufacture the memory device, a substrate is first fabricated. Memory cells including phase change materials in a layer of encapsulation materials are formed on a front side of the substrate. A tensile or compressive stress is induced into the phase change materials on the front side of the substrate.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: January 13, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Huai-Yu Cheng
  • Patent number: 8921156
    Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: December 30, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Prashant B Phatak, Tony P. Chiang, Pragati Kumar, Michael Miller
  • Patent number: 8921816
    Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: December 30, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Bo-Young Seo, Byung-Suo Shim, Yong-Kyu Lee, Tea-Kwang Yu, Ji-Hoon Park
  • Patent number: 8890104
    Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 18, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min Yong Lee, Young Ho Lee, Seung Beom Baek, Jong Chul Lee
  • Patent number: 8878153
    Abstract: A structure for a variable-resistance element using an electrochemical reaction. The structure limits a position at which metal cross-linking breaks to a position most preferred for cross-linking break: namely, a part of an ion conduction layer closest to a first electrode. Also provided is a method for manufacturing the variable-resistance element, which has a first electrode serving as a source for a metal ion(s), a second electrode which is less ionizable (i.e. has a higher redox potential) than the first electrode, and an ion conduction layer which is interposed between the first and second electrodes and can conduct the metal ion(s). There is a first region in the ion conduction layer, adjacent to the first electrode, having a diffusion coefficient that increases continuously towards the first electrode right upto contacting the first electrode.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: November 4, 2014
    Assignee: NEC Corporation
    Inventor: Yukihide Tsuji
  • Patent number: 8866123
    Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Akio Shima, Takashi Kobayashi
  • Patent number: 8847186
    Abstract: A Zinc Oxide (ZnO) layer deposited using Atomic Layer Deposition (ALD) over a phase-change material forms a self-selected storage device. The diode formed at the ZnO/GST interface shows both rectification and storage capabilities within the PCM architecture.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano
  • Patent number: 8835898
    Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line with a spacer of electrically insulating material surrounding the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
  • Patent number: 8830740
    Abstract: The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: September 9, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Hiroyuki Minemura, Takashi Kobayashi, Toshimichi Shintani, Satoru Hanzawa, Masaharu Kinoshita
  • Patent number: 8803122
    Abstract: Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 12, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Shyue Seng (Jason) Tan, Eng Huat Toh
  • Patent number: 8803124
    Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 12, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Dipankar Pramanik, Tony P. Chiang, David Lazovsky
  • Patent number: 8779408
    Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 15, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Hsiu Lee, Chieh-Fang Chen
  • Patent number: 8766234
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Imran Hashim, Venkat Ananthan, Tony P. Chiang, Prashant B. Phatak
  • Patent number: 8767441
    Abstract: Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: July 1, 2014
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo, Hagop Nazarian
  • Patent number: 8766233
    Abstract: A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 1, 2014
    Assignee: NEC Corporation
    Inventors: Yukihiro Sakotsubo, Masayuki Terai, Munehiro Tada, Yuko Yabe, Yukishige Saito
  • Patent number: 8748859
    Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: June 10, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Christopher J Petti, Calvin K Li
  • Patent number: 8741698
    Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium oxide for use in a variety of electronic devices. Forming the dielectric layer includes depositing zirconium oxide using atomic layer deposition. A method of atomic layer deposition to produce a metal-rich metal oxide comprises the steps of providing a silicon substrate in a reaction chamber, pulsing a zirconium precursor for a predetermined time to deposit a first layer, and oxidizing the first layer with water vapor to produce the metal-rich metal oxide. The metal-rich metal oxide has superior properties for non-volatile resistive-switching memories.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: June 3, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Jinhong Tong, Vidyut Gopal, Imran Hashim, Randall Higuchi, Albert Lee
  • Patent number: 8741727
    Abstract: A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Junichi Ariyoshi, Taiji Ema, Toru Anezaki
  • Patent number: 8686393
    Abstract: An integrated circuit device may include a semiconductor substrate including an active region and a transistor in the active region. The transistor may include first and second spaced apart source/drain regions in the active region of the semiconductor substrate, and a semiconductor channel region between the first and second source/drain regions. The semiconductor channel region may include a plurality of channel trenches therein between the first and second source/drain regions. A gate insulating layer may be provided on the channel region including sidewalls of the plurality of channel trenches, and a gate electrode may be provided on the gate insulating layer so that the gate insulating layer is between the gate electrode and the semiconductor channel region including the plurality of channel trenches. Related methods are also discussed.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jihyung Yu, Daewon Ha, Song yi Kim
  • Patent number: 8687402
    Abstract: A non-volatile solid state resistive device that includes a first electrode, a p-type poly-silicon second electrode, and a non-crystalline silicon nanostructure electrically connected between the electrodes. The nanostructure has a resistance that is adjustable in response to a voltage being applied to the nanostructure via the electrodes. The nanostructure can be formed as a nanopillar embedded in an insulating layer located between the electrodes. The first electrode can be a silver or other electrically conductive metal electrode. A third (metal) electrode can be connected to the p-type poly-silicon second electrode at a location adjacent the nanostructure to permit connection of the two metal electrodes to other circuitry. The resistive device can be used as a unit memory cell of a digital non-volatile memory device to store one or more bits of digital data by varying its resistance between two or more values.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: April 1, 2014
    Assignee: The Regents of The University of Michigan
    Inventors: Wei Lu, Sung Hyun Jo, Kuk-Hwan Kim
  • Patent number: 8680504
    Abstract: A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) thrilled over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 25, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Patent number: 8674333
    Abstract: Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8674522
    Abstract: The present invention provides a castle-like shaped protect or a periphery protect or a DC chop mask for forming staggered data line patterns in semiconductor devices so as to shift the adjacent data lines from one another so as to print contacts with larger areas at one end of each data line.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 18, 2014
    Assignee: Nanya Technology Corp.
    Inventors: David Pratt, Richard Housley
  • Publication number: 20140061568
    Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Inventors: Durai Vishak Nirmal Ramaswamy, Lei Bi, Beth R. Cook, Dale W. Collins
  • Publication number: 20140054531
    Abstract: Embodiments of the invention set forth a nonvolatile memory element with a novel variable resistance layer and methods of forming the same. The novel variable resistance layer includes a metal-rich host oxide that operates with a reduced switching voltage and current and requires significantly reduced forming voltage when manufactured. In some embodiments, the metal-rich host oxide is deposited using a modified atomic layer deposition (ALD) process. In other embodiments, the metal-rich host oxide is formed by depositing a metal-containing coupling layer on a host oxide and thermally processing both layers to create a metal-rich composite host oxide with a higher concentration of oxygen vacancies.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Nan Lu, Imran Hashim, Jinhong Tong, Ruey-Ven Wang
  • Publication number: 20140054535
    Abstract: A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Hung Chen, Hang-Ting Lue, Kuang-Yeu Hsieh, Erh-Kun Lai, Yen-Hao Shih
  • Patent number: 8659002
    Abstract: A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second conductive material layers. A energy conversion layer is formed in association with the phase change material layer, and electrically coupled to a third conductive material layer. An electrically isolating material layer is formed between the phase change material layer and the energy conversion layer.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: February 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Mike Violette, Jon Daley
  • Patent number: 8652897
    Abstract: Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngkuk Kim, Insang Jeon, Youngseok Kim, Young-Lim Park, Ho-Kyun An
  • Patent number: 8652884
    Abstract: The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits.
    Type: Grant
    Filed: February 27, 2011
    Date of Patent: February 18, 2014
    Assignee: The Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang
  • Publication number: 20140043894
    Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Ugo Russo, Andrea Redaelli, Fabio Pellizzer
  • Publication number: 20140036568
    Abstract: A resistive random access memory (ReRAM) device can comprise a first metal layer and a first metal-oxide layer on the first metal layer. The first metal-oxide layer comprises the first metal. A second metal layer can comprise a second metal over and in physical contact with the first metal-oxide layer. A first continuous non-conductive barrier layer can be in physical contact with sidewalls of the first metal layer and sidewalls of the first metal-oxide layer. A second metal-oxide layer can be on the second metal layer. The second metal-oxide layer can comprise the second metal layer. A third metal layer can be over and in physical contact with the second metal-oxide layer. The first and second metal-oxide layers, are further characterized as independent storage mediums.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: CHEONG MIN HONG, Feng Zhou
  • Publication number: 20140034892
    Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Davide Erbetta, Luca Fumagalli
  • Patent number: 8642990
    Abstract: A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: February 4, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Patent number: 8642985
    Abstract: A memory cell includes a memory element, a current-limiting element electrically coupled to the memory element, and a high-selection-ratio element electrically coupled to the current-limiting element. The memory element is configured to store data as a resistance state. The current-limiting element is a voltage-controlled resistor (VCR) having a resistance that decreases when a voltage applied thereto increases. The high-selection-ratio element has a first resistance that is small when a voltage applied to the memory cell is approximately equal to a selection voltage of the memory cell, and has a second resistance that is substantially larger than the first resistance when the voltage applied to the memory cell is approximately equal to one-half of the selection voltage.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 4, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Frederick T. Chen, Heng-Yuan Lee, Yu-Sheng Chen
  • Publication number: 20140027705
    Abstract: A memristor array includes a lower layer of crossbars, upper layer of crossbars intersecting the lower layer of crossbars, memristor cells interposed between intersecting crossbars, and pores separating adjacent memristor cells. A method forming a memristor array is also provided.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Inventors: Jianhua Yang, Minxian Max Zhang, Gilberto Medeiros Ribeiro, R. Stanley Williams
  • Patent number: 8637413
    Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: January 28, 2014
    Assignees: Sandisk 3D LLC, Kabushiki Kaisha Toshiba
    Inventors: Charlene Chen, Dipankar Pramanik
  • Patent number: 8637843
    Abstract: Disclosed herein is a device that includes: an interlayer insulation film having a through hole; and a phase change storage element provided in the through hole. The phase change storage element includes: an outer electrode being a conductive film of cylindrical shape and being formed along an inner wall of the through hole; a buffer insulation film being an insulation film of cylindrical shape and being formed along an inner wall of the outer electrode, an upper end of the buffer insulation film being recessed in part to form a recess; a phase change film filling an interior of the recess; and an inner electrode being a conductive film formed along an inner wall of the buffer insulation film including a surface of the phase change film.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 28, 2014
    Inventor: Isamu Asano
  • Publication number: 20140021431
    Abstract: Some embodiments include a construction having oxygen-sensitive structures directly over spaced-apart nodes. Each oxygen-sensitive structure includes an angled plate having a horizontal portion along a top surface of a node and a non-horizontal portion extending upwardly from the horizontal portion. Each angled plate has an interior sidewall where an inside corner is formed between the non-horizontal portion and the horizontal portion, an exterior sidewall in opposing relation to the interior sidewall, and lateral edges. Bitlines are over the oxygen-sensitive structures, and have sidewalls extending upwardly from the lateral edges of the oxygen-sensitive structures. A non-oxygen-containing structure is along the interior sidewalls, along the exterior sidewalls, along the lateral edges, over the bitlines, and along the sidewalls of the bitlines. Some embodiments include memory arrays, and methods of forming memory cells.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Fabio Pellizzer, Cinzia Perrone
  • Patent number: 8633465
    Abstract: The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 21, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Gengyu Yang, Yimao Cai, Yu Tang, Lijie Zhang, Yue Pan, Shenghu Tan, Yinglong Huang
  • Patent number: 8618523
    Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Norikatsu Takaura, Yuichi Matsui, Motoyasu Terao, Yoshihisa Fujisaki, Nozomu Matsuzaki, Kenzo Kurotsuchi, Takahiro Morikawa