Abstract: An exemplary embodiment of a non-volatile memory includes a bottom conductive layer, a resistive switching layer, an oxygen vacancy barrier layer and an upper conductive layer. The resistive switching layer is disposed on the bottom conductive layer. The oxygen vacancy barrier layer is disposed on the resistive switching layer. The upper conductive layer is disposed on the oxygen vacancy barrier layer.

Abstract: Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell.

Abstract: Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, due to the addition of a current limiting component. In one embodiment, the current limiting component comprises a resistive material configured to improve the switching performance and lifetime of the resistive switching memory element. The electrical properties of the current limiting layer are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element found in the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide layer that is a current limiting material and an oxygen barrier layer that is an oxygen deficient material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Abstract: A data storage and a semiconductor memory device including the same are provided, the data storage including a lower electrode, a first discharge prevention layer stacked on the lower electrode, a phase-transition layer on the first discharge prevention layer, a second discharge prevention layer stacked on the phase-transition layer, and an upper electrode stacked on the second discharge prevention layer. The phase transition layer includes oxygen and exhibits two different resistance characteristics depending on whether an insulating property thereof changed. The first and second discharge prevention layers block discharge of the oxygen from the phase transition layer.

Abstract: The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.

Abstract: Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices.

Abstract: Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a conductive material in a number of vias and on a substrate structure, the conductive material to serve as a number of conductive lines of the array and coupling the number of conductive lines to the array circuitry.

Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: A semiconductor memory device includes an isolation layer formed in a substrate and defining an active region, a trench formed in the substrate and defining a part of the active region as an active pillar; a word line formed inside the trench, a sub-source line formed under the trench and crossing the word line, a main source line formed over the substrate, coupled to the sub-source line, and crossing the word line, a variable resistor pattern formed over the active pillar, and a bit line contacting the variable resistor pattern and crossing the word line.

Abstract: A method of fabricating a programmable memory microelectronic device includes depositing onto a first electrode an intermediate layer of a material having a chalcogenide; depositing an ionizable metallic layer on the intermediate layer; irradiating with ultraviolet radiation the ionizable metallic layer so that metallic ions from the ionizable metallic layer diffuse into the intermediate layer to form a chalcogenide material containing metallic ions, and depositing a second electrode on the layer of chalcogenide material containing metallic ions obtained in the prior step. The second and third steps are repeated at least n times, where n is an integer greater than or equal to 1. The ionizable metallic layer deposited during the second step has a sufficiently small thickness that the metallic ions may be diffused totally during the irradiation (third) step.

Abstract: Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material.

Abstract: Electronic apparatus, systems, and methods include a resistive random access memory cell having an oxygen gradient in a variable resistive region of the resistive random access memory cell and methods of forming the resistive random access memory cell. Oxygen can be incorporated into the resistive random access memory cell by ion implantation. Additional apparatus, systems, and methods are disclosed.

Abstract: The present invention generally relates to the three-dimensional arrangement of memory cells. This 3D arrangement and orientation is made with macro cells that enable the programming, reading and/or querying of any memory cell in the 3D array without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. The individual macro cells are electrically coupled together such that a single transistor on the substrate can be utilized to address multiple macro cells. In such an arrangement, all the auxiliary circuits for addressing memory elements are simplified thereby diminishing their integrated circuit area.

Abstract: Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.

Abstract: Disclosed herein is a novel charging controlled RRAM (Resistance Random Access Memory), and various methods of making such a charging controlled RRAM device. In one example, a device disclosed herein includes a first word line structure formed above a substrate, wherein the first word line structure includes a gate electrode and a nano-crystal containing layer of insulating material, a second word line structure formed above the substrate, wherein the second word line structure comprises a gate electrode and a nano-crystal containing layer of insulating material, a first implant region formed in the substrate proximate the first word line structure, wherein the first implant region defines a first bit line, and a second implant region formed in the substrate proximate the second word line structure, wherein the second implant region defines a second bit line.

Abstract: A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.

Abstract: The capability of retaining a resistance value of a stored state and an erased state is improved in a resistance variation-type memory device. A memory layer 5 including a high-resistance layer 2 and an ion source layer 3 is provided between a lower electrode 1 and an upper electrode 4. The ion source layer 3 contains Al (aluminum) as an additive element together with an ion conductive material such as S (sulfur), Se (selenium), and Te (tellurium) (chalcogenide element) and a metal element to be ionized such as Zr (zirconium). Since Al is included in the ion source layer 3, the high-resistance layer which includes Al (Al oxide) is formed on an anode in erasing operation. Thus, a retaining property in a high-resistance state improves, and at the same time, an operating speed is improved.

Abstract: Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material. The ion source material may include at least one of a chalcogenide material and a metal. Apparatuses, such as systems and devices, include a plurality of such memory cells. Memory cells include an adhesion material of metal silicide between a ion source material and an electrode of elemental metal. Methods of forming a memory cell include forming a first electrode, forming an active material, forming an ion source material, and forming a second electrode including metal silicide over the metal ion source material. Methods of adhering a material including copper and a material including tungsten include forming a tungsten silicide material over a material including copper and treating the materials.

Abstract: A stateful negative differential resistance device includes a first conductive electrode and a second conductive electrode. The device also includes a first material with a reversible, nonvolatile resistance that changes based on applied electrical energy and a second material comprising a differential resistance that is negative in a locally active region. The first material and second material are sandwiched between the first conductive electrode and second conductive electrode. A method for using a stateful NDR device includes applying programming energy to the stateful NDR device to set a state of the stateful NDR device to a predetermined state and removing electrical power from the stateful NDR device. Power-up energy is applied to the stateful NDR device such that the stateful NDR device returns to the predetermined state.

Abstract: A variable resistance nonvolatile memory element capable of suppressing a variation in resistance values is provided.

Abstract: According to one embodiment, a conductive bridging memory device includes a first wiring layer having a plurality of first wiring portions extending in a first direction, a second wiring layer having a plurality of second wiring portions extending in a second direction crossing the first direction, and a resistance change layer provided continuously along a plane having the first direction and the second direction between the first wiring layer and the second wiring layer. Each of the first wiring portions includes a first wiring extending in the first direction. Each of the second wiring portions includes a second wiring extending in the second direction, and an ion metal layer provided between the second wiring and the resistance change layer and extending in the second direction.

Abstract: A multi-terminal programmable element. The programmable element includes a source electrode and a drain electrode on a base. The programmable element includes reference voltage contact that is not in contact with the source or drain electrode. The base includes a transition-metal oxide with oxygen vacancies for drifting under an applied electric field. Further, materials of the source electrode and the base are selected such that an interface of a source and/or drain electrode material and the transition metal oxide base material forms an energy barrier for electron injection from the electrode into the base material. The energy barrier has a height that depends on an oxygen vacancy concentration of the base material. Four non-volatile states are programmable into the programmable element.

Abstract: A stack type memory device includes a semiconductor substrate; a plurality of bit lines arranged and stacked on the semiconductor substrate; a plurality of word lines formed on the plurality of bit lines; a plurality of interconnection units, each extending from a respective word line toward a respective one of the plurality of bit lines; and a plurality of memory cells connected between the plurality of bit lines and the interconnection units extending from the plurality of word lines, respectively.

Abstract: A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.

Abstract: Resistive random access memory (RRAM) devices, and methods of manufacturing the same, include a RRAM device having a switching device, and a storage node connected to the switching device, wherein the storage node includes a first electrode, a metal oxide layer, and a second electrode sequentially stacked. The metal oxide layer contains a semiconductor material element affecting resistance of the storage node.

Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.

Abstract: A memory device includes a plurality of side-wall electrodes formed on a first side-wall of a trench within an insulating layer over a first plurality of contacts in an array of contacts in a substrate. The plurality of side-wall electrodes contact respective top surfaces of the first plurality of contacts. The side-wall electrodes respectively comprise a layer of tantalum nitride, having a composition TaxNy, where y is greater than x, and a layer of electrode material having a lower electrical resistivity and a lower thermal resistivity than the layer of tantalum nitride. Top surfaces of the plurality of side-wall electrodes contact memory material. A second plurality of side-wall electrodes may be formed on a second side-wall of the trench over a second plurality of contacts in the array of contacts.

Abstract: A resistive memory device may include a substrate, gate electrode structures, a first impurity region, a second impurity region, a first metal silicide pattern and a second metal silicide pattern. The substrate may have a first region where isolation patterns and first active patterns may be alternately arranged in a first direction, and a second region where linear second active patterns may be extended in the first direction. The gate electrode structures may be arranged between the first region and the second region of the substrate. The first and second impurity regions may be formed in the first and second impurity regions. The first metal silicide pattern may have an isolated shape configured to make contact with an upper surface of the first impurity region. The second metal silicide pattern may make contact with an upper surface of the second impurity region.

Abstract: Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.

Abstract: The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.

Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.

Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal.

Abstract: A memory device includes a substrate and a memory array on the substrate. The memory array includes memory cells including stressed phase change materials in a layer of encapsulation materials. The memory cells may include memory cell structures such as mushroom-type memory cell structures, bridge-type memory cell structures, active-in-via type memory cell structures, and pore-type memory cell structures. The stressed phase change materials may comprise GST (GexSbxTex) materials in general and Ge2Sb2Te5 in particular. To manufacture the memory device, a substrate is first fabricated. Memory cells including phase change materials in a layer of encapsulation materials are formed on a front side of the substrate. A tensile or compressive stress is induced into the phase change materials on the front side of the substrate.

Abstract: A phase-change memory device comprises a first insulating layer on a substrate and a through hole formed in the first insulating layer. A first phase-change material layer is positioned along lower sidewalls and a lower face of the through hole. A second insulating layer is laterally surrounded by the first phase-change material layer. A second phase-change material layer is positioned along upper sidewalls of the through hole and in contact with upper surfaces of the first phase-change material layer and the second insulating layer.

Abstract: A phase change memory device including a multi-level cell and a method of manufacturing the same are provided. The device includes a first phase-change material layer to which a current is provided from a heating electrode, and a second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from a heating electrode.

Abstract: Provided is a resistive memory device and a method of manufacturing the resistive memory device that includes a bottom electrode, an insulating layer that is formed on the bottom electrode and has a hole that exposes the bottom electrode, a resistance layer and an intermediate layer which are formed in the hole, a switch structure formed on a surface of the intermediate layer, and an upper electrode formed on the switch structure.

Abstract: The present invention relates to a transparent memory for a transparent electronic device. The transparent memory includes: a lower transparent electrode layer that is sequentially formed on a transparent substrate, and a data storage region and an upper transparent layer which are made of at least one transparent resistance-variable material layer. The transparent resistance-variable material layer has switching characteristics as a result of the resistance variance caused by the application of a certain voltage between the lower and upper transparent electrode layers. An optical band gap of the transparent resistance-variable material layer is 3 eV or more, and transmittivity of the material layer for visible rays is 80% or more. The invention provides transparent and resistance-variable memory that: has very high transparency and switching characteristics depending on resistance variation at a low switching voltage, and can maintain the switching characteristics thereof after a long time elapses.

Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

Abstract: A phase change memory device for preventing thermal cross-talk includes lower electrodes respectively formed in a plurality of phase change cell regions of a semiconductor substrate. A first insulation layer is formed on the semiconductor substrate including to the lower electrodes having holes for exposing the respective lower electrodes. Heaters are formed on the surfaces of the respective holes to contact the lower electrodes. A second insulation layer is formed to fill the holes in which the heaters are formed. A mask pattern is then formed on the first and second insulation layers, including the heaters, to have openings that expose portions of the respective heaters having a constant pitch. A phase change layer is formed on the mask pattern including the exposed portions of the heaters and the first and second insulation layers and subsequently, upper electrodes are formed on the phase change layer.

Abstract: A memory cell structure and method to form such structure. An example memory cell includes a bottom electrode formed within a substrate. The memory cell also includes a phase change memory element in contact with the bottom electrode. The memory cell includes a liner laterally surrounding the phase change memory element. The liner includes dielectric material that is thermally conductive and electrically insulating. The memory cell includes an insulating dielectric layer laterally surrounding the liner. The insulating dielectric layer includes material having a lower thermal conductivity than that of the liner.

Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a memory element and a first electrode having an inner surface surrounding the memory element to contact the memory element at a first contact surface. The device includes a second electrode spaced away from the first electrode, the second electrode having an inner surface surrounding the memory element to contact the memory element at a second contact surface.

Abstract: To provide a semiconductor memory device comprising a plurality of silicon pillars arranged in a matrix, whose sidewalls are provided with gate electrodes with gate insulating films interposed between the silicon pillars and the gate electrodes and whose top ends are electrically connected to memory elements, and a bit line and a word line provided between the silicon pillars so as to be orthogonal to each other. The bit line is electrically connected to a bottom end of the silicon pillars on both sides of the bit line in alternate rows, and the word line is electrically connected to a gate electrode formed on a sidewall of the silicon pillars on both sides of the word line in alternate columns.

Abstract: A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

Abstract: A mixed ionic-electronic conduction (MIEC) memory cell including a mixed ionic-electronic conductor containing dopants therein, a heater disposed adjacent to the mixed ionic-electronic conductor, a pair of first electrodes electrically connected to the mixed ionic-electronic conductor, and at least one pair of second electrodes electrically connected to the mixed ionic-electronic conductor is provided. The pair of first electrodes drive the dopants in the mixed ionic-electronic conductor to drift along a first direction when the mixed ionic-electronic conductor is heated by the heater. The pair of second electrodes locally modify a distribution of the dopants along a second direction when the mixed ionic-electronic conductor is heated by the heater, and the first direction is different from the second direction.

Abstract: A memory element (ME) including at least one layer of conductive metal oxide (CMO) that includes mobile oxygen ions and including at least two layers of insulating metal oxide (IMO) is disclosed. In one configuration a layer of IMO that is directly in contact with a CMO layer is specifically selected so that a material of the IMO layer is non-reactive with a material of the CMO. In another configuration, at least one pair of adjacent IMO layers are made from materials having different band gaps operative to an generate an internal electric field positioned in the layers and present in the at least two adjacent IMO layers in the absence of electrical power. The internal electric field can be a static electric field. The IMO and/or CMO layers can be deposited in part or in whole using ALD, PEALD, or nano-deposition. The ME can be formed BEOL.

Abstract: In some aspects, a reversible resistance-switching metal-insulator-metal stack is provided that includes a first conducting layer, a carbon nano-tube (“CNT”) material above the first conducting layer, a second conducting layer above the CNT material, and an air gap between the first conducting layer and the CNT material. Numerous other aspects are provided.

Abstract: In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

Abstract: A highly integrated programmable non-volatile memory and a manufacturing method thereof are provided. More particularly, a memory device including an antifuse and a diode, or a variable resistor and a diode, an operation method thereof, and a manufacturing method of a plurality of memory cells capable of increasing the integration density by utilizing a vertical space are provided. The highly integrated programmable non-volatile memory includes first stepped cells and second stepped cells formed to have different heights. The first stepped cells are formed on a horizontal plane with a high height, and the second stepped cells are formed on a horizontal plane with a low height.

Abstract: According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.