Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed therefrom.

Abstract: A new devices structure of nano tunneling field effect transistor based on nano metal particles is introduced. The nano semiconductor device, comprising a source and a drain, wherein each of the source and drain comprise an implanted nano cluster of metal atoms, wherein the implanted nano cluster of metal atoms forming the source has an average radius in the range from about 1 to about 2 nanometers, and the implanted nano cluster of metal atoms forming the drain has an average radius in the range from about 2 to about 4 nanometers. Processes for producing the nano semiconductor device are detailed.

Abstract: One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between the first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. Additional examples of the present invention include integrated circuits that contain multiple nanoscale electronic devices that each includes an anisotropic dielectric material layered between first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material.

Abstract: A method for fabricating a III-nitride based semiconductor device, including (a) growing one or more buffer layers on or above a semi-polar or non-polar GaN substrate, wherein the buffer layers are semi-polar or non-polar III-nitride buffer layers; and (b) doping the buffer layers so that a number of crystal defects in III-nitride device layers formed on or above the doped buffer layers is not higher than a number of crystal defects in III-nitride device layers formed on or above one or more undoped buffer layers. The doping can reduce or prevent formation of misfit dislocation lines and additional threading dislocations. The thickness and/or composition of the buffer layers can be such that the buffer layers have a thickness near or greater than their critical thickness for relaxation. In addition, one or more (AlInGaN) or III-nitride device layers can be formed on or above the buffer layers.

Abstract: One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between the first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. Additional examples of the present invention include integrated circuits that contain multiple nanoscale electronic devices that each includes an anisotropic dielectric material layered between first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material.

Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.

Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Abstract: A photo detector is provided with a plurality of quantum dot layers and first conductive type contact layers provided at both sides of the plurality of quantum dot layers so as to sandwich them; a second conductive type impurity is doped in a first semiconductor layer formed between one first conductive type contact layer and a first quantum dot layer which is closest to the one first conductive type contact layer so that it results in a barrier against a carrier positioned at the one first conductive contact layer.

Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such quantum computational systems may include quantum computers, quantum cryptography systems, quantum information processing systems, quantum storage media, and special purpose quantum simulators.

Abstract: A computer-implemented method for encryption and decryption using a quantum computational model is disclosed. Such a method includes providing a model of a lattice having a system of non-abelian anyons disposed thereon. From the lattice model, a first quantum state associated with the lattice is determined. Movement of non-abelian anyons within the lattice is modeled to model formation of first and second quantum braids in the space-time of the lattice. The first quantum braid corresponds to first text. The second quantum braid corresponds to second text. A second quantum state associated with the lattice is determined from the lattice model after formation of the first and second quantum braids has been modeled. The second quantum state corresponds to second text that is different from the first text.

Abstract: Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell.

Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed therefrom.

Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.

Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.

Abstract: Described is a scalable quantum computer that includes at least two classical to quantum interface devices, with each being connected to a distinct quantum processing unit (QPU). An Einstein-Podolsky-Rosen pair generator (EPRPG) is included for generating an entangled Einstein-Podolsky-Rosen pair that is sent to the QPUs. Each QPU is quantumly connected with the EPRPG and is configured to receive a mobile qubit from the EPRPG and perform a sequence of operations such that the mobile qubit interacts with a source qubit when a teleportation algorithm is initiated, leaving a second mobile qubit in the original quantum state of the source qubit.

Abstract: A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.

Abstract: An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the ?=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two ?-quasiparticles. which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the ?=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a ?/8 gate may be effected.

Abstract: A fabrication method is used in conjunction with a semiconductor device having a metal oxide active layer less than 100 nm thick and the upper major surface and the lower major surface have material in abutting engagement to form underlying interfaces and overlying interfaces. The method of fabrication includes controlling interfacial interactions in the underlying interfaces and the overlying interfaces to adjust the carrier density in the adjacent metal oxide by selecting a metal oxide for the metal oxide active layer and by selecting a specific material for the material in abutting engagement. The method also includes one or both steps of controlling interactions in underlying interfaces by surface treatment of an underlying material forming a component of the underlying interface and controlling interactions in overlying interfaces by surface treatment of the metal oxide film performed prior to deposition of material on the metal oxide layer.

Abstract: The Bell-state analyzer includes a semiconductor device having quantum dots formed therein and adapted to support Fermions in a spin-up and/or spin-down states. Different Zeeman splittings in one or more of the quantum dots allows resonant quantum tunneling only for antiparallel spin states. This converts spin parity into charge information via a projective measurement. The measurement of spin parity allows for the determination of part of the states of the Fermions, which provides the states of the qubits, while keeping the undetermined part of the state coherent. The ability to know the parity of qubit states allows for logic operations to be performed on the qubits, i.e., allows for the formation of (two-qubit) quantum gates, which like classical logic gates, are the building blocks of a quantum computer. Quantum computers that perform a parity gate and a CNOT gate using the Bell-state analyzer of the invention are disclosed.

Abstract: The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting nanowire. The present invention provides structures and devices comprising conductive nanowire segments and conductance constricting nanowire segments having accurately selected phases including crystalline and amorphous states, compositions, morphologies and physical dimensions, including selected cross sectional dimensions, shapes and lengths along the length of a nanowire. Further, the present invention provides methods of processing nanowires capable of patterning a nanowire to form a plurality of conductance constricting segments having selected positions along the length of a nanowire, including conductance constricting segments having reduced cross sectional dimensions and conductance constricting segments comprising one or more insulating materials such as metal oxides.

Abstract: Ionisation of one of a pair of dopant atoms in a substrate creates a double well potential, and a charge qubit is realised by the location of one or more electrons or holes within this potential. The dopant atoms may comprise phosphorous atoms, located in a silicon substrate. A solid state quantum computer may be formed using a plurality of pairs of dopant atoms, corresponding gate electrodes, and read-out devices comprising single electron transistors.

Abstract: A high speed and miniature detection system, especially for electromagnetic radiation in the GHz and THz range comprises a semiconductor structure having a 2D charge carrier layer or a quasi 2D charge carrier layer with incorporated single or multiple defects, at least first and second contacts to the charge carrier layer, and a device for measuring photovoltage between the first and second contacts. System operation in various embodiments relies on resonant excitation of plasma waves in the semiconductor structure.

Abstract: A spin transistor comprises a semiconductor substrate part having a lower cladding layer, a channel layer and an upper cladding layer sequentially stacked therein, a ferromagnetic source and drain on the substrate part, and a gate on the substrate part to control spins of electrons passing through the channel layer. The lower cladding layer comprises a first lower cladding layer and a second lower cladding layer having a higher band gap than that of the first lower cladding layer. The upper cladding layer comprises a first upper cladding layer and a second upper cladding layer having a higher band gap than that of the first upper cladding layer. The source and the drain are buried in an upper surface of the substrate part and extend downwardly to or under the first upper cladding layer.

Abstract: A functional device which is composed of a nanometer-sized functional structure, which can reduce connection resistance in connecting the functional structure to an external electrode, and which includes a wiring section capable of minimizing constraints given to structural designs of various functional structures, and a method of manufacturing it are provided. A functional device in which a functional structure having contained sections in positions spaced from each other is retained by a carbon nanotube. A gap is formed in the carbon nanotube, and the carbon nanotube is segmented into a first carbon nanotube and a second carbon nanotube by the gap. One of the contained sections is contained in the first carbon nanotube at an opening of the first carbon nanotube facing the gap, and the other of the contained sections is contained in the second carbon nanotube at an opening of the second carbon nanotube facing the gap.

Abstract: A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.

Abstract: A method for forming arrays of metal, alloy, semiconductor or magnetic nanoparticles is described. An embodiment of the method comprises placing a scaffold on a substrate, the scaffold comprising, for example, polynucleotides and/or polypeptides, and coupling the nanoparticles to the scaffold. Methods of producing arrays in predetermined patterns and electronic devices that incorporate such patterned arrays are also described.

Abstract: Disclosed herein is a spin transistor including: a semiconductor substrate having a channel layer formed therein; first and second electrodes which are formed to be spaced apart from each other on the substrate at a predetermined distance along a longitudinal direction of the channel layer; a source and drain which include magnetized ferromagnetic materials and are formed to be spaced apart form each other between the first electrode and the second electrode at a predetermined distance along the longitudinal direction of the channel layer; and a gate which is formed on the substrate between the source and the drain, and adjusts spin orientations of electrons passing through the channel layer, wherein the electrons passing through the channel layer are spin-aligned at a lower side of the source by a stray magnetic field of the source and spin-filtered at a lower side of the drain by a stray field of the drain.

Abstract: A micro electronic component, preferably in the form of an electronic memory, includes the use of clusters as an electronic memory. Also disclosed as part of the present invention is a method for fabricating a micro electronic component. The present invention contemplates fabrication of an especially compact electronic memory that works especially with single-electron transistors or single-electronic transfers. According to the present invention, clusters with a metallic cluster nucleus are arranged in parallel grooves essentially in lines or rows and are connected individually to first and second connecting electrodes, such that individually the clusters can be electrically modified or polled independently of each other.

Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Abstract: The present invention provides an optical device integrating an active device with a passive device without any butt joint structure between two devices. The optical integrated device of the invention includes a GaAs substrate, first and second cladding layers, and an active layer sandwiched by the first and second cladding layers. These layers are disposed on the GaAs substrate. The GaAs substrate provides a first region and a second region. The active layer comprises of the first active layer disposed on the first region and the second active layer disposed on the second region of the GaAs substrate. The first active layer has a quantum well structure whose band-gap energy smaller than 1.3 eV, while the second active layer has a quantum well structure whose band-gap energy is greater than that of the first active layer.

Abstract: An optical device with a quantum well is provided. The optical device includes an active layer made of a Group III-V semiconductor compound and having a quantum well of a bandgap grading structure in which conduction band energy and valence band energy change linearly with a slope with the content change of predetermined components while an energy bandgap between the conduction band energy and the valence band energy is maintained at a predetermined value; and two barrier layers, one of which is positioned on an upper surface of the active layer and the other is positioned on a lower surface of the active layer, and which are made of a Group III-V semiconductor compound and have higher conduction band energy and lower valence band energy than the active layer. A driving voltage is decreased and luminous efficiency and reliability are enhanced.

Abstract: Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped polysilicon (4.1 eV) or aluminum metal (4.1 eV) for gates or capacitor plates.

Abstract: A method of forming the active region of an optoelectronic device incorporating semiconductor quantum dots whose ground state emission occurs at wavelengths beyond 1350 nm at a temperature of substantially 293 K is provided by forming a first layer of quantum dots covered by a spacer layer with strained areas extending there through. The spacer layer then forms a template upon which quantum dots of an active layer may be formed with a surface with a surface density and formation that is influenced by the underlying first layer of quantum dots. This allows a choice of growth parameters more favourable to the formation of quantum dots in the active layer emitting at long wavelengths with a narrow inhomogeneous broadening. As an example, the active layer of quantum dots may be formed at a lower temperature than the first layer of quantum dots.