Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

Abstract: The present disclosure concerns an image sensor comprising a set of pixels, wherein each pixel of the set comprises a first and a second element, the first element comprising a photodiode module unit, and the second element being an element for filtering color and focusing incident light into said first element. The image sensor further comprises at least two consecutive pixels from the set of pixels, for which first elements are put side by side, and wherein the image sensor comprises a gap between second elements of said at least two consecutive pixels.

Abstract: A transistor is formed having a thin film metal channel region. The transistor may be formed at the surface of a semiconductor substrate, an insulating substrate, or between dielectric layers above a substrate. A plurality of transistors each having a thin film metal channel region may be formed. Multiple arrays of such transistors can be vertically stacked in a same device.

Abstract: A new devices structure of nano tunneling field effect transistor based on nano metal particles is introduced. The nano semiconductor device, comprising a source and a drain, wherein each of the source and drain comprise an implanted nano cluster of metal atoms, wherein the implanted nano cluster of metal atoms forming the source has an average radius in the range from about 1 to about 2 nanometers, and the implanted nano cluster of metal atoms forming the drain has an average radius in the range from about 2 to about 4 nanometers. Processes for producing the nano semiconductor device are detailed.

Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.

Abstract: An organic thin film transistor substrate includes a gate line formed on a substrate, a data line intersecting the gate line and defining a subpixel area, an organic thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and an organic semiconductor layer forming a channel between the source and drain electrodes, a passivation layer parallel with the gate line, for covering the organic semiconductor layer and peripheral regions of the organic semiconductor layer, and a bank insulating layer for determining the position of the organic semiconductor layer and the passivation layer.

Abstract: The invention provides a transistor having a substrate, a structure supported by the substrate including a source, drain, gate, and channel, wherein the source and the channel are made of different materials, and a tunnel junction formed between the source and the channel, whereby the tunnel junction is configured for injecting carriers from the source to the channel.

Abstract: A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by a first pad region and a second pad region, forming a gate around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the exposed nanowire, removing a second portion of the exposed nanowire to form a cavity defined by the core portion of the nanowire surrounded by the gate structure and the spacer, exposing a silicon portion of the substrate, and epitaxially growing a doped semiconductor material in the cavity from exposed cross section of the nanowire, the second pad region, and the exposed silicon portion to connect the exposed cross sections of the nanowire to the second pad region.

Abstract: A field emission device is provided. The field emission device includes a first substrate including a gate electrode including gate lines respectively extending in first, second, and third direction and a cathode electrode including cathode lines respectively extending in the first, second, and third directions; a second substrate facing the first substrate and including an anode electrode; and a space between the first and second substrates.

Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.

Abstract: Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.

Abstract: Provided is a material composition which allows a nonvolatile memory element made of a perovskite-type transition metal oxide having the CER effect to be formed of three elements, which comprises an electric conductor having a shallow work function or a small electronegativity, such as Ti, as an electrode and a rare earth-copper oxide comprising one type of rare earth element, copper and oxygen, such as La2CuO4, as a material constituting a heterojunction with the electric conductor.

Abstract: A power device package controls heat generation of a power device using a semi-permanent metal-insulator transition (MIT) device instead of a fuse, and emits heat generated by the power device through a small-sized heat sink provided only in one region on the power device, thereby ensuring excellent dissipation of heat. Therefore, the power device package can be usefully applied to any electric/electronic circuit that uses a power device.

Abstract: Provided is a monitoring pattern for a silicide that may include a plurality of poly pads, a plurality of N-well regions and P-well regions, active regions, and a poly gate line. The plurality of poly pads are disposed on a semiconductor substrate. The plurality of N-well regions and P-well regions are disposed in a single line between the poly pads. The active regions are disposed on the N-well and the P-well regions. The poly gate line electrically connects the active regions to the poly pads and has a configuration permitting it to pass through the active regions a plurality of times.

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.

Abstract: An organic thin film transistor substrate includes a gate line formed on a substrate, a data line intersecting the gate line and defining a subpixel area, an organic thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and an organic semiconductor layer forming a channel between the source and drain electrodes, a passivation layer parallel with the gate line, for covering the organic semiconductor layer and peripheral regions of the organic semiconductor layer, and a bank insulating layer for determining the position of the organic semiconductor layer and the passivation layer.

Abstract: Light strips for emergency lighting, path lighting, accent lighting and device lighting are provided. Devices incorporating and lighted by the light strips are also provided. The light strips include a light emitting layer made from a plurality of semiconductor nanoparticles disposed between and in electrical communication with an anode and a cathode. The semiconductor nanoparticles may be made from Group IV semiconductors, such as silicon. Devices that may be lit with the light strips include displays and keypad, such as those found in cellular phones and personal digital assistants.

Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Abstract: Provided is a 2-terminal semiconductor device that uses an abrupt MIT semiconductor material layer. The 2-terminal semiconductor device includes a first electrode layer, an abrupt MIT semiconductor organic or inorganic material layer having an energy gap less than 2eV and holes in a hole level disposed on the first electrode layer, and a second electrode layer disposed on the abrupt MIT semiconductor organic or inorganic material layer. An abrupt MIT is generated in the abrupt MIT semiconductor material layer by a field applied between the first electrode layer and the second electrode layer.

Abstract: A semiconductor device includes a semiconductor substrate and a super junction structure on the substrate. The super junction structure is constructed with p-type and n-type column regions that are alternately arranged. A p-type channel layer is formed to a surface of the super junction structure. A trench gate structure is formed to the n-type column region. An n+-type source region is formed to a surface of the channel layer near the trench structure. A p+-type region is formed to the surface of the channel layer between adjacent n+-type source regions. A p-type body region is formed in the channel layer between adjacent trench gate structures and in contact with the p+-type region. Avalanche current is caused to flow from the body region to a source electrode via the p+-type region without passing through the n+-type source region.

Abstract: A semiconductor memory device includes a variable resistance element including a first electrode, a current path forming region, and a second electrode. The current path forming region includes a first region made of a variable resistance material whose resistivity changes by applying voltage, and a second region formed by doping a metal element to the variable resistance material such that a resistivity of the second region is higher than that of the first region and is not changed by applying a voltage used to change the resistivity of the first region. The first region is in contact with the first electrode and the second electrode, and extends from one electrode side to the other electrode side. The second region is provided outside the first region in at least part of the current path forming region in direction extending from one electrode side to the other electrode side.

Abstract: A robust, stand-alone load cell comprises a block of aligned carbon nanotubes with parallel electrodes on opposing sides of the block and an electrical circuit connected between the electrodes for measuring the electrical resistance of the block. The nanotubes are preferably aligned perpendicular to the electrodes. Carbon nanotube-based load cells may be incorporated into a wafer asssembly for characterizing semiconductor processing equipment. Such a wafer assembly includes two parallel wafers with a plurality of carbon nanotube load cells positioned between and attached to both wafers. The load cells are independently electrically connected to a device which monitors and records the resistivity of the load cell.

Abstract: A programmable dopant fiber includes a plurality of quantum structures formed on a fiber-shaped substrate, wherein the substrate includes one or more energy-carrying control paths, which pass energy to quantum structures. Quantum structures may include quantum dot particles on the surface of the fiber or electrodes on top of barrier layers and a transport layer, which form quantum dot devices. The energy passing through the control paths drives charge carriers into the quantum dots, leading to the formation of “artificial atoms” with real-time, tunable properties. These artificial atoms then serve as programmable dopants, which alter the behavior of surrounding materials. The fiber can be used as a programmable dopant inside bulk materials, as a building block for new materials with unique properties, or as a substitute for quantum dots or quantum wires in certain applications.

Abstract: A vertical transistor with integrated isolation is provided. The vertical transistor includes a vertical semiconductor structure and an isolation layer on a bottom surface of the vertical semiconductor structure. The vertical transistor further includes a plurality of terminals on a top surface of the vertical semiconductor structure.

Abstract: Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

Abstract: Methods for forming carbon silicon alloy (CSA) and structures thereof are disclosed. The method provides improvement in substitutionality and deposition rate of carbon in epitaxially grown carbon silicon alloy layers (i.e., substituted carbon in Si lattice). In one embodiment of the disclosed method, a carbon silicon alloy layer is epitaxially grown on a substrate at an intermediate temperature with a silicon precursor, a carbon (C) precursor in the presence of an etchant and a trace amount of germanium material (e.g., germane (GeH4)). The intermediate temperature increases the percentage of substitutional carbon in epitaxially grown CSA layer and avoids any tendency for silicon carbide to form. The presence of the trace amount of germanium material, of approximately less than 1% to approximately 5%, in the resulting epitaxial layer, has an effect of stabilizing and enhancing deposition/growth rate without compromising the tensile stress of CSA layer formed thereby.

Abstract: An integrated circuit includes a silicon-on-insulator (SOI) substrate including a buried oxide layer positioned between a top-side silicon layer and a bottom-side silicon layer. A micro-electromechanical system (MEMS) device is integrated into the top-side silicon layer. A semiconductor layer is formed over the bottom-side silicon layer. A control circuit is integrated into the semiconductor layer and is configured to control the MEMS device.

Abstract: Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.

Abstract: In a photoelectric conversion device, in a contact between a p-type semiconductor 3a and an electrode 2, an n-type semiconductor 6 of a conductivity type opposite to that of the p-type semiconductor is provided between the p-type semiconductor 3a and the electrode 2. The existence of the n-type semiconductor 6 allows a recombination rate of photo-generated carriers excited by incident light to be effectively reduced, and allows a dark current component to be effectively prevented from being produced. Therefore, it is possible to improve photoelectric conversion efficiency as well as to stabilize characteristics. Further, a tunnel junction is realized by increasing the concentration of a doping element in at least one or preferably both of the p-type semiconductor 3a and the n-type semiconductor 6 in a region where they are in contact with each other, thereby keeping ohmic characteristics between the semiconductor and the electrode good.

Abstract: A method of manufacturing a structure is provided. This method include a steps of preparing a first substrate having a projection, forming a first layer on the projection, transferring the first layer to a second substrate, and removing at least apart of the second substrate.

Abstract: Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Abstract: A method of fabricating a semiconductor device includes forming first spacers formed of a TEOS layer and second spacers formed of a first nitride layer on sidewalls of a gate electrode formed on a semiconductor substrate, and then forming source/drain regions in the semiconductor substrate using the first and second spacers and the gate electrode as masks, and then removing the second spacers, and then depositing a second nitride layer on an entire surface of the semiconductor substrate, and then implanting ions into the second nitride layer to generate compressive stress, and then etching the second nitride layer to form barrier nitride layers on the side walls of the first spacers. Because the barrier nitride has compressive stress, it is possible to prevent the movement of mobile ions, minimize influence on charge loss and charge gain in a flash memory device, and enhance a retention characteristic.

Abstract: Provided is a monitoring pattern for a silicide that may include a plurality of poly pads, a plurality of N-well regions and P-well regions, active regions, and a poly gate line. The plurality of poly pads are disposed on a semiconductor substrate. The plurality of N-well regions and P-well regions are disposed in a single line between the poly pads. The active regions are disposed on the N-well and the P-well regions. The poly gate line electrically connects the active regions to the poly pads and has a configuration permitting it to pass through the active regions a plurality of times.

Abstract: A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern including a protrusion with a lower surface on the substrate and an upper surface opposite the lower surface, a width of the protrusion gradually decreasing from the lower surface to the upper surface, the upper surface of the protrusion being sharp and defining a first active region of the active pattern along a first direction, isolation layer patterns on the substrate in recesses at both sides of the active pattern, the isolation layer patterns exposing the first active region, a gate structure on the first active region and on the isolation layer patterns, the gate structure extending along a second direction, the first and second directions being perpendicular to each other, and source/drain regions under the first active region at both sides of the gate structure.

Abstract: Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity region is provided between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench. Related methods of fabricating semiconductor devices are also provided herein.

Abstract: A semiconductor device includes a semiconductor substrate and a super junction structure on the substrate. The super junction structure is constructed with p-type and n-type column regions that are alternately arranged. A p-type channel layer is formed to a surface of the super junction structure. A trench gate structure is formed to the n-type column region. An n+-type source region is formed to a surface of the channel layer near the trench structure. A p+-type region is formed to the surface of the channel layer between adjacent n+-type source regions. A p-type body region is formed in the channel layer between adjacent trench gate structures and in contact with the p+-type region. Avalanche current is caused to flow from the body region to a source electrode via the p+-type region without passing through the n+-type source region.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device can include a transistor structure, including a gate dielectric on a substrate, a gate electrode on the gate dielectric, a spacer at sidewalls of the gate electrode, and source/drain regions in the substrate; and an interlayer dielectric on the transistor structure where an air gap is provided in a region between the spacer, the interlayer dielectric, and the source/drain region of the substrate.

Abstract: A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

Abstract: A semiconductor device (100) is formed on a semi-insulating semiconductor substrate (101) including a channel layer (104), a spacer layer (105), an electron supply layer (106), and a barrier layer (108). A composite layer (110) is formed over the barrier layer (108). A metal (116) is deposited over the composite layer (110). The metal (116) is annealed to promote a chemical reaction between the metal (116) and the composite layer (110) in which a portion of the metal sinks into the composite layer (110) and forms an ohmic contact with the composite layer.

Abstract: A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: A non-volatile memory device includes a substrate that is divided into a field region and an active region by isolation layer patterns. The active region has an active trench for increasing an effective area of the active region. A tunnel oxide layer is formed on the active region. A floating gate pattern is formed on the tunnel oxide layer to fill up the active trench. A dielectric layer pattern is formed on the floating gate pattern. A control gate pattern is formed on the dielectric layer pattern. Thus, the non-volatile memory device has an increased effective area of the active region so that the non-volatile memory device may have improved operational characteristics.

Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Abstract: The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.

Abstract: A strained HOT MOSFET. The MOSFET includes (a) a first semiconductor layer having a first crystallographic orientation; (b) a buried oxide layer on top of the first semiconductor layer; (c) a second semiconductor layer on top of the buried oxide layer, wherein the second semiconductor layer has a second crystallographic orientation, and wherein the second crystallographic orientation is different from the first crystallographic orientation; (d) a third semiconductor layer on top of the first semiconductor layer, wherein the third semiconductor layer has the first crystallographic orientation; and (e) a fourth semiconductor layer on top of the third semiconductor layer, wherein the fourth semiconductor layer includes a different material than that of the third semiconductor layer, and wherein the fourth semiconductor layer has the first crystallographic orientation.

Abstract: An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains the bipolar transistor. The collector of the bipolar transistor may comprise the floor isolation region. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

Abstract: A thermoelectric conversion material having a novel composition is provided. The thermoelectric conversion material comprises a first dielectric material layer, a second dielectric material layer, and an electron localization layer that is present between the first dielectric material layer and the second dielectric material layer and that has a thickness of 1 nm.