Abstract: A computer-implemented method for encryption and decryption using quantum computational model is disclosed. Such a method includes providing a model of a lattice having a system of non-abelian anyons disposed thereon. From the lattice model, a first quantum state associated with the lattice is determined. Movement of non-abelian anyons within the lattice is modeled to model formation of first and second quantum braids in the space-time of the lattice. The first quantum braid corresponds to first text. The second quantum braid corresponds to second text. A second quantum state associated with the lattice is determined from the lattice model after formation of the first and second quantum braids has been modeled. The second quantum state corresponds to second text that is different from the first text.

Abstract: A magnetoresistive element according to an embodiment includes: a first magnetic layer; a tunnel barrier layer on the first magnetic layer; a second magnetic layer placed on the tunnel barrier layer and containing CoFe; and a nonmagnetic layer placed on the second magnetic layer, and containing nitrogen and at least one element selected from the group consisting of B, Ta, Zr, Al, and Ce.

Abstract: An electron emission element has an electron emission layer that emits an electron from a surface emission portion, a focusing electrode layer that is film-formed on a surface of the electron emission layer via a first insulation layer and focuses the emitted electron, a gate electrode layer that is film-formed on a surface of the focusing electrode layer via a second insulation layer, an emission concave portion that penetrates the gate electrode layer, the second insulation layer, the focusing electrode layer and the first insulation layer and opens in a concave shape on a surface of the surface emission portion, a carbon layer that is film-formed from a surface of the gate electrode layer over an inner peripheral surface of the emission concave portion, and a partial insulation portion that insulates the focusing electrode layer from the carbon layer.

Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.

Abstract: An electron emission element has an electron emission layer that emits an electron from a surface emission portion, a focusing electrode layer that is film-formed on a surface of the electron emission layer via a first insulation layer and focuses the emitted electron, a gate electrode layer that is film-formed on a surface of the focusing electrode layer via a second insulation layer, an emission concave portion that penetrates the gate electrode layer, the second insulation layer, the focusing electrode layer and the first insulation layer and opens in a concave shape on a surface of the surface emission portion, a carbon layer that is film-formed from a surface of the gate electrode layer over an inner peripheral surface of the emission concave portion, and a partial insulation portion that insulates the focusing electrode layer from the carbon layer.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: By means of an RIE etch process for silicon (3), a pin-type structure (4,4a) without crystal defects is formed with high aspect ratio and with nano dimensions on the surface of silicon wafers without any additional patterning measures (e-beam, interference lithography, and the like) by selecting the gas components of the etch plasma in self-organization wherein, among others, a broadband antireflective behaviour is obtained that may be applicable in many fields.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: Provided is a ferroelectric thin film formed on a substrate and having an amount of remanent polarization increased in its entirety. The ferroelectric thin film contains a perovskite-type metal oxide formed on a substrate, the ferroelectric thin film containing a column group formed of multiple columns each formed of a spinel-type metal oxide, in which the column group is in a state of standing in a direction perpendicular to a surface of the substrate, or in a state of slanting at a slant angle in a range of ?10° or more to +10° or less with respect to the perpendicular direction.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, the source wires 126 of a pixel portion 205 are formed of material having low resistance (representatively, aluminum, silver, copper). The source wires of a driving circuit are formed in the same process as the gate wires 162 of the pixel portion and a pixel electrode 163.

Abstract: An SOI device includes an SOI substrate having a stacked structure including a buried oxide layer and a first silicon layer sequentially stacked on a silicon substrate. The SOI substrate possesses grooves having a depth that extends from an upper surface of the first silicon layer to a partial depth of the buried oxide layer. An insulation layer is formed on the lower surfaces of the grooves and a second silicon layer is formed filling the grooves having the insulation layer formed thereon. Gates are formed on the second silicon layer and junction regions are formed in the first silicon layer on both sides of the gates to contact the insulation layer.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a t

Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.

Abstract: A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the sidewalls of the photoresist features by performing for a plurality of cycles. Each cycle comprises depositing a layer on the photoresist layer wherein the deposited layer has a thickness between a monolayer to 20 nm. Features are etched into the layer through the photoresist features. The photoresist layer and sidewall layer are stripped.

Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.