Solid Dielectric Type Patents (Class 29/25.42)
  • Publication number: 20090284897
    Abstract: A collective component has a first region that intersects a conductive paste film for external terminal electrodes in a break line in which break leading holes are arranged and a second region that does not intersect a conductive paste film for external terminal electrodes in the break line. The first break leading holes are formed in the first region so as not to reach the second region. The second break leading holes are formed only in the second region or from the second region to a portion of the first region. The pitch of the first break leading holes is wider than the pitch of the second break leading holes.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 19, 2009
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroto Itamura
  • Patent number: 7617577
    Abstract: A digital variable capacitor package is provided as having a ground plane disposed on predetermined portion of the top surface of a substrate. An elongated signal electrode may also be disposed on the substrate and including a first end defining an input and a second end extending to a substantially central region of the top surface of the substrate. This elongated signal electrode is disposed to be electrically isolated from the ground plane. A number of elongated cantilevers are disposed on the substrate and each include first ends coupled to the second end of the signal electrode and each further include second ends suspended over different predetermined portions of the ground plane. In operation, one or more of the cantilevers may be actuated to move portion thereof into close proximity to the ground plane for providing one or more discrete capacitance values.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: November 17, 2009
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: John L. Ebel, Rebecca Cortez, Richard E. Strawser, Kevin D. Leedy
  • Patent number: 7614142
    Abstract: A method for fabricating an interposer includes: forming on one primary surface of a first substrate a thin-film capacitor including a first capacitor electrode, a crystalline capacitor dielectric film formed on the first electrode and a second capacitor electrode formed on the dielectric film; and forming on the primary surface of the first substrate and the capacitor a first layer as semi-cured, and a first partial electrode to be a part of a through-electrode, buried in the first resin layer and electrically connected to the first electrode or the second electrode.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: November 10, 2009
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
  • Patent number: 7612983
    Abstract: A monolithic ceramic electronic component includes a ceramic laminate provided with ceramic layers and internal electrode layers disposed between the ceramic layers such that a portion of each internal electrode is led to an end surface of the ceramic laminate and the external electrode disposed on the end surface of the ceramic laminate to which the internal electrode layers are led, so as to connect to the internal electrode layers. At least one end portion in a longitudinal direction of an exposed portion of the internal electrode layer led to and exposed at the end surface of the ceramic laminate is covered with a glass film, and the internal electrodes and the external electrode are electrically connected to each other at a portion not covered with the glass film in the exposed portion of the internal electrode layer.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: November 3, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kiyotaka Maegawa, Mitsuhiro Kusano
  • Patent number: 7610679
    Abstract: There is disclosed a method of producing an inkjet printhead including a cavity unit having therein ink passages and formed by stacking a plurality of kinds of flat plates each of which has a specific ink-passage pattern for constituting the ink passages.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: November 3, 2009
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Atsushi Ito
  • Publication number: 20090268373
    Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.
    Type: Application
    Filed: July 2, 2009
    Publication date: October 29, 2009
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Motohiko SATO, Kazuhiro HAYASHI, Akifumi TOSA, Kenji MURAKAMI, Tomohide YAMADA, Motonobu KURAHASHI
  • Publication number: 20090268368
    Abstract: A rolled film capacitor is disclosed which includes a first dielectric film and a second dielectric film, which are wound along their length dimension to form alternating turns of the winding. A plurality of first conductive segments are arranged on a first surface of the first dielectric film along the length dimension of the first dielectric film, and a plurality of second conductive segments are arranged on a surface of the second dielectric film along the length dimension of the second dielectric film, or on a second surface of the first dielectric film along the length dimension of the first dielectric film. The first conductive segments can have a progressively increasing length along the length dimension of the first dielectric film, and the second conductive segments have a progressively increasing length along the length dimension of the first or second dielectric film. The number of the first and/or second conductive segments per turn of the winding can be equal to or more than one.
    Type: Application
    Filed: June 18, 2009
    Publication date: October 29, 2009
    Applicant: ABB RESEARCH LTD
    Inventors: Henning Fuhrmann, Joerg Ostrowski, Johan Mood
  • Patent number: 7602600
    Abstract: A tantalum capacitor includes: sintered bodies which are disposed at intervals and respectively have first surfaces forming the same surface; and electrode rods which respectively extend into the tantalum sintered bodies and project from the first surfaces of the tantalum sintered bodies. The tantalum capacitor further includes: layers composed of an oxide film layer, a functional polymer layer or a manganese layer, and a carbon layer which are sequentially laminated on surfaces of each of the tantalum sintered bodies excluding the first surface; a conductive layer which covers outside surfaces of the tantalum sintered bodies excluding the first surfaces; and an electrode plate having openings respectively formed at positions corresponding to the first surfaces of the tantalum sintered bodies so that the electrode rods are exposed through the openings. The electrode plate is connected to the conductive layer and spreads across the first surfaces of the tantalum sintered bodies.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: October 13, 2009
    Assignee: Fujitsu Limited
    Inventor: Masayuki Itoh
  • Publication number: 20090251847
    Abstract: The capacitor has a monolithic anode and at least one anode lead wire extending from the anode. At least one sacrificial lead wire extends from the anode. A dielectric layer is on said anode and a cathode layer is on the dielectric layer. The anode lead wire is in electrical contact with the anode and a cathode lead is in electrical contact with the cathode.
    Type: Application
    Filed: April 3, 2008
    Publication date: October 8, 2009
    Inventors: Erik Reed, David Jacobs, Randolph S. Hahn
  • Publication number: 20090251846
    Abstract: An embedded capacitor including a dielectric layer disposed between opposing faces of electrodes, in which the dielectric layer includes a high-loss dielectric layer and one or more insulating layers in contact with the high-loss dielectric layer. The dielectric layer may have a two-layer structure or a three-layer structure in which an insulating layer is additionally interposed between the high-loss dielectric layer and the electrode, thereby decreasing the dielectric loss while maintaining a high dielectric constant, compared to capacitors including a single-layer dielectric structure.
    Type: Application
    Filed: October 6, 2008
    Publication date: October 8, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Chan LEE, Eun Sung LEE, Yoo Seong YANG
  • Patent number: 7596842
    Abstract: The invention concerns a method of making multilayered constructions useful in forming capacitors and resistors, which may be used in the manufacture of printed circuit boards and microelectronic devices. According to the inventive method, a thermosetting polymer layer or layers are attached directly onto a heat resistant film layer, specifically on the side(s) of the heat resistant film to be attached to an electrically conductive layer having an electrical resistance material layer thereon. Attaching the adhesive to the heat resistant film rather than the electrically conductive layer streamlines the manufacturing process, particularly in the formation of the electrical resistance material layer onto the electrically conductive layer. This also results in better precision and uniformity of the multilayered construction.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: October 6, 2009
    Assignee: Oak-Mitsui Inc.
    Inventors: John A. Andresakis, Pranabes K. Pramanik
  • Patent number: 7596841
    Abstract: An electromechanical device includes a support structure formed by attaching inner surfaces of second and third substrates to a first substrate. The support structure includes at least one cavity between the second and third layers. An electromechanical active element is provided on an outer surface of at least one of the second or third layers.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: October 6, 2009
    Assignees: Agency for Science Technology and Research, Sony Corporation
    Inventors: Kui Yao, Xiao Song Eric Tang, Peng Gao, Xujiang He, Jian Zhang, Santiranjan Shannigrahi
  • Publication number: 20090244809
    Abstract: A thin-film device includes a substrate, and a capacitor provided on the substrate. The capacitor incorporates a lower conductor layer having a top surface and a side surface; a flattening film disposed to cover the top and side surfaces of the lower conductor layer; a dielectric film disposed on the flattening film; and an upper conductor layer disposed on the dielectric film. The lower conductor layer is composed of an electrode film and a plating film disposed on the electrode film. The dielectric film has a thickness that falls within a range of 0.02 to 1 ?m inclusive and that is smaller than a thickness of the lower conductor layer. A surface roughness in maximum height of a top surface of the flattening film is smaller than that of the top surface of the lower conductor layer and equal to or smaller than the thickness of the dielectric film.
    Type: Application
    Filed: June 5, 2009
    Publication date: October 1, 2009
    Applicant: TDK CORPORATION
    Inventors: Hajime Kuwajima, Masahiro Miyazaki, Akira Furuya
  • Patent number: 7594309
    Abstract: A method of producing a laminate-type piezoelectric element, wherein a ceramic laminated body therein is formed through an intermediate laminated body-forming step of forming an intermediate laminated body 100 by alternately laminating green sheets 110 that serve as the piezoelectric layers and the inner electrode layers 20, and a calcining step of forming the ceramic laminated body by calcining the intermediate laminated body 100. In the intermediate laminated body-forming step, an overlapped portion 108 and a non-overlapped portion 109 are formed in the intermediate laminated body 100, and voids 40 are formed, in advance, in at least part of the portion that becomes the non-overlapped portion 109. In the calcining step, relaxing layers including the voids 40 are formed.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 29, 2009
    Assignee: Denso Corporation
    Inventors: Akio Iwase, Shige Kadotani, Tetsuji Itou
  • Patent number: 7587821
    Abstract: A method of manufacturing an inkjet head at a low cost is provided. The inkjet head has a passage unit. A plurality of plates are laminated together to form the passage unit. The passage unit has individual ink passages that extend in the plate laminating direction. When the passage unit is to be manufactured, communication holes that will become individual ink passages later will first be formed in the plurality of plates that form the passage unit. All of the plates in which the communication holes are formed will be laminated together with a thermosetting adhesive. The laminated plates will be heated and pressure will be applied thereto. In this way, all of the plates will be simultaneously adhered. An ink passage unit can be manufactured in one adhesion step. The manufacturing costs of the ink passage unit can be reduced. Components such as actuator units, an ink supply unit, and the like will be attached to the manufactured ink passage unit to complete an inkjet head.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: September 15, 2009
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Tatsuo Terakura
  • Patent number: 7589952
    Abstract: A multilayer electronic device includes a laminate and an external electrode that is formed on an end surface of the laminate after a plurality of conductive particles having a particle diameter of about 1 ?m or more is adhered to the end surface of the laminate, for example, by a sandblast method or a brush polishing method. The external electrode is defined by a plating film that is formed by electroplating or electroless plating.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: September 15, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Akihiro Motoki, Kenichi Kawasaki, Makoto Ogawa, Shigeyuki Kuroda, Tatsuo Kunishi
  • Patent number: 7589951
    Abstract: A laminated body is prepared, in which at an end surface at which internal electrodes are exposed, the internal electrodes disposed adjacently are electrically isolated from each other, and a distance between the internal electrodes disposed adjacently is about 20 ?m or less when measured along the thickness direction of an insulator layer, and a withdrawn-depth of the internal electrodes is about 1 ?m or less when measured from the end surface. In a step of electroless plating, plating deposits formed at the end portions of the plurality of internal electrodes are increased in size so as to be connected to each other.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: September 15, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tatsuo Kunishi, Makoto Ogawa, Akihiro Motoki
  • Patent number: 7584539
    Abstract: A method of manufacturing an inkjet printer component and an inkjet printer component electropolishing device are provided. The method includes positioning an electrode in a fluid passageway of an inkjet printer component, the electrode including a conductive face and a nonconductive face; polishing a side of the fluid passageway by: biasing the nonconductive face of the electrode toward a side of the fluid passageway such that the conductive face of the electrode does not contact any portion of the fluid passageway; providing an electrolytic fluid to the fluid passageway of the inkjet printer component; and applying a voltage between the electrode and the inkjet printer component.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: September 8, 2009
    Assignee: Eastman Kodak Company
    Inventors: James E. Harrison, Francis T. Galbraith, Kevin P. Egan, Bruce A. Bowling, Richard W. Sexton
  • Publication number: 20090219667
    Abstract: A capacitor element for a power capacitor. The capacitor element includes a plurality of series-connected cylindrical sub-elements. Each sub-element includes at least two strips of dielectric material wound in a number of turns. A layer of electrically conductive material is disposed between the turns of the winding. The sub-elements are disposed one outside the other as seen in a direction transversely to the plane of the strip. A strip in an outermost sub-element is longer than the strip in each inwardly lying sub-element. A power capacitor includes a plurality of the capacitor elements, and a capacitor battery includes a plurality of the power capacitors. A method of manufacturing the inventive capacitor element and the use of the inventive power capacitor.
    Type: Application
    Filed: November 2, 2006
    Publication date: September 3, 2009
    Inventor: Esbjorn Eriksson
  • Patent number: 7583493
    Abstract: A monolithic semiconductor ceramic capacitor includes semiconductor ceramic layers made of a semiconductor ceramic having a Sr site and a Ti site. The semiconductor ceramic satisfies the inequality 1.000<m?1.020, wherein m represents the molar ratio of the Sr site to the Ti site. The semiconductor ceramic contains crystal grains and has grain boundary layers. The crystal grains contain a donor element such as La or Sm in the form of a solid solution. The grain boundary layers contain an acceptor element such as Mn, Co, Ni or Cr. The amount of the acceptor element therein is equal to or less than 0.5 mol (preferably 0.3 to 0.5 mol) per 100 mol of Ti. The crystal grains have an average size of 1.0 ?m or less (preferably 0.5 to 0.8 ?m). Therefore, the monolithic semiconductor ceramic capacitor has good electrical properties, good resistivity, good dielectric strength, and high reliability and is suitable for thin or compact apparatuses.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: September 1, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinsuke Tani, Mitsutoshi Kawamoto
  • Patent number: 7581297
    Abstract: A piezoelectric vibrator has an airtight terminal comprised of a lead terminal and a piezoelectric member. The lead terminal has an inner lead portion and an outer lead portion. The piezoelectric member has an exciting electrode and a mount electrode disposed on a surface of the piezoelectric member. A plasma arc electrode is connected to a power supply for generating a plasma arc discharge. To bond together the inner lead portion of the lead terminal to the mount electrode of the piezoelectric member, the outer lead portion is connected to an output terminal of the power supply and the plasma arc electrode is positioned at a vicinity of a bonding portion for bonding together the inner lead portion and the mount electrode. A voltage is applied between the inner lead portion and the plasma arc electrode to generate a plasma arc discharge.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: September 1, 2009
    Assignee: Seiko Instruments Inc.
    Inventors: Masayuki Sato, Seigo Fukuchi, Atsushi Tomisaki
  • Patent number: 7581295
    Abstract: An array of piezoelectric elements is easily manufactured by making insulating portions at side surfaces smaller. The piezoelectric element includes: a multilayered structure in which piezoelectric material layers and internal electrode layers are alternately stacked; first insulating films formed by using an AD method, for covering a first group of internal electrode layers at a first surface of the multilayered structure; second insulating films formed by using the AD method, for covering a second group of internal electrode layers at a second surface of the multilayered structure; a first external electrode connected to the second group of internal electrode layers and insulated from the first group of internal electrode layers at the first surface; and a second external electrode connected to the first group of internal electrode layers and insulated from the second group of internal electrode layers at the second surface.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: September 1, 2009
    Assignee: FUJIFILM Corporation
    Inventor: Tetsu Miyoshi
  • Patent number: 7581311
    Abstract: A method for manufacturing a dielectric element including the steps of: preparing a lower electrode; forming a dielectric on the lower electrode to fabricate a first laminated structure; annealing the first laminated structure; forming an upper electrode on a dielectric film to fabricate a second laminated structure; and annealing the second laminated structure under a reduced pressure atmosphere at a temperature of 150° C. or higher.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: September 1, 2009
    Assignee: TDK Corporation
    Inventors: Tomohiko Katoh, Kenji Horino
  • Patent number: 7578858
    Abstract: A method of making capacitor structure includes arranging first-layer conducting strips on a first layer of an integrated circuit chip, and arranging second-layer conducting strips on a second layer of the integrated circuit chip. The first-layer conducting strips and the second-layer conducting strips can be arranged as respective piecewise spirals. The second-layer conducting strips are arranged overlying and electrically separated from the first-layer conducting strips, and the method further includes electrically connecting the first-layer conducting strips with the second-layer conducting strips.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: August 25, 2009
    Assignee: Marvell International Ltd.
    Inventor: Pantas Sutardja
  • Publication number: 20090207554
    Abstract: A ceramic electronic component has a chip element body having a conductor arranged inside, external electrodes, and a discrimination layer. The chip element body has first and second end faces facing each other, first and second side faces being perpendicular to the first and second end faces and facing each other, and third and fourth side faces being perpendicular to the first and second end faces and to the first and second side faces and facing each other. The external electrodes are formed on the first and second end faces, respectively, of the chip element body. The discrimination layer is provided on at least one side face out of the first side face and the second side face in the chip element body. The chip element body is comprised of a first ceramic. The discrimination layer is comprised of a second ceramic different from the first ceramic and has a color different from that of the third and fourth side faces.
    Type: Application
    Filed: January 8, 2009
    Publication date: August 20, 2009
    Applicant: TDK CORPORATION
    Inventors: Toshihiro IGUCHI, Akitoshi YOSHII, Akira GOSHIMA, Kazuyuki HASEBE
  • Publication number: 20090207550
    Abstract: An electrical component that is surface mountable includes a base body having first inner electrodes and second inner electrodes. A first outer electrode extends along the base body in a first direction, and a through connection extends along the base body in a second direction that is different from the first direction. The first inner electrodes are electrically connected to the first outer electrode. The second inner electrodes are electrically interconnected via the through connection.
    Type: Application
    Filed: May 11, 2006
    Publication date: August 20, 2009
    Applicant: EPCOS AG
    Inventors: Thomas Feichtinger, Markus Ortner
  • Publication number: 20090207555
    Abstract: An antiferroelectric ceramic material that can be formed into a multilayer capacitor is disclosed. The antiferroelectric ceramic material is selected from the Pb(Sn, Zr, Ti)O3 (PSnZT) composition family.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 20, 2009
    Applicant: TRS TECHNOLOGIES
    Inventors: Wesley S. HACKENBERGER, Seongtae KWON
  • Patent number: 7574787
    Abstract: A method of producing at least one piezoelectric element includes depositing a piezoelectric ceramic material onto a surface of a first substrate to form at least one piezoelectric element structure. Then an electrode is deposited on a surface of the at least one piezoelectric element structure. Next, the at least one piezoelectric element structure is bonded to a second substrate, the second substrate being conductive or having a conductive layer. The first substrate is then removed from the at least one piezoelectric element structure and a second side electrode is deposited on a second surface of the at least one piezoelectric element structure. A poling operation is performed to provide the at least one piezoelectric element structure with piezoelectric characteristics.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: August 18, 2009
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Baomin Xu, Steven A. Buhler, Michael C. Welsberg, William S. Wong, Scott E. Solberg, Karl A. Littau, John S. Fitch, Scott A. Elrod
  • Publication number: 20090201628
    Abstract: In a multilayer ceramic capacitor including: a laminated body layer formed by alternately laminating dielectric layers made of ceramic particles and internal electrodes; and a pair of external electrodes provided on at least both end surfaces of the laminated body layer and alternately connected to the internal electrodes electrically, the number of boundaries between ceramic particles per unit length of the dielectric layer in the lamination direction is larger than that in the direction connecting the pair of external electrodes. Thus increasing the number of ceramic grain boundaries between internal electrodes improves the insulation characteristic. Particularly, even if the number of ceramic particles thicknesswise decreases due to lamellation, increasing the number of grain boundaries suppresses deterioration of the insulation characteristic.
    Type: Application
    Filed: March 14, 2008
    Publication date: August 13, 2009
    Inventors: Hiroshi Kagata, Satoshi Tomioka, Koichi Shigeno
  • Publication number: 20090201623
    Abstract: The present invention provides a capacitive RF-MEMS device comprising a vertically integrated decoupling capacitor (14). The decoupling capacitor (14) therefore does not take extra area. Furthermore, the RF-MEMS according to the invention needs less interconnects, which also saves space and which reduces the series inductance/resistance in the RF path.
    Type: Application
    Filed: April 21, 2006
    Publication date: August 13, 2009
    Applicant: NXP B.V.
    Inventor: Peter Gerard Steeneken
  • Publication number: 20090193637
    Abstract: The present invention relates to the field of solid state capacitors, and in particular to capacitors that have an anode body formed of porous valve action material, such as tantalum, niobium or niobium monoxide. According to one aspect of the present invention, there is provided a method of forming capacitor anode bodies from valve action material comprising the steps of: providing a capacitor grade powder of the valve action material, charging the powder into moulding means, compacting the powder in the moulding means so as to shape the powder into an anode body shape, stabilising the body shape, for example by sintering of the material to form an inter-connected porous body, characterised in that the moulding process involves the use of lubrication means which is adapted to apply lubricant locally to lubricate the interface between an outside surface of the anode body and a moulding surface of the moulding means.
    Type: Application
    Filed: September 1, 2006
    Publication date: August 6, 2009
    Inventors: Colin McCracken, Nigel Patrick Grant
  • Publication number: 20090195963
    Abstract: A capacitor includes a pair of electrically conductive layers; a plurality of substantially or nearly tubular dielectric materials disposed between the pair of electrically conductive layers formed of anodic oxide of metal; first electrodes which are filled in hollow portions of the dielectric materials and connected to one of the electrically conductive layers; and a second electrode that is filled in voids between the respective dielectric materials and connected to the other electrically conductive layer.
    Type: Application
    Filed: June 13, 2008
    Publication date: August 6, 2009
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Hidetoshi MASUDA, Masaru KUROSAWA, Kotaro MIZUNO
  • Patent number: 7569080
    Abstract: A powder compaction process using opposed rib and channel punches which are interleaved and a production method are used to produce capacitor elements having a uniform compaction density and which are free of surface imperfections.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: August 4, 2009
    Assignee: Kemet Electonics Corporation
    Inventor: Jeffrey P. Poltorak
  • Patent number: 7565725
    Abstract: A method for forming a variable capacitor including a conductive strip covering the inside of a cavity, and a flexible conductive membrane placed above the cavity, the cavity being formed according to the steps of: forming a recess in the substrate; placing a malleable material in the recess; having a stamp bear against the substrate at the level of the recess to give the upper part of the malleable material a desired shape; hardening the malleable material; and removing the stamp.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: July 28, 2009
    Assignees: STMicroeectronics S.A., Commissariat a l'energie Atomique
    Inventors: Guillaume Bouche, Fabrice Casset, Pascal Ancey
  • Patent number: 7562451
    Abstract: A method of manufacturing an actuator device configured to prevent separation of a vibration plate and to enhance durability and reliability, and a liquid-jet apparatus are provided. The method includes the steps of forming a vibration plate on one surface of a substrate, and forming a piezoelectric element having a lower electrode, a piezoelectric layer, and an upper electrode on the vibration plate. The step of forming a vibration plate at least includes an insulation film forming step of forming an insulation film made of zirconium oxide by forming a zirconium layer on the one surface side of the substrate in accordance with a sputtering method and subjecting the zirconium layer to thermal oxidation by inserting the substrate formed with the zirconium layer to a thermal oxidation furnace heated to a temperature greater than or equal to 700° C. at a speed greater than or equal to 200 mm/min.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: July 21, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Maki Ito, Masami Murai, Xin-Shan Li, Toshinao Shinbo
  • Patent number: 7564675
    Abstract: A face-centered cubic structure capacitor is provided, which includes a first metal layer, a second metal layer, and a connection layer. The first metal layer comprises a plurality of first metal wires, a plurality of second metal wires, and a plurality of first metal blocks. The first and second metal wires are intercrossed with each other to form a grid structure, and each of the first metal blocks is disposed in each grid of the grid structure. The second metal layer comprises a plurality of third metal wires, a plurality of fourth metal wires, and a plurality of second metal blocks. The third and fourth metal wires are intercrossed with each other to form a grid structure, and each of the second metal blocks is disposed in each grid of the grid structure. The connection layer comprises a plurality of third metal blocks and a plurality of fourth metal blocks.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: July 21, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: I-Hsun Chen, Szu-Kang Hsien
  • Patent number: 7564116
    Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: July 21, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Yong Ahn, Cheol Seong Hwang, Sung Kun Kim, Chang Sup Ryu, Suk-Hyeon Cho, Ho Sik Jeon
  • Publication number: 20090180239
    Abstract: A metal capacitor in which an electric conductivity is significantly improved is provided. The metal capacitor includes: a metal member 11 including a plurality of grooves 11a; a metal oxide film 12 being formed on the metal member 11; a sealing electrode member 13 being formed on the metal oxide film 12 to fill in the plurality of grooves 11a; and an insulating layer 14 being formed on the sealing electrode member 13 and the metal oxide film 12 to insulate the metal member 12 and the sealing electrode member 13.
    Type: Application
    Filed: June 10, 2008
    Publication date: July 16, 2009
    Inventor: Young Joo Oh
  • Patent number: 7561406
    Abstract: A thin film capacitor with high capacity and low leak current is provided. The thin film capacitor includes a nickel substrate with nickel (Ni) purity of 99.99 weight percent or above, and a dielectric layer and an electrode layer disposed in this order on the nickel substrate. The thin film capacitor is typically manufactured as follows. A precursor dielectric layer is formed on a nickel substrate with nickel purity of 99.99 weight percent or above, and is subjected to annealing to form a dielectric layer. The diffusion of impurities from the nickel substrate to the precursor dielectric layer during annealing is suppressed.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: July 14, 2009
    Assignee: TDK Corporation
    Inventors: Hitoshi Saita, Yuko Saya, Kiyoshi Uchida, Kenji Horino
  • Publication number: 20090159322
    Abstract: A through hole capacitor at least including a substrate, an anode layer, a dielectric layer, a first cathode layer, and a second cathode layer is provided. The substrate has a plurality of through holes. The anode layer is disposed on the inner surface of at least one through hole, and the surface of the anode layer is a porous structure. The dielectric layer is disposed on the porous structure of the anode layer. The first cathode layer covers a surface of the dielectric layer. The second cathode layer covers a surface of the first cathode layer, and the conductivity of the second cathode layer is greater than that of the first cathode layer. The through hole capacitor can be used for impedance control, as the cathode layers of the through hole are used for signal transmission.
    Type: Application
    Filed: March 11, 2008
    Publication date: June 25, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Bang-Hao Wu, Li-Duan Tsai, Min-Lin Lee, Cheng-Liang Cheng
  • Patent number: 7551422
    Abstract: A multilayer capacitor having a dielectric body, an internal layer portion, external layer portions a first terminal electrode connected with a first internal conductor layer and a first external conductor layer, formed at least on a first side face of side faces of the dielectric body, and a second terminal electrode connected with a second internal conductor layer and a second external conductor layer, formed on a second side face opposed to the first side face of the dielectric body. The dielectric layer positioned at the external layer portions includes a plurality of pin hole conducting portions connecting a pair of first external conductor layers or a pair of second external conductor layers to each other adjacent to the dielectric layer, in an area of overlapping a pair of the first external conductor layers or a pair of the second external conductor layers adjacent to the dielectric layer.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: June 23, 2009
    Assignee: TDK Corporation
    Inventor: Masaaki Togashi
  • Publication number: 20090154056
    Abstract: A film capacitor includes metallization that is sectionalized, patterned and configured to provide interconnections on only one face of a rolled or stacked film capacitor.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Eladio Clemente Delgado, Michael Andrew de Rooij, Patricia Chapman Irwin, Yang Cao
  • Publication number: 20090154057
    Abstract: A film capacitor including a pair of electrodes having multiple pores is provided. The film capacitor includes a polymer film deposited upon each of the pair of electrodes to form a dielectric layer.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 18, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventor: Daniel Qi Tan
  • Publication number: 20090154068
    Abstract: Provided is a solid electrolytic capacitor including a capacitor element with a positive polarity; an anode wire of which one side is inserted into the capacitor element and the other side projects outward from the capacitor element; a cathode extraction layer formed on the capacitor element; a plurality of conductive bumps formed on the cathode extraction layer; an anode lead frame fixed to the side of the capacitor element, where the anode wire projects outward, and having an insertion portion into which the projecting end of the anode wire is inserted; a molding portion formed to surround the capacitor element and exposing the projecting end of the anode wire, the outer surface of the anode lead frame, and ends of the conductive bumps; an anode lead terminal provided on the molding portion so as to be electrically connected to the exposed end of the anode wire and the anode lead frame; and a cathode lead terminal provided on the molding portion so as to be electrically connected to the exposed ends of the
    Type: Application
    Filed: January 8, 2008
    Publication date: June 18, 2009
    Inventors: Hee Sung Choi, Seoung Jae Lee, Yeoung Jin Lee, Sung Han Won, Ha Yong Jung, Hyun Ho Shin, Jung Tae Park, Jae Youn Jeong
  • Patent number: 7548408
    Abstract: A method for manufacturing a capacitor includes the steps of: forming a conductive layer above a base substrate; forming a dielectric layer above the conductive layer; forming a lanthanum nickelate layer above the dielectric layer; and patterning at least the dielectric layer by using at least the lanthanum nickelate layer as a mask.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 16, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Masao Nakayama
  • Patent number: 7547370
    Abstract: A method for manufacturing a multilayer ceramic electronic element includes the steps of forming ceramic green sheets having superior surface smoothness and small variations in thickness at a high speed, in which defects such as pinholes are prevented from occurring, and providing internal electrodes and step-smoothing ceramic paste on the ceramic green sheets with high accuracy. The method includes the steps of applying ceramic slurry to a base film by a die coater followed by drying performed in a drying furnace for forming the ceramic green sheets, and performing gravure printing of conductive paste and ceramic paste onto the ceramic green sheets by using a first and a second gravure printing apparatus, respectively. Accordingly, the internal electrodes are formed, and the step-smoothing ceramic paste is provided in regions other than those in which the internal electrodes are formed.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: June 16, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shingo Okuyama, Hiroyoshi Takashima, Akira Hashimoto, Shinichi Kokawa
  • Publication number: 20090141419
    Abstract: Film capacitor assembly has a plurality of film capacitive layers for storing an electric charge. The plurality of film capacitive layers have a first metal contact and a second metal contact. A heat sink removes heat from the plurality of film capacitive layers. The heat sink is in thermal conductive communication with at least one of the first metal contact and the second metal contact. A dielectric material is configured to prevent a transmission of electric current through the heat sink from the plurality of film capacitor capacitive layers.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 4, 2009
    Inventors: Debabrata Pal, John Huss
  • Publication number: 20090141420
    Abstract: Packaged capacitive devices are described having electrical interconnects of electrodes which possess efficient electrical contact between current collectors, electrical isolation of electrodes, and/or electrochemical stability, while minimizing the mechanical stress and strain applied to the electrodes, in part, due to the use of a compliant layer. The packaged capacitive devices are adaptable to a wide range of electrode diameters and electrode stack lengths.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 4, 2009
    Applicant: Corning Incorporated
    Inventors: Roy Joseph Bourcier, Todd Michael Roswech
  • Publication number: 20090135545
    Abstract: The invention relates to a capacitor having a porous electrically conductive substrate on whose inner and outer surfaces a first layer of a dielectric and an electrically conductive second layer are applied. The invention also relates to a method for the production of such capacitors and to their use in electrical and electronic circuits.
    Type: Application
    Filed: October 20, 2005
    Publication date: May 28, 2009
    Applicant: BASF Aktiengesellschaft
    Inventors: Florian Thomas, Patrick Deck, Klaus Kuhling, Hans-Josef Sterzel, Daniel Fischer
  • Publication number: 20090126175
    Abstract: An example of a multi-layer ceramic capacitor may include multiple dielectric sheets. In a cross section of each dielectric sheet, there may be printed a first external electrode, a first internal electrode which includes one or more protrusions and which is joined to the first external electrode by way of an interposed dielectric portion, a second external electrode joined as a single body to the first internal electrode, and a second internal electrode joined to the first internal electrode with a dielectric portion positioned in a space defined by the protrusions. The dielectric sheets may be stacked alternately to be symmetrical, such that the first external electrodes and the second external electrodes are electrically connected and the protrusions of the first internal electrodes and the second internal electrodes are electrically connected. In this way, the areas of the internal electrodes can be maximized.
    Type: Application
    Filed: January 26, 2009
    Publication date: May 21, 2009
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Kwi-Jong LEE