Abstract: Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.

Abstract: The integrated circuit comprises an output circuit feeding an external system connected to an output terminal of the integrated circuit and a detection circuit of the characteristic of the external system. The detection circuit includes a comparator for comparing the voltage on the output terminal in response to a signal delivered by the output circuit with a voltage of reference, memorizing means memorizing at different times the result of the comparison and a logic circuit connected to the memorizing means which delivers at its outputs combinations of logic states depending upon the characteristics of the external systems, the combinations of logic states being utilized by the integrated circuit to control the external systems in accordance with their particular characteristics.

Abstract: A low-power consumption, high-speed electronic switching system has a pair of complementary switching means connected between opposite polarity terminals of the voltage source and an output terminal. The pair of switches provides a variable impedance for applying one or the other of the polarities and said output terminal. To speed an appearance of that polarity, an inverter is coupled between an input and an output terminal via a differentiating capacitor. The differentiated inverter output speeds the appearance of the switched output signal during the interval before the complementary input becomes effective thereat.

Abstract: A buffer having a first and second complementary IGFET input inverter connected in series and an output including a bipolar emitter follower with its base connected to the output of the first inverter, a second bipolar transistor connected in series with the emitter follower with its base connected to the output of the second inverter and an IGFET connected between the junction of the bipolar transistors and a voltage supply terminal and with its gate connected to the input of the first inverter. The output IGFET pulls the buffer output up to the supply voltage when the emitter of the emitter follower is at the supply voltage minus V.sub.BE.

Abstract: A latch circuit suited for a high-density semiconductor integrated circuit is disclosed, which comprises a first inverter circuit, a gating means for transferring an input signal to an input terminal of the first inverter circuit, a second inverter circuit having an input terminal coupled to the output of the first inverter circuit, and a transferring means for applying the output of the second inverter circuit to the input terminal of the first inverter circuit, the transferring means having substantially equal impedance characteristics in both directions.

Abstract: There is disclosed an optoelectronic coupling device for transmitting digital signals from an input to an output, which input and output are electrically isolated from each other. An input stage includes an input for receiving digital input signals from an incoming signal line and an output. The input stage is connected to an optoelectronic coupling circuit comprising luminescent diodes and phototransistors arranged adjacent to respective ones of the luminescent diodes. Either the collectors or the emitters of both phototransistors are commonly connected to a first voltage source. The other leads of the phototransistors form outputs of the optoelectronic coupling circuit. An output stage, connected to these outputs, includes an operational amplifier having an output, a non-inverting input and an inverting input. Each of the non-inverting and inverting inputs are connected to one of the outputs of the optoelectronic coupling circuit.

Abstract: A circuit arrangement is described for the transmission of a digital data signal. The circuit arrangement is inserted as an asynchronous interface into the transmission path between digital data handling systems with differing clock frequencies f.sub.1 and f.sub.2. The circuit arrangement comprises a register 1 of D flip-flops for buffering the input data D.sub.1. The clocking of the register 1 is performed with a special clock signal f.sub.Inter, which is derived from a series circuit of edge controlled R-S and J-K flip-flops 3 and 4 respectively. The result is output data D.sub.2 synchronous with the frequency f.sub.2.

Abstract: A bipolar drive circuit for driving a load, such as a printer, is compatible with complementary metal oxide semiconductor (CMOS) circuitry and may be driven by a non-inverting hex buffer. Connected to the input of the drive circuit is a clamp circuit for providing a shunt path to ground for leakage currents during floating or open circuit conditions at the input. The output of the drive circuit includes a plurality of transistors connected in a complementary Darlington configuration to provide the necessary current gain to drive a conventional output, medium power, transistor. A diode is connected between the input of the drive circuit and ground for protection.

Abstract: An address buffer is disclosed in MOS technology with an address memory circuit exhibiting an address input driven via a transfer signal and having two complementary address outputs and two complementary signal outputs of high signal level. An isolating amplifier is provided with a following-connected output stage. The isolating amplifier is driven via a control clock pulse and supplies complementary control signals. It also has two parallel paths each consisting of the driven segments of two transistors. These parallel paths are connected to the drive clock pulse at a first common node and are connected to a base voltage source at a second common node. The first transistor of each parallel path is driven via a respective high signal level signal output of the address memory circuit and the second transistor of each parallel path is driven via a respective address output of the address memory circuit which is inverse to the high level signal output.

Abstract: An interface device for selectively accessing two internal signal paths of an integrated circuit through a single external connection pin. Each of the signal paths is provided with a bias voltage sensitive conduction device that permits conduction at a different externally provided bias voltage that inhibits current flow in the other conduction device. The different bias voltages are provided to the external connection pin through an external load resistor.

Abstract: A charge is placed on the floating substrate of an insulated-gate field-effect transistor IGFET by applying, to the source of the IGFET, a signal making a first transition between first (V.sub.1) and second (V.sub.2) voltages and a second transition between the second voltage and a third voltage (V.sub.3) which is intermediate V.sub.1 and V.sub.2. The first transition is of a polarity and magnitude to forward bias the source-to-substrate junction of the IGFET and establishes a first level (L.sub.1) at the substrate region close to said second voltage. The second transition causes the source potential to go to V.sub.3 but the source-to-substrate junction is reverse biased and the substrate potential remains at a level (L.sub.2) which is intermediate L.sub.1 and V.sub.3. Consequently, the source to substrate junction remains isolated for values of signals applied to the source in the range between V.sub.1 and L.sub.2.

Abstract: A large scale semiconductor integrated circuit device comprising plural transistors and resistors formed in one semiconductor substrate, and many emitter-coupled circuits formed by connecting the transistors and resistors with a double metallic layer on the substrate surface.Moreover, between the groups and respective input/output terminals, large scale transistors are provided for outputting the emitter-follower circuits. These groups containing the emitter coupled circuits are connected to the input/output terminals by the double metallic wiring layer.

Abstract: A transistor logic circuit wherein a selector is coupled to a pullup resistor and output sense amplifier through an isolation transistor. The selector includes a plurality of transistors having emitter electrodes coupled to a plurality of input terminals, base electrodes coupled to control signals and collector electrodes connected to a common output terminal. The isolation transistor has its base electrode coupled to a reference voltage and its emitter and collector electrodes serially coupled between the output terminal and the pullup resistor and output sense amplifier. Control signals fed to the base electrodes of the plurality of transistors couples a selected one of the input terminals to the output terminal. The logic state of a signal at such selected input terminal is sensed by the sense amplifier. The isolation transistor isolates the large capacitance produced as a result of connecting the collector electrodes together from the switching action of the sense amplifier.

Abstract: An improved input system for isolating resolver or synchro outputs from inputs to demodulators or analog-to-digital converters uses current transformers rather than voltage transformers. The resistances of resistors connected in series with the primary windings of the isolation transformers are adjusted to standardize the input currents of the transformers.

Abstract: An input terminal of an interface circuit is connected to a first logic circuit which produces a first logic signal. The interface circuit compares the first logic signal with a reference voltage whose level is set between a high level and a low level of the first logic signal. The interface circuit converts levels of the signal compared. An output terminal of the interface circuit is connected to a second logic circuit whose signal levels are different from levels of the first logic signal and which is driven by the output signal compared and amplified.

Abstract: Two independent power supplies for an I.sup.2 L or ISL logic array can be timed to turn on at different times by a simple RC network connected externally of the logic array. The differential timing is utilized to condition or set a bistable device in a predetermined initial desired state, without requiring an additional device terminal pin for that purpose.

Abstract: A current isolation circuit converts a pulse width modulated input signal to an isolated DC output current whose magnitude is a function of the duty cycle of the input signal. The isolation circuit includes an optical isolator which receives the pulse width modulated input signal and has an output which changes between a conductive and a non-conductive state in response to the input signal. A voltage regulating diode, such as a Zener diode, is connected to the output of the optical isolator and to an isolated power supply so that the voltage across the Zener diode varies between two known voltage values in response to the switching of the optical isolator output between conductive and non-conductive states. A signal derived from the Zener diode is filtered to produce a reference signal with a magnitude which is a function of the duty cycle of the input signal.

Abstract: A TTL to CMOS input buffer integrated circuit having an input terminal for connection to an output terminal of a TTL device is disclosed.

Abstract: In a Static Induction Transistor Logic (or an Integrated Injection Logic) semiconductor device having a lateral PNP transistor used as an injector and a longitudinal field effect transistor (or a longitudinal NPN transistor) used as a driving transistor, a collector of a transistor for a level-converter which converts a signal level from an upper layer or first logic level to a lower layer or second logic level is connected to a gate (or a base) of a driving transistor placed in the lower layer through a current limiting element integrated on the same chip to effectively use an injection current in a signal-level converting circuit used in a Static Induction Transistor Logic or in an Integrated Injection Logic which is constructed by using a laminated circuit construction.

Abstract: A high input impedance, low output impedance, temperature-stable tuning voltage interface circuit with substantial ripple rejection and negligible DC offset. The circuit comprises two transistors of opposite conductivity types, the first being coupled through a resistor to a supply voltage and through a temperature-stabilizing, DC-offsetting diode to the output of the second transistor. The rejection of the ripple voltage superimposed on the supply voltage is determined by the ratio of the value of the resistor to the effective resistance of the diode.

Abstract: The invention relates to an I.sup.2 L circuit in which the transistors provided with current injectors are distributed between a number of groups which are connected in series as stages between the supply connections. For the logic signal connections between a higher and a lower stage, a current source is used which is controlled from the higher stage and which is connected to the base of a controlled transistor in the lower stage. According to the invention, the switching time of the controlled transistor is reduced by providing a conductive connection which comprises the collector-emitter path of an auxiliary transistor between the base of the controlled transistor and a suitable point of a reference potential.

Abstract: Disclosed is an integrated buffer circuit having a selectable stabilized trip voltage. The circuit includes an input stage and a reference stage. Each of these stages includes an MOS field effect transistor, a substantially constant resistance device coupling the drain of the input transistor to a bias source, and a device having a resistance that is variable in response to control signals coupling the source of the input transistor to another bias source. The reference stage is biased in the linear region at the selectable trip voltage. A signal generated at the drain of the transistor in the reference stage is connected to all of the variable resistance devices as the control signal. This signal varies the variable resistance in such a way as to compensate for threshold voltage variations in the transistor of the input stage and thus stabilize the selected trip voltage of the input stage.

Abstract: A depletion type MISFET is connected between a power voltage supply line of a transistor logic circuit block and a power source voltage terminal. The gate electrode of the depletion type MISFET is connected to a reference voltage. The transistor logic circuit block has a driving MISFET and a load connected in series between the power voltage supply line and the reference voltage. The load of the transistor logic circuit is similarly constituted by a depletion type MISFET, while the driving MISFET is of enhancement type. The driving MISFET and the load MISFET in the transistor logic circuit block are built-in in a monolithic semiconductor integrated circuit, together with the MISFET for the power voltage supply to the transistor logic circuit.

Abstract: An inverter circuit operating at a high speed and with low power consumption is disclosed, which comprises a first bipolar transistor having a collector coupled to the output of the circuit, a second bipolar transistor having a collector coupled to the base of the first transistor and means responsive to at least one input signal to produce a first signal for driving the first transistor and a second signal complementary to the first signal for driving the second transistor substantially at the same time.

Abstract: A CMOS semiconductor memory device in which a memory cell array and peripheral circuits are formed on the same semiconductor substrate. Wells of the peripheral circuits with MOS transistors of one channel type formed therein are supplied with a PN junction reverse bias potential higher than that for wells of the memory cell array during the memory operation, while the potential at the peripheral circuit wells is made equal to the potential at the wells of the memory cell array when the memory is not operating. High-speed operation of the memory device may be achieved because the junction capacitance of the MOS transistors formed in the peripheral circuit wells is reduced when the memory is operating.

Abstract: An output circuit is provided in which a first IG-FET of a first conductivity type is connected between a first potential supply terminal and an output terminal and having its substrate controlled by a third potential higher than the first potential of the first potential supply terminal and a second IG-FET of a second conductivity type connected between a second potential supply terminal having a second potential lower than the first potential and the output terminal and having its substrate electrode supplied with the second potential. A control circuit is further provided which receives an input signal and control signal and controls the output circuit to permit the latter to produce one of the first potential, second potential and high impedance state. The output circuit and control circuit are combined to provide a converter circuit for converting the level of a CML (complementary MOS Transistor Logic) to a TTL (Transistor-Transistor Logic).

Abstract: A gating means, biased to pass current only during signal transitions, transfers binary signals from an input signal source to a latch circuit when the signal source and the latch are operated at similar voltages. Following data transfer, the operating voltage across the latch is increased. The voltage levels of the latch output signals are correspondingly increased but the state to which the latch was set is maintained and there is no steady state current conduction through the gating means.

Abstract: A low power high sensitivity detector having two pairs of MOS cross coupled transistors, voltage equalization circuitry, and a single input, with no external reference, forms the basic configuration of a detector-level shifter circuit which is compatible with today's single chip large capacity memories. The lengths of the channels of one of the pairs of cross coupled transistors are designed to be longer than the other pair. This provides a built-in imbalance which provides good tolerance to transistor parameter variation due to semiconductor processing variations.

Abstract: A high-performance address buffer for use with a dynamic random-access memory is transistor-transistor logic-input compatible, utilizing a time constant on which activation of one output is dependent.

Abstract: An FET substrate voltage generator circuit is disclosed for converting a single power supply and ground potential to a negative potential having an absolute value whose magnitude is greater than the power supply potential and applying that potential to the substrate of an integrated circuit upon which it is formed. The circuit dissipates less power per unit of current supplied by the circuit and occupies less space than do prior art circuits. The circuit applies the principle of voltage doubling to a first capacitor to achieve the desired voltage magnitude across a second capacitor and then applies the principle of a.c. coupling to that second capacitor connected through an impedance to the first capacitor, to achieve the desired polarity inversion for the substrate voltage to be generated. This circuit provides the current generating capacity necessary to drive the substrate to a negative voltage and sink the required current so as to maintain the substrate at an adequate negative bias.

Abstract: In a system wherein a single input signal is transmitted via a plurality of output signal channels for various signal processing and control functions, optical isolating circuits in combination with current limiting resistors provide operational isolation among the respective output signal transmitting channels such that a component failure in one channel will not adversely affect the operation of the remaining channels.

Abstract: An input/output interface for a digital controller including an optical isolator coupling an input portion which formats an external signal to make it compatible with the optical isolator and an output portion comprising an RC network connected to a threshold detector with hysteresis to provide a filtered output logic signal in addition to an accompanying audio or visual signal. The interface, with slight modifications can be used with either DC or AC external signals.

Abstract: An interface driver circuit, for use in a programmable energy load controller system, comprises a pair of optically-coupled input sections, respectively receiving data and a special signal of digital nature and a first voltage polarity. A buffer amplifier section is coupled to the data input circuit for driving a twisted-wire transmission line, coupled to the paralleled inputs of a plurality of receivers, with logic signals alternating essentially between ground potential and the first voltage at the first polarity; a second amplifier section is enabled by the special signal input section and impresses a voltage of the remaining polarity across the interface driver circuit output when commanded at the special signal input, regardless of the state of the data signal at the first input.

Abstract: In an address buffer circuit in a semiconductor memory including a flip-flop formed of MISFETs and an output circuit consisting of two drivers each formed of MISFETs, and producing a binary address signal, the flip-flop is supplied with a constant operating voltage and triggered by a pulse signal of a shorter pulse width than that of a chip enable signal and the MISFETs of the driver on the ground side have the gates cross-coupled to the outputs of the respective drivers so that at least one grounding MISFET in each driver is turned on in the outputting period to prevent the floating of the output level.

Abstract: This circuitry translates a relatively large voltage bi-level logical signal to an inphase relatively low voltage bi-level signal for bistatic current-switching logical circuitry. A transistor is connected in the common base circuit arrangement for a first order of input-output circuit isolation. Substantially complete isolation is afforded by a reference tracking circuit which is arranged to track exactly for temperature, base-to-emitter voltage and process variations. This circuit provides a potential at the base of the transistor which is the sum of the emitter-to-base voltage drop and one half of the applied energizing potential. The proper base potential is effected by simple adjustment of the ratio of the value of the input resistor to the value of the load resistor. Many such circuits may be operated on a single semiconductor chip.

Abstract: A CMOS circuit having high voltage capability is provided. At least one P channel transistor is coupled between a first voltage node and an output of the circuit. At least two N channel transistors are coupled in series between the output of the circuit and a second voltage node. The at least two N channel transistors each have a separate tub which is connected to the source of each respective N channel transistor. This arrangement of the N channel transistors provides at least one tub which is isolated from the voltage nodes when the output of the circuit is at a potential substantially equal to a voltage present at the first voltage node.

Abstract: A circuit is disclosed for impedance matching an electrical signal-generating transducer to an electrical signal-processing amplifier while substantially retaining both the original signal-to-noise power ratio and the original signal amplitude at the input to the amplifier. A load resistance of a value substantially equal to twice the characteristic resistance of the transducer is coupled across the amplifier input, while a negative low-noise resistance approximately equal in magnitude to the source resistance is coupled in series with the load resistance. A transmission line having a characteristic impedance approximately equal to the transducer resistance is coupled between the transducer output and the series-coupled load resistance and negative resistance.

Abstract: An input buffer gate for integrated injection logic (I.sup.2 L) circuits, including a multiple-collector transistor wherein a first collector is electrically common with the base thereof, a second (Schottky) collector is connected to receive an input signal, and a third collector which drives internal I.sup.2 L gates. The buffer has a high input breakdown voltage, virtually no input capacitance, power-up/power-down capability at logic "1" and virtually no input current at logic "0", very low storage time, and an input "1" threshold of about 0.5 volts.

Abstract: An improved input circuit is provided for an array of photo detectors. For each photo detector in the array, the circuit utilizes a first FET with a source for coupling to an output of a photo detector, a gate coupled to a first gate voltage, and a drain for coupling to an output circuit. The first gate voltage is provided by a feedback circuit which utilizes matched properties of adjacent FETs. In one embodiment, FETs are used in an open loop feedback circuit to reduce the input impedance seen by the photodiode at the source of the first FET. A similar objective is accomplished in another embodiment utilizing FETs in a closed loop feedback circuit. Further embodiments utilize FETs arranged as a differential amplifier with active loads to provide a low input impedance and a virtual ground at the source of the first FET.

Abstract: A line buffer circuit for coupling an interface to a data highway without requiring separate signal paths for sense and drive functions, comprises a unity-gain voltage amplifier coupling a line in the highway to the respective interface terminal for the sense function, and a current source connected to sink current from the highway line to ground for the drive function. The current source is controlled so that the current passing through it is proportional to the magnitude of the current passing from the amplifier through the interface terminal.

Abstract: A buffer having a single input and a pair of outputs providing three unambiguous logic output states including a first output connected directly to the input and a second output connected to the junction of a common gate configured FET and an impedance. The input is also connected to the source and body of the FET and a voltage source is connected to the impedance. The first output varies with the input for a first polarity input signal and the second output varies with the input for the opposite polarity input signal.

Abstract: A reliable voltage level shifter circuit implemented with complementary metal oxide semiconductor field effect transistor (MOSFET) devices, suitable for high voltage applications. The disclosed circuit is relatively unsusceptible to low voltage transistor breakdown, whereby a wide range output voltage swing is achieved.

Abstract: A self-powered fiber optic interconnect system in which electrical output from data transmitting equipment is converted in a transmitter unit to optical signals in a fiber optic cable for transmission to a receiver unit for reconversion to electrical signals for data receiving equipment and a power source separate from the transmitting and receiving equipment so that the interconnect system can be completely interchangeable with an electrical copper wire interconnect system. When the data transmitting equipment is a computer with parallel data output, the transmitter unit converts the parallel output to serial data output for transmission to the receiver unit over a single fiber optic cable and the receiver unit reconverts the output to parallel data for the data receiving equipment.

Abstract: In a MIS random access memory device including a data-in amplifier and MIS memory cells, a device is provided for holding the output level of the data-in amplifier at the precharge potential of the memory cells except during a write operation by controlling an input circuit and a driver circuit of the data-in amplifier through utilizing the read/write signal and the control signal for the memory. Data stored in the memory cells are free from the influence of the output of the data-in amplifier during a non-write operation.

Abstract: An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.

Abstract: Combining a differential PNP transistor pair for receiving external digital signals with an NPN output transistor in an I.sup.2 L configuration connected to the output of the differential pair provides a simple, high-speed, and versatile digital logic to I.sup.2 L interface circuit. The interface circuit is applicable to almost any digital logic series and also to analog inputs as they provide inputs into I.sup.2 L circuitry.

Abstract: A coupling device for adaptation of I.sup.2 L transistors to a transistor operating with a higher bias current setting on a semiconductor body, said coupling device formed in one island from the combination of a current injector and a normally operated vertical transistor.

Abstract: A level shifter using complementary metal oxide semiconductor (CMOS) transistors is provided. A first transistor couples a first voltage to a node of the level shifter circuit, and the first transistor is controlled by an input signal. A P-channel and an N-channel MOS device are connected in series between the first voltage and a second voltage. The gate electrodes of the P-channel and N-channel MOS devices are connected to the node. An output for the level shifter circuit is taken from a junction formed by the P-channel and N-channel MOS devices. A resistance is coupled between the gate electrodes of the P-channel and the N-channel MOS devices and the second voltage.

Abstract: An amplifier circuit for amplifying an input signal and obtaining true and complementary output signals includes cross-coupled transistors connected to first and second nodes. The first and second nodes are made to be an equal potential by precharging. Then, the potential of the first node is either maintained or changed to a lower (in absolute value) level in response to and dependently on a control input signal, while the potential of the second node is slightly lowered (in absolute value) by dividing the precharged change of the second node with a capacitor. Thus, the first node is controlled by the input signal, while the second node is given a reference potential determined by a capacitance division ratio.

Abstract: A circuit utilizing a source follower and a comparator to interface an MOS digital circuit with bipolar digital circuits is disclosed.