Abstract: A latching circuit with at least one node which is precharged by a precharge signal and discharged by the latching of a particular state in the latch. The at least one node is fed back to a control electrode of a transistor which is in series with an input terminal of the latching circuit. The feedback from the at least one node controls operation of the series transistor so that an input signal appearing on the input terminal can be locked out when the latching circuit has a desired logic signal latched into it.

Abstract: The circuit includes a signal input circuit having a light emitting diode that is optically coupled to a phototransistor in a signal output circuit comprising a noise suppression circuit and a Schmitt trigger circuit. The noise suppression circuit comprises a switch portion including a transistor switch and a timing portion including a capacitor. The transistor switch is connected in parallel with the capacitor, and in the quiescent condition of the line isolation circuit, the transistor switch is turned on so as to maintain the capacitor in a discharged condition. When the light emitting diode is illuminated by an input signal exceeding a particular threshold, the phototransistor is turned on, causing the transistor switch to turn off. The charging of the capacitor thereupon commences.

Abstract: A data rate control device interfacing between a computer and a communication line facilitates reading out of data from the computer at a fast rate and then transmitting that data at a slow rate on the communication line with allowance being made between data transmissions for reflections and echoes on the line to die down. The control device includes a clock generator, control logic and a clock transmitter for sending out Fast Clocks and causing the serial reading in of data to a shift register of the control device. Once the presence of one character of data is detected in the register by the control logic, the Fast Clocks are terminated and Slow Clocks are sent to the register for serial reading out of the data character to a loop transmitter of the control device for transmission of the data character on the communication line.

Abstract: A decoupling apparatus for a charge-coupled device line-addressable random-access memory includes a series of bipolar transistors, the bases of which are connected to output lines from the CCD LARAM. The emitters of the bipolar transistors, connected together, are connected to the source of a depletion-mode MOS reset transistor and to a comparator circuit.

Abstract: A circuit for interfacing with sensors having a loop current flowing therethrough comprising a current mirror utilizing multiple diode-connected transistors for dividing the loop current into several equal subparts and means connected to said current mirror for producing a latching output signal when the current equal to one subpart of the loop current exceeds a predetermined value.

Abstract: The timing pattern of incoming pulses is modified by amplifying the pulses, selectively shifting the dc potential of the amplified pulses, and clipping or slicing the amplified pulses at a predetermined potential. The thus clipped or sliced output pulses have a predetermined timing pattern at a predetermined dc level,resulting in a time pattern correction of the incoming pulses.

Abstract: Transition circuits are provided for interfacing logic gate circuits from different kinds of logic gate families where the characteristic logic state voltage levels differ between the families as do the separations between these logic state voltage levels as they occur in these logic families.

Abstract: A high speed driver for providing high-current and high-voltage output levels suitable for driving MOS circuits, such as MOS RAMs from standard TTL input signals. Novel circuitry in the driver provides very high speed signal switching and a power-saving feature prevents MOS supply current drain by the circuit when TTL power has been turned off.

Abstract: The prior art, low power ratioless true/complement driver is improved upon by connecting a first isolation FET (T2) so that its gate is connected to drain potential (V.sub.DD) and by connecting to the second isolation FET (T4) so that its gate is connected to the phase-splitting node (1). This enables the number of clock pulse sources necessary to operate the generator circuit to be reduced by one so that the speed of the generator circuit is increased, by virtue of the second isolation FET (T4) having a gate size substantially smaller than the gate size of the inverting FET (T3) so that it will more rapidly switch from its on-state to its off-state than does the inverting FET.

Abstract: An MOST buffer circuit has a first normally non-conductive transistor in series with a second normally conductive transistor between earth and a main power supply. A normally discharged bootstrap capacitor is connected between the common connection point of the two transistors and the gate of the first transistor. In response to an input signal, the transistor is switched on, the transistors conduct in series, and the bootstrap capacitor charges. The transistor is then switched off, ceasing the series current and developing an output potential which approximates to that of the power supply.

Abstract: A high speed true/complement driver circuit is disclosed wherein the time interval between the address and memory select pulses are minimized by utilizing a high speed enhancement/depletion mode inverter pair followed by a clocked signal isolation stage. A pair of enhancement mode/depletion mode inverters connected in cascade configuration serves to generate the true and complement output signals which are isolated from noise at the input line by a symmetric pair of clocked FETs.

Abstract: The invention described herein is an interface circuit which effectively allows TTL output voltages to fall within the range of CMOS input thresholds. The interface circuit contains bipolar and FET devices connected to generate an input voltage threshold which is equal to two base-emitter voltage drops. The interface circuit also includes a switching circuit portion which comprises one P-channel MOS transistor connected to one N-channel MOS transistor.

Abstract: A voltage level shifting device for interfacing systems using positive logic levels and systems using negative logic levels. The circuit is so configured that the output of the device can be connected in parallel with a similar device in wired-OR operation and that a short circuit of the output will not cause excessive current flow, and damaging the circuit components.

Abstract: An integrated driver circuit comprises a signal-generating circuit for sending forth output signals when a power source voltage is impressed thereto; a level converting means for changing the level of one of the output signals into a control signal having a voltage n-fold (n>1) larger than the power source voltage; and at least one field effect transistor arranged to be rendered conducting or non-conducting according to said control signal for selective actuation of external display means provided outside of the integrated driver circuit.

Abstract: A memory having a P channel device for each storage element, complementary FET inverters as row drivers for reading and complementary FET devices connected in series as column drivers for reading. A P channel device and a resistor are connected to the source and drain of the N channel device of the row driver and a P channel device is provided as a column driver for the high writing or programming potential. The series P channel device of the column read driver is switched off during writing.

Abstract: Regenerating amplifier for use with two charge coupled devices comprising field effect transistors to pre-charge the output diffusion capacitance of an output charge coupled device and the input diffusion capacitance of an input charge coupled device. The output diffusion capacitance is discharged by the arrival of output charge, in turn holding off an input gate such that the charge on the input diffusion capacitance is not shifted into the input charge coupled device. Various embodiments having control potentials and a field effect transistor to fully discharge the input diffusion capacitance of an input charge coupled device being usable with a plurality of input charge coupled devices having corresponding output charge coupled devices wherein individual charging transistors are available to charge each output diffusion zone capacitance with a common transistor being used to charge all input diffusion capacitances.

Abstract: Disclosed is a field effect transistor (FET) logic circuit which advantageously combines enhancement and depletion mode field effect transistors. A depletion mode input transistor is connected between an input node and an intermediate node and has its gating electrode connected to a fixed potential such as ground. A self-biased depletion mode field effect load transistor is connected between a positive potential and the same intermediate node to which the gating electrode of one or more enhancement mode field effect transistors are also connected. The source electrodes of the enhancement mode field effect transistors are connected to a fixed source of potential such as ground while the drain electrodes of the enhancement mode field effect transistors provide open drain outputs to similarly constructed subsequent logic stages.

Abstract: A high speed address buffer circuit for use in MOS/LSI semiconductor memories or the like. An unbalanced, dynamic cross-coupled pair of MOS driver transistors is used to sense an address input during a short time window, and internal address signals are generated from the state of the sense circuit. Sensing nodes are precharged and equalized prior to the time window, and the node which is to stay at the logic "1" level is held at a high level by boosting capacitors to which a delayed clock signal is applied. The state of the sense circuit is sampled at a time after the delayed clock and high level addresses are generated.

Abstract: An interface for transmitting data in either a clock edge triggered synchous transmission mode or an asynchronous transmission mode. An edge triggered register has its input connected to a source of digital data and its output connected to a two-to-one multiplexer. A bypass path connected between the digital data source and the multiplexer is provided around the edge triggered register. The two-to-one multiplexer is selectively actuable to provide either asynchronous transmission by connecting the bypass path to an output means or to provide synchronous transmission by connecting the output of the edge triggered register to the output means.

Abstract: A complementary MOS voltage level shift circuit which can be used as a memory buffer circuit, for example, is disclosed. The circuit utilizes both N-channel depletion mode devices and P-channel enhancement mode MOS devices preferably fabricated on silicon-on-sapphire. Both types of devices are operated with only negative or zero gate-source voltage in order to minimize threshold voltage shifts in radiation environments. A capacitive voltage level shifting technique is used to obtain push-pull operation with driver type devices in order to reduce power consumption and increase switching speed while feeding into a capacitive load. Load type devices are used to prevent discharge of a capacitive load.

Abstract: An MOS buffer circuit which may be employed as part of a electrically programmable read-only memory or other MOS integrated circuit is described. The buffer may be "powered down" when the memory is in a standby mode. Low threshold (zero threshold) voltage devices are employed in the circuit along with depletion mode transistors and enhancement mode transistors in a manner which permits the buffer to be readily powered down.

Abstract: A MOS control circuit for controlling an output signal, said control circuit being coupled to first and second sources of potential. The magnitude or peak-to-peak amplitude of the first source of potential is greater than the magnitude developed by the second source of potential. The control circuit output signal has a waveshape magnitude of desired dimension somewhere between the magnitude of the second source of potential and the magnitude of the first source of potential. In order to accomplish this, a first inverter receives and inverts an input signal and produces an output potential at a node. A clamping circuit reduces the potential at the node by a desired amount. A source follower is driven by the potential at the node and also receives the input signal. The output of the source follower is the control output signal.

Abstract: An interface circuit for interconnecting an integrated injection logic (I.sup.2 L) portion of an integrated circuit to a linear portion of an integrated circuit. The circuit transfers both logic information and I.sup.2 L current level references from the I.sup.2 L circuitry to the linear circuitry at the relatively large voltage levels present in linear circuitry. One embodiment employs a cascode arrangement involving one transistor, two diodes and a resistor. Another embodiment utilizes the matching characteristics of a pair of transistors operating in the forward and reverse modes respectively to perform the function with only one transistor.

Abstract: A no-delay, ratioless AND gate compatible with a four-phase, major-minor clocking scheme and a six-phase metal oxide semiconductor (MOS) system. The disclosed AND gate can be implemented by the interconnection of first and second field effect transistors having conduction paths thereof selectively connected between a respective input terminal and the output terminal of the AND gate to precharge and conditionally discharge the output terminal.

Abstract: An MOS circuit possessing hysteresis and positive feedback for fast switching includes a first MOSFET having its gate connected to an input. A second depletion mode MOSFET has its drain connected to the source of the first MOSFET and its source connected to ground. A third depletion mode MOSFET has its drain connected to the source of the first MOSFET and its gate and source connected to the drain of a fourth MOSFET and to the gate of a fifth MOSFET. The gate of the fourth MOSFET is connected to the gate and source of a sixth depletion mode MOSFET and to the drain of the fifth MOSFET. The fifth MOSFET has its source connected to ground.

Abstract: An input buffer for MOSFET integrated circuit for receiving low level voltage signals even below the threshold voltages of the transistors comprising the circuit is described. A reference voltage between two logic levels of the input voltage, such as TTL logic signals of 0.8 volts and 1.8 volts, is trapped on a reference storage node and the logic input voltage is trapped on a data input storage node. The two trapped voltages are then capacitively boosted by the same voltage to a level well above the transistor threshold voltage so that the differences in the voltage levels can be amplified, and the logic signal latched up by conventional circuitry. The voltage levels need be only momentarily boosted above the threshold level.

Abstract: A PMOS output buffer circuit permits interfacing directly with TTL, CMOS, and NMOS. A feedback circuit incorporated into the buffer acts to limit the drive current for negative potential output excursions. The feedback circuit is sensitive to device parameters that vary with processing so that the output characteristics can be set independently of process variables.

Abstract: Disclosed is a field effect transistor (FET) circuit utilizing three sources of potential, the third source of potential being derived from the substrate. An input stage, connected between first and second sources of potential, is adapted to receive a logic input signal approximating said first and second sources of potential. An output stage connected between the first source of potential and a third source of potential, is adapted to provide a logical output signal approximating said first and third sources of potential. The third source of potential, which is derived from the substrate, provides a potential level suitable for turning off depletion mode FET devices.

Abstract: A semiconductor memory employs a variety of circuit elements which are used to manipulate the digital information stored within the rows and columns of the memory array. The circuit elements must be manipulated in an ordered sequence with proper relative timing to permit decoding of various addresses and other circuit commands and enabling of various ones of the circuit elements. The plurality of timing signals are generated within the memory by a corresponding plurality of timing generators. Accurate timing and sequencing is obtained by utilizing the output of one timing generator to trigger or initiate the generation of a signal in another generator followed by either proper conditioning upon an input signal, such as an address, or by a predetermined delay designed into the timing generator itself.

Abstract: The decoder buffer is utilized in a memory system for an array of variable threshold MNOS transistor memory cells arranged in word rows. The gate electrodes of the memory transistors comprising each word row is coupled via a word line to the output of a decoder buffer. Inputs to the decoder buffers are provided from address decoder and inverter circuits in response to memory address inputs. FET control circuitry is included for selectively providing operating voltages to the decoder buffers in accordance with the various memory functions performed. Each decoder buffer comprises first, second and third fixed threshold field effect transistors, the first and second transistors being serially connected with respect to each other, forming a junction therebetween which is coupled to the associated one of the memory word lines.

Abstract: An interface circuit for coupling a high voltage AC source to a bistable circuit for deriving a low voltage DC output signal at first and second voltage levels dependent on the condition of a switch. The AC voltage is coupled via the switch, a first voltage divider and first diode means to the set input of the bistable circuit and directly via a second voltage divider and second diode means to the reset input of the bistable circuit. The voltage ratios of the two dividers are chosen so that the bistable circuit is set and remains set when the switch is closed and is reset and remains reset when the switch is opened.

Abstract: A detector circuit for MOS/LSI integrated circuit devices comprises a series transistor which has a sense clock applied to its gate and a gated capacitor connected between the gate and a sense node. The sense node and an input node may be precharged to a level at or near the supply. During the sense clock, the input and sense nodes are shunted together by the series transistor. If at the logic level of the supply, the gated capacitor is off and does not affect the circuit; if the input node decays toward the other logic level, the gated capacitor is on and the trailing edge of the sense clock causes the sense node to be switched to a full logic level.

Abstract: Regenerating amplifier for use with charge coupled devices comprising a pair of diode-coupled transistors connected to an output terminal of one charge coupled device, two capacitances, and means for precharging said two capacitances. One of the capacitances is a parasitic capacitance, the other of which is the input capacitance of the second charge coupled device. The charge is transferred from the output terminal of the first charge coupled device by discharging one precharged capacitor and thus discharging or not discharging the second capacitance at the input to the second charge coupled device, depending upon the binary state of the data being transferred.

Abstract: A gating means couples excitation signals to the input of an inverter which is connected between first and second power terminals. Positive feedback means is connected between the input and the output of the inverter. In response to an excitation signal, whose level is intermediate the levels of the operating voltages applied between the first and second power terminals, the inverter output is driven to the potential at one of the first and second power terminals while the potential at the other one of the first and second power terminals is applied to the inverter input. The gating means, conductive during transitions of the excitation signals from one level to another, does not conduct in the steady state condition, whereby a potential at the inverter input of higher amplitude than the excitation signals is not coupled back to the source of excitation signals.

Abstract: Circuitry for providing electrical isolation between an input signal source and other circuitry which utilizes such input signal. The isolation circuitry uses an optical coupling means comprising a light-emitting diode circuit and a photo-responsive element, the input signal being supplied by a bridge circuit which provides a unidirectional voltage from the input signal which is then applied to a normalizing, or limiting, circuit which converts the unidirectional voltage to a substantially constant value which is supplied to the light-emitting diode circuit. The circuit is responsive to an input signal which can be an AC signal or a DC signal of either polarity, such circuit having a high degree of noise survivability even in the presence of transient noise signals such as "showering arcs" having extremely high amplitudes.

Abstract: In an address buffer circuit in a semiconductor memory including a flip-flop formed of MISFETs and an output circuit consisting of two drivers each formed of MISFETs, and producing a binary address signal, the flip-flop is supplied with a constant operating voltage and triggered by a pulse signal of shorter pulse width than that of a chip enable signal and the MISFETs of the driver on the ground side have the gates cross-coupled to the outputs of the respective drivers so that at least one grounding MISFET in each driver is turned on in the outputting period to prevent the floating of the output level.

Abstract: An MOS input buffer circuit includes an input connected to the gate electrode of an enhancement mode input MOSFET. The drain of the input MOSFET is connected to the output of the input buffer circuit. The source of the input MOSFET is connected to the drain of a second depletion mode MOSFET having its source connected to ground and its gate connected to a V.sub.DD voltage conductor. A load circuit is coupled between the V.sub.DD voltage conductor and the output, and consists of an enhancement mode MOSFET and a depletion load MOSFET coupled in series between output and V.sub.DD voltage conductor. A third depletion mode MOSFET has its drain connected to the V.sub.DD voltage conductor, its source connected to the source of the input MOSFET, and its gate connected to the output. The positive gain (or negative slope) portion of the switching characteristic of the input buffer circuit extends substantially all the way between the high and low output levels.

Abstract: A semiconductor switching circuit utilizes a relatively low breakdown voltage transistor for switching between a higher and a lower voltage by switching between a first conducting state of said transistor which is a "turned-on" state and a second state which is a "breakdown" state. The switching circuit is especially useful for the operation of display devices.

Abstract: Each end of a transmission line comprises a lightning protector and a component ensuring a connection under complete electro-insulation with an emitter on one hand and a receiver on the other hand.

Abstract: A source follower circuit which exhibits essentially zero input to output voltage drop and very low capacitive loading on the input. A current mirror arrangement is used. The input is connected to the gate of a depletion mode transistor which is connected in series with an enhancement mode device. The gate of the enhancement device is biased by a series circuit having a depletion device with gate shorted to source and an enhancement device with gate shorted to drain.

Abstract: A complementary MOS logic circuit is disclosed. The circuit utilizes two stages with a coupling network comprising a capacitor and a diode used to couple the first stage to the second stage. This results in a circuit with the logic signal coupled to the input being inverted at the output without introducing substantial loss in signal amplitude.

Abstract: This relates to an MOS logic synchronizing circuit operating with a single phase clock waveform. A logic inverter has two parallel-connected switching MOST's, the gate of one (M4) being connected to clock and the gate of the other (M2) being coupled to the logic input via the source-drain path of a third MOST (M1) whose gate is connected to clock. Input signal change is delayed by a full clock period.

Abstract: A voltage boosting circuit comprises a plurality of units connected in sequence and each composed of a condenser and a plurality of MOS-FETs without any transformer or diode. The boosting circuit lends itself to miniaturization by integrated circuit technique.

Abstract: In a sensing amplifier for a capacitive MISFET memory, the level of an output signal from the memory is shifted by a signal level shifting circuit and the level-shifted signal is applied to an input of the sensing amplifier to thereby provide a high speed operation.

Abstract: An MOS buffer circuit particularly suitable as an input stage for receiving a lower level input signal in an MOS integrated circuit. A transistor is employed to decouple an input transistor from a load, thereby allowing an output signal from the circuit to rise more quickly.

Abstract: Regenerator circuit for CCD elements in which charge representing information is transferred from a first CCD element to a second CCD element. The circuit includes a first MOS capacitance and a second capacitance connected in series with the first capacitance, the point at which the two capacitances are connected with one another being connected to the input of said second CCD. The output of the first CCD includes an output stage having an output diffusion zone. A transistor is connected between a terminal to which a potential .phi..sub.v can be connected and the point between said first and second capacitances. This transistor has a gate electrode which is connected by a line to the output diffusion zone of the first CCD.

Abstract: A level shift circuit comprises an inverter connected to a first voltage supply source and supplied with an input pulse. A condenser and a directional switching element are connected in series between the output point of the inverter and one potential point of the first voltage supply source. The input of a first MOS-FET is connected to the output of the inverter while the input of a second MOS-FET is connected to a connection point between the condenser and the directional switching element. The source of the first MOS-FET is connected to a common terminal of first and second voltage supply sources while the source of the second MOS-FET is connected to the other terminal of the second voltage supply source. An output voltage is generated between a common connecting point of the drains of the first and second MOS-FETs and one potential point of the second voltage supply source.

Abstract: A high speed circuit for converting CML/ECL gate signals to TTL gate signals. The circuit includes two parallel current paths coupled to a current mirror section in which uniform current is maintained in portions of each path. Each current path includes a transistor which is coupled to the CML/ECL gate for sensing the differential voltage in the gate. The TTL gate is coupled to one of the current paths which steer current into or out of the TTL gate depending upon the differential voltage sensed in the CML/ECL gate.

Abstract: A voltage level shifting driver and receiver for interfacing systems using ositive logic levels and systems using negative logic levels. The driver operates to convert positive voltage logic levels to negative voltage logic levels and the receiver operates to convert negative voltage logic levels back to positive voltage logic levels.

Abstract: A high speed buffer circuit having an input and complementary outputs includes a pair of feedback transistors for shortening the response time of the output signals at the complementary outputs and a capacitive load at each output for delaying the effect of the output signals on the feedback transistors.