Abstract: Each one of two switching transistors, driven by complementary input signals, has its conduction path connected between a different one of two output terminals and a first point of potential. Connected between each output terminal and a second point of potential are the conduction paths of a load transistor responsive to the signal at the other output terminal, and an input signal responsive transistor. When the switching transistor connected to one output terminal is being turned on, the effective impedance of the input signal responsive transistor connected between that output and the second point of potential is increased, thereby increasing the speed of response of the circuit and minimizing its power dissipation.

Abstract: A protection circuit for a monolithic integrated circuit in which regions of one conductivity type are formed in a common substrate of complementary conductivity type and in which a first voltage is applied to the substrate to prevent forward conduction through the junctions formed between the regions and the substrate. The protection network includes a control element, responsive to the first voltage, which is connected between a second voltage point and selected regions for coupling the voltage at the second point to the selected regions only in response to the presence of the first voltage. This prevents the junctions formed by the selected regions and the substrate from being forward biased and carrying excessive and/or destructive currents when the first voltage is absent.

Abstract: The phasing circuit transfers digital data from an external interface circuit to an internal interface circuit with no bit errors and no violation of bit count integrity under control of an external clock having a given frequency and a given phase and an internal clock having a frequency equal to the given frequency and a phase that is different than the given phase.

Abstract: A memory input signal dynamic logic buffer circuit for providing FET level complementary output signals in response to low level input signals. The circuit is compatible with a variety of bipolar transistor driving logic families as the input signal sensitivity may set external to the circuit. The circuit includes a cross-coupled dynamic latch responsive to gated input and reference signals. Voltage boosting capacitors coupled to the latch nodes provide for simultaneous setting of the latch and boosting of the output nodes, which are connected to dynamic output driver circuits.

Abstract: A circuit arrangement which permits interfacing logic systems operating on different logic levels and thus requiring different supply voltages in which the supply voltage for the logic system having the smaller signal excursion is obtained by means of a pair of zener diodes connected in series across the potential and reference potential of the logic system having a larger signal excursion to develop a potential and reference potential for the system having smaller signal excursions lying between the respective potential and reference potential levels of the system having larger excursions.

Abstract: A circuit of complementary field effect devices whose logical input threshold voltage can be varied between levels suitable for TTL logic or CMOS or PMOS or other logic under control of an electrical signal in real time.

Abstract: A signal converter circuit for converting a binary signal delivered from a bipolar transistor logic circuit into another binary signal adapted for application to a MIS transistor logic circuit. The converter circuit comprises first, second and third stages; the first stage includes a source follower circuit, the second stage includes a series connection of a pair of parallel-connected MIS FETs and a switching MIS FET, and the third stage includes an inverter circuit. The output of the third stage is fed back to the gate of one of the pair of MIS FETs in the second stage so that the converter output has binary levels acceptable to a MIS logic circuit.

Abstract: This specification discloses an improvement for a voltage booster circuit. The improvement lies mainly in the use of MISFETs as switching means in a level converting circuit constructed in a complementary MIS semiconductor integrated circuit and therefore the voltage loss due to the conventional switching means can be prevented.

Abstract: The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to a FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed.

Abstract: A logic level converter converts an input signal having first and second voltage levels to an output signal having first and third voltage levels in which the voltage excursion of the output signal is greater than that of the input signal. The converter comprises first and second cross-coupled inverters in which the second inverter provides the output signal and is biased with respect to the first and third voltage levels and in which the first inverter is biased with respect to the third voltage level and the digital input signal. A voltage divider is associated with the first inverter to insure sufficient voltage swing for proper switching of the inverters. The inverters have dissimilar gains to insure that when the inverters are biased at equal voltages, the inverters always assume a predetermined state. The converter is implemented with PMOS field effect transistors and includes capacitors for increasing switching speed.

Abstract: An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=1nM, ##EQU1## AND WHERE THE CAPACITANCE OF ANY INTERMEDIATE STAGE IS C.sub.P =.sqroot.C.sub.(P.sub.-1) .sup.. C.sub.(P.sub.+1). Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one.

Abstract: An integrated circuit bipolar bootstrap driver has an interface circuit means, a low logic level circuit means and a bootstrap, high logic level circuit means. The interface circuit means is coupled to the low logic level and high logic level circuit means and selectively activates one of the circuit means in response to an input signal. The high logic level circuit means includes an integrated circuit npn Darlington pair and a pnp low current, low speed lateral type integrated circuit transistor in combination with an integrated circuit capacitor which is used to provide a bootstrapped high logic level signal.

Abstract: Two semiconductor chips having complementary MOS circuits are interconnected by means of an output stage provided on the first chip and an input stage provided on the second chip. The connection is a high-speed connection despite the relatively high internal impedance of the MOS transistors. The output stage incorporates MOS transistors for transforming the signal level to a relatively low level, and the input stage incorporates MOS transistors interconnected as a pulsed trigger or amplifier for restoring the low signal to a relatively high level for connection to other MOS circuits.

Abstract: Input signals lying outside the power supply range are used to develop potentials which are applied to the gate electrodes and substrates of transistors forming a transmission gate, when the transistors are to be turned off. The transmission gate circuit can then block input signals outside the range of its power supply.

Abstract: A two bit partitioning circuit for a dynamic programmed logic array which introduces two stages of delay in the signal path in one clock cycle, with minimum power dissipation. The circuit has two primary inputs and four outputs which serve as inputs to a bootstrap driver which produces an output signal to the programmed logic array. A basic path through the circuit consists of two stages, the first stage comprising two active devices (FET) and a first capacitive means, while the second stage comprises three active devices and a second capacitive means. The major portion of the capacitance of the second stage is provided by the capacitance of the bootstrap driver. The stages are dynamic with the discharge speed of the first stage being much faster than that of the second stage thereby enabling a signal to propagate through the two stages in one clock cycle, with the only power dissipation being that required to charge the two capacitive means.

Abstract: A MOS logic circuit includes a source follower circuit arrangement consisting of a driver MOS element, in addition to a transfer MOS element, an inverter MOS element and a load MOS element. The transfer MOS element receives input signals at its source and produces output signals at its drain, the output signals being applied to the gate of the driver MOS element contained within the source follower circuit arrangement. The resulting output signals developed at the source of the driver MOS element are supplied to the inverter MOS element. This permits the slice or boundary level between the logical 1 and 0 to be higher than the given threshold level of the MOS elements.

Abstract: Circuits for generating pulsating potentials and voltage levels outside the range of, and/or of greater magnitude than, the operating potential applied to the circuits. Each circuit includes first and second transistors for applying a first voltage to one plate of a capacitor and a second voltage to the other plate of the capacitor, during one time interval. During a subsequent time interval, the first and second transistors are turned off and a third transistor applies the second potential to the one plate of the capacitor. The change in the potential at the one plate of the capacitor is coupled to the other plate of the capacitor at which is produced an output potential outside the range of the first and second voltages. The potential difference between the first voltage and the output potential is greater in amplitude than the potential difference between the first and second voltages.

Abstract: Improved circuits for a MOS-RAM including an on chip TTL compatible high-level clock driver and sense amplifier. The driver employs a unique feedback and delay scheme allowing the high-level line to be quickly and efficiently discharged without using a large, high capacitance device. The upward swing of the control signal for the sense amplifier includes a perturbation which increases the sensitivity of the amplifier.

Abstract: A driver circuit comprises an output circuit having a depletion type MOSFET and an enhancement type MOSFET connected in series with the depletion type FET. A voltage V1 is supplied to the drain of the depletion type FET and a voltage V2 is supplied to the source of the enhancement type FET, wherein .vertline.V1.vertline. > .vertline.V2.vertline. > .vertline.V th D.vertline., VthD being the threshold voltage of the depletion type MOSFET. A control signal is supplied directly to the gate of the enhancement type FET and, through an inverter, to the gate of the depletion type FET. As a result, a push-pull driver circuit using E/D MOSFETs is obtained.

Abstract: An amplifier circuit for amplifying an input signal includes a flip-flop circuit activated by a timing signal. A trigger circuit generates a first trigger signal of the same polarity as the input signal and another circuit generates a second trigger signal of the opposite polarity to the input signal. The flip-flop circuit is triggered by the first and second trigger signals at the same time the flip-flop circuit is activated by the timing signal.

Abstract: A two branch circuit for converting dual complementary signals characterizing emitter coupled logic to a single signal characterizing transitor-transistor logic. A two branch circuit supplies translation between ECL input signals, referenced to a voltage supply and TTL output signals, referenced to ground, using a current summing node receiving current from both branches and connected to a TTL output driver. A first circuit branch includes a feedback loop which generates a reference current summed with the current in the second branch.

Abstract: A novel sense amplifier circuit providing conversion of MOS input signals to TTL output signals with tri-state logic output at the output data bus, the input circuit of the sense amplifier providing current sensing and programmable input thresholds for economical construction and enhanced speed of operation of the sense amplifier. A novel tri-state operation is provided for the input section of the sense amplifier to provide either a clamped voltage at the input data bus line during MOS to TTL communication or a floating input when it is desired that MOS devices on the input data bus are to communicate.

Abstract: A network for preventing large transient currents in the conduction paths of a pull-up transistor connected between a first point of operating potential and an output point and a pull-down transistor connected between the output point and a second point of operating potential. The network includes a third transistor having its base to emitter path connected in parallel with the base to emitter path of the pull-down transistor and its collector coupled to the base of the pull-up transistor. The collector current of the third transistor is limited, causing it to saturate at a given current level and to then limit the flow of additional base drive to the pull-down transistor, whereby the maximum collector current of the pull-down transistor is also limited. In addition, a diode is connected between the output point and the collector of the third transistor.

Abstract: An asynchronous interlock circuit for an interface adaptor circuit in a digital system includes a D-type latch, a D-type flip-flop, and an RS-type flip-flop interconnected to accept a peripheral status input from a peripheral equipment unit, a read status input and a read data input derived from control and selection inputs to the interface adaptor from a microprocessor unit of the digital system. The asynchronous interlock circuit stores information corresponding to a logical "1" on the peripheral status interrupt input in the D-type flip-flop, even if the latter signal disappears prior to acknowledgment by the microprocessor of a corresponding interrupt signal generated by the interface adaptor circuit. The D-type flip-flop is reset by a sequence of a read status signal and a read data signal, thereby avoiding problems which could arise if the peripheral status input remains at a logical "1" even after acknowledgment by the microprocessor unit of an interrupt signal generated by the interface adaptor.

Abstract: A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, thereby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.

Abstract: An apparatus is disclosed which comprises an improved voltage driver circuit. Commonly available voltage driver circuits are deficient for driving n-channel MOS RAMs due to insufficient peak voltage and extended rise time. The apparatus, without requiring an additional voltage power supply or modifications to the memory system environment, effectively increases an internal drive voltage which results in the desired performance characteristics for driver circuits.

Abstract: An electrical transformer for transforming electrical impedances of high transformation ratios including a dielectric substrate having a pair of parallel electromagnetic coupled-transmission lines bonded to one surface of the dielectric substrate. The first of the pair of transmission lines being adapted to be connected to a first impedance at one end with the other end being connected to a ground terminal through a first tuning capacitance which varies the real part of the transformed impedance. The second of the pair of transmission lines being coupled, at its end opposite the first tuning capacitor, through a second tuning capacitance to a second impedance to which the first impedance is to be matched. The second tuning capacitance is utilized to vary the imaginary part of the transformed impedance.

Abstract: A dual inverter circuit wherein the first inverter circuit includes a pair of phase splitter transistors, one serving to feed the base of the pull-up transistor in the first inverter circuit and the other serving to feed the base of the phase splitter transistor in the second inverter circuit. The circuit provides a minimum delay time between the operation of the first inverter and the turn-on time of the second inverter while also providing active pull-up circuits, i.e., pull-up transistors, in the two inverters to insure fast operate times for both inverters especially desirable when feeding into large capacitance loads.

Abstract: A logic gate circuit includes a resistance divider input to the base of an input transistor and a multiple emitter output transistor in an emitter follower configuration. The circuit has favorable switching speed and power dissipation characteristics and reduces the effect of both capacitive loading and series resistance in signal interconnections. An efficient layout of one such logic circuit has intercell wiring channels formed across the circuit and has the inputs and outputs of the circuit arranged in two lines each of which crosses perpendicular to the wiring channels.

Abstract: A logic level translator uses a current switch, a current source and a plurality of cathode followers to convert T.sup.2 L and DTL level binary signals into CML and ECL level binary signals. The translator provides isolation between the T.sup.2 L ground and the CML ground so that noise in the CML signals is reduced.

Abstract: A driving logic circuit having input and output terminals and first and second power terminals is described in combination with an interfacing means for making the driving logic circuit compatible with a driven logic circuit. This is accomplished by providing a first D.C. power source means which is connected across the first and second power terminals, and a second D.C. power source means which is connected in opposition to the first D.C. power means. With this arrangement the D.C. power to the power terminals is shifted to the extent of the voltage of the second D.C. power source means so as to be made compatible with the driving voltages required to drive the driven logic circuit.

Abstract: A buffer amplifier for use with a ripple-carry binary generator comprises a pair of serially connected FET transistors. The input to one of the transistors is precharged by the preceding generator stage and also receives the ripple carry signal. A feedback loop from the output of the transistor to the input hastens the transition from the pre-charge condition to ground.

Abstract: A combination of a linear integrated circuit supplied with voltages from a first dc voltage source and a second dc voltage source of lower power capacity and opposite polarity, a switching circuit for performing a switching action according to the output signal of the linear integrated circuit without consuming power from the low capacity dc voltage source, and a digital circuit operable by the reception of the switching signal from the switching circuit. The low level dc voltage source provides a voltage by converting the voltage supplied from the first dc voltage source.

Abstract: An electronic timepiece having the electronic circuitry formed as a single monolithically integrated circuit chip is provided, a first portion of the circuitry being actuated by a first potential and a second portion of the circuitry being actuated by a second potential higher than said first. The circuit chip includes complementary coupled MOS transistors, the first and second circuit portions operating respectively at first and second logic levels. An interface is provided intermediate said first and second circuit portions, the interface being adapted to effect an interfacing of said logic levels, and an electrical insulation of said first and second circuit portions.

Abstract: A pulse level correcting circuit wherein a resistance is interposed between the input and output sides, and a branch line including a switching element is disposed between an output terminal and a reference voltage terminal, the switching element being adapted to cause a current to flow through the resistance when the level of an input pulse is on the ground level side, whereby the level of the input pulse is corrected by the voltage drop across the resistance at the current flow.

Abstract: A C MOS level converter for converting low voltage control signals to equivalent control signals of a relatively high voltage which operates with extremely low power consumption. The level converter has first and second pairs of P-type MOS transistors coupled source to source and drain to drain, the commonly connected sources of each pair being coupled to ground potential and the gate of each outer transistor of each pair being coupled to low voltage control signals of opposite phase. The gate of each inner transistor of each pair is coupled to the common drain terminal of the other pair, and the common drain terminal of each pair is coupled to the drain terminal of a different one of a pair of N-type MOS transistors. The gate of each N-type transistor is coupled to the gate of the associated inner transistor of the first and second pairs.

Abstract: A switching circuit is disclosed that is operative from a single supply voltage and is capable of switching in response to both positive and negative voltage input signals and exhibits hysteresis within defined positive and negative threshold voltage limits with respect to a datum voltage level. The circuit includes an input transistor having an input electrode connected to the signal input terminal and a transistor - diode current mirror connected to said input electrode whereby the current mirror defines one of the threshold voltage limits.

Abstract: coupling of signals between Large Scale Integrated Circuit chips is facilitated by provision of an emitter follower output stage for the chip. Special input circuits are also provided. The logic circuits may be DTL or Schottky TTL. The special input circuit may be a DTL type or a CTL (complementary transistor logic) type. Pull down resistors may be employed with the emitter follower output driver and the special DTL input circuit.