Selective Patents (Class 323/354)
  • Patent number: 10082488
    Abstract: An ultrasound device, including a profile generator, an encoder configured to receive a profile signal from the profile generator, and an attenuator configured to receive a signal representing an output of an ultrasound sensor and coupled to the encoder to receive a control signal from the encoder, the attenuator including a plurality of attenuator stages, the attenuator configured to produce an output signal that is an attenuated version of the input signal.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: September 25, 2018
    Assignee: Butterfly Network, Inc.
    Inventors: Kailiang Chen, Tyler S. Ralston
  • Patent number: 9800136
    Abstract: An active damper and a power supply according to exemplary embodiments include: a damper resistor coupled to an input voltage; a damper switch coupled in parallel with the damper resistor; and a capacitor to which a reset current generated by a leading edge of the input voltage flows. The damper switch is turned off by the reset current.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 24, 2017
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Hyun-Chul Eum, Young-Jong Kim
  • Patent number: 9625933
    Abstract: A switchable voltage regulation circuit includes a power supply chip and a voltage regulation module. The voltage regulation module includes first and second resistors and first and second switch units. A first terminal of the first resistor is electrically coupled to a power supply and a first output pin of the power supply chip. A first terminal of the second resistor is electrically coupled to the second terminal of the first resistor. The first switch unit is electrically coupled between the first terminal of the first resistor and the second terminal of the first resistor. The second switch unit is electrically coupled between the first terminal of the second resistor and the voltage output. By manual switching, or by transistors under control of a baseboard management unit, the resistances can be switched in or switched out to regulate the voltage.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: April 18, 2017
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Liang-Yi Cui, Jun-Jun Lu
  • Patent number: 9201099
    Abstract: Conductive strips are stacked, insulated, folded, and formed into geometric shapes to provide a low resistance, low inductance, shunt, wherein the geometric shape readily enables cooling to reduce changes in resistance due to self-heating effects. One such geometric shape is attained by winding the conductive strips into a spiral. Another geometric shape is a shape resembling a wave. Both geometric shapes allow cooling by directing airflow from a fan across their surface portions. A variable-speed cooling-fan is controlled in response to measured temperature of the shunt, or in response to a measurement of the current through the shunt. Differential cooling may be employed by means of changing the amount of airflow across various portions of the shunt in response to measured temperature of the shunt.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: December 1, 2015
    Assignee: TEKTRONIX, INC.
    Inventors: Andrew John Tedd, John Stewart Ford, Lionel Ind
  • Patent number: 9000737
    Abstract: Provided is a maximum power extraction devices including: a battery; a voltage control unit adjusting a size of a first power outputted from the battery according to a resistor selected from a plurality of resistors, and generating a compare signal according to a size difference between an operating voltage adjusting the size of the first power depending on the selected resistor and a reference voltage; a switching unit connected between the battery and a load and adjusting a size of the operating voltage according to a size difference of the compare signal in response to first and second switching control signals; a switching control unit generating the first and second switching control signals to allow a size between the operating voltage according to the compare signal and the reference voltage to be within an error range; and a maximum power control unit measuring the number of first operations obtained by counting the occurrence number of the first or second switching control signals for a predetermined
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: April 7, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sewan Heo, Yil Suk Yang, Jong-Kee Kwon
  • Patent number: 8816668
    Abstract: A semiconductor circuit includes a control signal generation circuit configured to generate control signals in response to a voltage characteristic determination signal and a reference voltage generation circuit configured to output a main reference voltage, having one of a first characteristic of being proportional to temperature, a second characteristic of being constant irrespective of temperature, and a third characteristic of being inversely proportional to temperature, in response to the control signals.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: August 26, 2014
    Assignee: SK Hynix Inc.
    Inventor: Je Il Ryu
  • Patent number: 8803502
    Abstract: A voltage regulator includes a voltage generation unit, a first resistor section, and a second resistor section. The voltage generation unit compares a reference voltage level with a voltage level of a first node and generates an output voltage. The first resistor section includes a first sub-resistor and a second sub-resistor between the first node and a ground voltage node, and controls a connection between the first sub-resistor and the second sub-resistor to change a resistance value of the resistors. The second resistor section includes a reference resistor, a plurality of unit resistors, and a plurality of step resistors, and controls connections of the unit resistors and the step resistors to change a resistance value of the resistors.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: August 12, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyun Chul Lee
  • Patent number: 8610421
    Abstract: A current generator includes an op-amp having a negative terminal arranged to be coupled to an input voltage, a resistance selection circuit having at least one tunable resistor connected with each other, and at least one power transistor. A gate of the at least one power transistor is coupled to an output of the op-amp, and a drain of the at least one power transistor is coupled to the at least one tunable resistor or a load. The resistance selection circuit is configured to select a node of the at least one tunable resistor based on the input voltage for coupling from a positive terminal of the op-amp. The at least one tunable resistor is configured to adjust a resistance setting to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Chih-Chang Lin
  • Patent number: 8054060
    Abstract: A switched mode power supply unit realized by an integrated circuit comprising a control circuit controlling the operation of the switched mode power supply unit, wherein the control circuit is configured to provide a plurality of different circuit configurations for different operating environments. The circuit configuration for the control circuit is defined by a control signal received by the control circuit.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: November 8, 2011
    Assignee: Nokia Coporation
    Inventors: Martti Ojanen, Hannu Virta
  • Patent number: 7986197
    Abstract: Simple and compact structures for an attenuator or resistor ladder can be implemented in a standard integrated circuit process as well as hybrid, thick or thin film ceramic processes, which allows metallization along with resistive components. The structure has the mathematical property that it attenuates an applied reference voltage logarithmically/exponentially along its length because of the natural solution of the Laplace equation for this type of geometry and contact configuration.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 26, 2011
    Assignee: Lonestar Inventions, L.P.
    Inventors: Osman Ersed Akcasu, Barbaros Sekerkiran
  • Patent number: 7986137
    Abstract: Multiple characteristics of a DC-DC converter, such as its mode of operation (e.g., either forced continuous conduction mode, or discontinuous conduction mode), and an operational parameter (such as the dead-time between switching times of the output switching devices (upper and lower MOSFETs) of the converter, whose associated driver integrated circuit has a pin usage that leaves only a single pin available for auxiliary purposes, are programmed by a single pin-based digital and analog information extracting circuit that couples both digital information and analog information within the same control signal to the driver IC by way of only the one available pin.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: July 26, 2011
    Assignee: Intersil Americas Inc.
    Inventors: Steven P. Laur, Wei Dong, Mehul Dilip Shah
  • Patent number: 7965065
    Abstract: A trimming circuit which comprises a shunt circuit having two shunt resistors and two shunt ON/OFF switches and connected in parallel with a series resistor circuit. The middle point of the shunt circuit is connected to a connection point of the series resistor circuit, the resistance ratio thereof with respect to the connection point being equal to the resistance ratio of the shunt resistors.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: June 21, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akihiro Hirota
  • Patent number: 7889048
    Abstract: A variable resistor network has a coarse resistance network and a fine resistance network connected in series with the coarse network. The coarse resistance network comprises a chain of series-connected resistors any one or more of which may be switched out of the series by individual parallel-connected relays. The fine network comprises a shunt resistor together with a fixed resistor and a series-connected adjustable resistor together connected in parallel with the shunt resistor. A control circuit is arranged to control the relays for the switching of the resistors of the coarse network and also to control adjustment of the adjustable resistor. A chosen resistance value can be set by appropriate switching of the coarse network and adjustment of the adjustable resistor.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: February 15, 2011
    Assignee: Pickering Interfaces Limited
    Inventors: David Paul Owen, Keith Thomas Moore
  • Patent number: 7868604
    Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
    Type: Grant
    Filed: November 18, 2007
    Date of Patent: January 11, 2011
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
  • Patent number: 7813151
    Abstract: A converter control circuit applicable to various topologies of converters each employing two switching devices is disclosed. The converter control circuit includes an oscillator for generating a pulse signal and triangle-wave signal of a certain frequency, a switching control signal output unit for outputting a switching control signal to control ON/OFF of a plurality of switching devices based on a duty ratio determined from a feedback signal which is applied to a feedback terminal, a mode select signal generator for generating a mode select signal for determination of a control mode of a converter in response to the feedback signal applied to the feedback terminal, and a mode selecting unit for selecting the control mode in response to the mode select signal.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: October 12, 2010
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventor: Hang-Seok Choi
  • Patent number: 7812589
    Abstract: A current source is provided with two resistor banks, and digital potentiometers are used to control how much each resistor bank affects the resulting output current. Furthermore, when the digital potentiometers are at a particular setting such that a particular resistor bank does not affect the resulting output current (i.e., the resistor bank is “inactive”), the resistance of that resistor bank can be switched without affecting the output current, thus minimizing or eliminating discontinuities in the output current during a current sweep operation. Thus, for example, when a resistor bank meets its threshold and becomes inactive, the resistance of the inactive resistor bank may be switched, and then the digital potentiometer setting may be changed to facilitate smoothly reactivating that resistor bank, with the new resistance.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: October 12, 2010
    Assignee: QualiTau, Inc.
    Inventors: James Borthwick, Peter P. Cuevas, Tal Raichman
  • Patent number: 7733615
    Abstract: A dynamic braking load analyzer that determines the proper resistance value for a dynamic braking load resistor to be used in combination with a variable frequency drive or servo-drive to accommodate the power dissipated from an induction motor when it is being reduced in speed. The analyzer includes a resistor bank having a plurality of resistors electrically coupled in parallel. Switches are provided between the resistors, and a resistor selector switch determines which resistors are switched into the resistor bank circuit. A heat sensing resistor in the resistor bank measures the heat generated by the resistors and provides a signal that is read by a heat meter. The combination of the temperature measurement and the resistance of the resistors in the circuit gives the proper braking resistance value for the deceleration of the induction motor.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: June 8, 2010
    Assignee: Powerohm Resistors, Inc.
    Inventors: Joseph S. Eschleman, Thomas Yingling, Michael Crowe
  • Patent number: 7639024
    Abstract: A resistance compensation circuit and a method thereof for tuning frequency, includes several resistors serially connected to one another, several transistors, each of which connects across one of the corresponding resistances, and a register electrically connected to the gates of the transistors. A control signal controls the switching of the transistors either to compensate the process variation of the resistance through the register or to tune the working frequency of the Integrated circuit.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: December 29, 2009
    Assignee: Siliconmotion Inc.
    Inventor: Te-Wei Chen
  • Publication number: 20090243726
    Abstract: A variable resistor array adapted to make a resistance value between a first terminal and a second terminal variable, includes a plurality of resistors connected in series, first through nth MOS transistors selectively connected to the resistors, and first through nth switches having one input terminal connected to the source of the ith MOS transistor, another input terminal connected to a predetermined voltage, and an output terminal connected to a back gate of the ith MOS transistor, and connecting either one of the one input terminal and the other input terminal to the output terminal under control of the ith control signal. The ith switch connects the other input terminal to the output terminal, and the ith switch also connects the one input terminal to the output terminal.
    Type: Application
    Filed: March 16, 2009
    Publication date: October 1, 2009
    Applicant: Seiko Epson Corporation
    Inventor: Takashi KOJIMA
  • Publication number: 20090234600
    Abstract: A load calculation control method and apparatus for load characteristic tests of electric generator and the like is provided, which enables continuous and precise following of a load control value and maintaining the value without using industrial water. In this apparatus, a resistor bank ?, which is to be connected to a load apparatus provided with a power supply apparatus (G), a ground relay (GR), a voltmeter (V), an electric power meter (P), an ampere meter (A), and main circuit breakers (CB, CBH), is divided into two or more (2-N). A switch (CL/CH) and a controller (CV) are connected to each resistor bank (?1-?N). each of which is assigned and maintained at a power capacity obtained by dividing, based on binary number, the maximum power capacity of resistor bank groups (?L, ?H) by two through (2n?1).
    Type: Application
    Filed: May 30, 2006
    Publication date: September 17, 2009
    Applicant: KOKEN COMPANY, LIMITED
    Inventor: Kesafumi Matsumoto
  • Publication number: 20090167283
    Abstract: Multiple characteristics of a DC-DC converter, such as its mode of operation (e.g., either forced continuous conduction mode, or discontinuous conduction mode), and an operational parameter (such as the dead-time between switching times of the output switching devices (upper and lower MOSFETs) of the converter, whose associated driver integrated circuit has a pin usage that leaves only a single pin available for auxiliary purposes, are programmed by a single pin-based digital and analog information extracting circuit that couples both digital information and analog information within the same control signal to the driver IC by way of only the one available pin.
    Type: Application
    Filed: March 11, 2009
    Publication date: July 2, 2009
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Steven Patrick Laur, Wei Dong, Mehul Dilip Shah
  • Patent number: 7504816
    Abstract: Multiple characteristics of a DC-DC converter, such as its mode of operation (e.g., either forced continuous conduction mode, or discontinuous conduction mode), and an operational parameter (such as the dead-time between switching times of the output switching devices (upper and lower MOSFETs) of the converter, whose associated driver integrated circuit has a pin usage that leaves only a single pin available for auxiliary purposes, are programmed by a single pin-based digital and analog information multiplexing circuit that couples both digital information and analog information within the same control signal to the driver IC by way of only the one available pin.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: March 17, 2009
    Assignee: Intersil Americas Inc.
    Inventors: Steven Patrick Laur, Wei Dong, Mehul Dilip Shah
  • Publication number: 20080309314
    Abstract: A voltage regulator and a method of manufacturing the voltage regulator, which can provide a desired output voltage of the voltage regulator using a plurality of metal wires, arranged in regular patterns, and conductive metal wiring patterns, configured to activate the metal wires by selectively connecting them to each other when a voltage regulator having various output voltage patterns is produced through a single chip, thus reducing the costs of manufacturing the voltage regulator by simplifying the manufacturing process while reducing the size of the chip of the voltage regulator.
    Type: Application
    Filed: December 7, 2007
    Publication date: December 18, 2008
    Applicant: Taejin Technology Co., Ltd.
    Inventor: Kee Seok Chang
  • Patent number: 7446577
    Abstract: Disclosed is a controller for driving current of a semiconductor device having an over-driving function, the controller comprising: a load means supplied with an internal voltage; a plurality of switching means, each of which has a first terminal connected to an external voltage and a second terminal connected to the load means, wherein at least one of the plurality of switching means is selectively turned on/off according to an voltage level of the external voltage.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: November 4, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae Il Kim, Kang Seol Lee
  • Publication number: 20080067998
    Abstract: An optical pointing device and a power supply semiconductor device therefore are provided. The optical pointing device includes: an optical unit for irradiating light to an object using a light source and receiving light reflected by the object to output an optical image; a motion sensor for receiving the optical image, sensing image data, and calculating a motion value to output the motion value; a moving velocity sensor for receiving the motion value and calculating a moving velocity of the optical pointing device to output the moving velocity; and a variable power supply for generating a different power supply voltage according to the moving velocity. The optical pointing device can generate different optimum power supply voltages required for respective internal blocks and variably apply a power supply voltage according to the moving velocity. Thus, the supply of unnecessary power is cut off, thereby preventing waste of power.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 20, 2008
    Applicant: ATLAB INC.
    Inventors: Bang-Won LEE, Sung-Hyuk HONG
  • Patent number: 7339362
    Abstract: An alterable DC power supply circuit includes a regulator, a resistor, and an adjustable load resistance. The regulator includes a voltage input pin, a voltage output pin, and an adjusting pin. The resistor is coupled between the voltage output pin and the adjusting pin. The adjustable load resistance is coupled between the adjusting pin and ground. The output voltage of the alterable DC power supply is adjustable by adjusting the adjustable load resistance. Using this alterable DC power supply to test the voltage stability of a chipset improves testing efficiency.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: March 4, 2008
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Heng-Chen Kuo
  • Patent number: 7292019
    Abstract: The control precision of one or more parameters of an integrated circuit (IC), for example the output voltage of a voltage regulator comprised in the IC, may be improved even when using inaccurate components external to the IC. Control of the output voltage, or any parameter, using components external to the IC may include coupling a resistor to the IC and measuring the actual resistance value of the resistor, and based on the measured value, selecting a nominal resistance value from a set of resistance values previously specified by the user. The output voltage, or parameter, may be generated according to the nominal resistance value instead of the actual resistance value, thereby reducing the error that may be incurred due the actual resistance value of the resistor not matching the expected nominal value of the resistor.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: November 6, 2007
    Assignee: Zilker Labs, Inc.
    Inventor: Kenneth W. Fernald
  • Patent number: 7269239
    Abstract: A two-wire communication protocol between a controller device and a controlled device, wherein both devices are coupled by a clock line and a data line. The controller device sends control signals comprising N bits, N being greater than or equal to two, to the controlled device via the data line. Each bit of said control signals is latched onto the controlled device on consecutive edges of a clock signal sent by the controller device to the controlled device on the clock line.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: September 11, 2007
    Assignee: EM Microelectronic-Marin SA
    Inventors: Daniel A Staver, Bruce Carl Wall, Tue Tran
  • Patent number: 7266462
    Abstract: A system, method and computer program for configuring power supply apparatus to supply a voltage optimized to tolerate a range about a nominal operating voltage of a device comprises a tester to test and communicate to a comparator a present utility voltage value. The comparator compares the present utility voltage with a present nominal operating voltage of the device. A configurator responds to the present utility voltage falling within an upper half of a first range having a centre point higher than the present nominal operating voltage and lower than an upper out-of-tolerance voltage of the device or within a lower half of a second range having a centre point lower than the present nominal operating voltage and higher than a lower out-of-tolerance voltage of the device, by configuring the power supply apparatus to supply a voltage respectively within the first range or the second range.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: September 4, 2007
    Assignee: International Business Machines Corporation
    Inventor: Paul Jonathan Quelch
  • Patent number: 7224153
    Abstract: A power regulator has an output for regulated power that is connected to supply power to a load. The load can have various electrical characteristics, including requiring a rapid transient response. The transient response amplitude for the power regulator is decreased by adding capacitance at the output, but that slows the response time of the power regulator by lowering the crossover frequency and the phase margin at the crossover frequency. An adjustable gain element imbedded in the feedback network provides an input to permit a builder or user of the power regulator to vary the effective value of impedance elements in the feedback network. The builder or user selectively connects an impedance to the input of the adjustable gain element to thereby adjust the frequency characteristics of the feedback network to thereby adjust output characteristics of the power regulator to compensate for the effects of capacitance added to the power regulator output.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: May 29, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Charles Allen DeVries, Jr., Joseph Gerard Renauer, Michael G. Amaro
  • Patent number: 7196570
    Abstract: Fuse circuit designs and the use thereof are disclosed. In one example, a fuse circuit providing predictable total resistances for multiple rounds of programming comprises a predetermined number of fuse stages coupled in series. Each stage comprises a first and a second connecting nodes, a fuse connected between the first and second connecting nodes, a first resistor with its first end connected to the first connecting node, and a second resistor with its first end connected to the second connecting node, wherein the first and second resistors connect to a third and a fourth connecting nodes, which are the first and second connecting nodes of a next fuse stage respectively, through their second ends.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: March 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shine Chien Chung
  • Patent number: 7173408
    Abstract: An adjustable regulated power device includes, for example, an electronic potential device, a regulated device and a control device. The electronic potential device includes an electronic potentiometer having a plurality of potentiometers. The regulated device includes a voltage regulator connected to an input power and at least one first potentiometer of the potentiometers. The first potentiometer forms a variable resistor used for adjusting an output voltage from the voltage regulator. The control device includes a microprocessor and a control input device used for receiving an input setting value. The microprocessor is connected to the control input device and the electronic potentiometer for receiving the setting value and controlling the electronic potentiometer according to the setting value.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: February 6, 2007
    Assignee: Winbond Electronics Corp.
    Inventor: Guang-Jian Huang
  • Patent number: 7071669
    Abstract: A reference voltage generation circuit includes first to third resistance ladder circuits. The first resistance ladder circuit has at least one variable resistance circuit in which a resistance value between both ends is variable, and outputs multi-valued reference voltages. The second resistance ladder circuit has series-connected resistance circuits each of which has a fixed resistance value, and outputs a plurality of reference voltages. The third resistance ladder circuit has at least one variable resistance circuit in which a resistance value between both ends is variable, and outputs multi-valued reference voltages. The first to third resistance ladder circuits are connected in series between first and second power supply lines. The resistance values of the variable resistance circuits in the first and third resistance ladder circuits are variably controlled by a given command or a variable control signal input through an external input terminal.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: July 4, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Akira Morita
  • Patent number: 7005837
    Abstract: A digital potentiometer is disclosed that includes first, second, and third signal terminals. A chain of series-connected impedance elements with multiple tap points is connected between the first and second signal terminals. A plurality of first switching devices are each connected to a respective one of the multiple tap points and to an internal wiper node. A configurable output stage is connected between the internal wiper node and the third signal terminal. The configurable output stage includes a buffer and a second switching device. The second switching device is operable to bypass the buffer. A switching circuit controls switching of the first switching devices. The switching circuit includes a Gray-code counter, a Gray-code decoder, and a make-before-break circuit that controls the timing of the switching of the wiper switches.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: February 28, 2006
    Assignee: Catalyst Semiconductor, Inc.
    Inventors: Cornel D. Stanescu, Adrian M. Tache, Horia Profeta, Radu H. Iacob, Adam P. Cosmin
  • Patent number: 6949918
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: September 27, 2005
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Michael W. Morrow, Gregory B. Tucker, Yuan-Po Ypt Tseng, Ali Minaei, Jay Heeb
  • Patent number: 6922046
    Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: July 26, 2005
    Assignee: Winbond Electronics Corporation
    Inventors: Chun-Mai Liu, Hagop A. Nazarian
  • Patent number: 6917190
    Abstract: A power supply apparatus includes an output voltage generator, a reference voltage generator, a voltage divider, and a voltage control circuit. An input voltage is supplied from a direct current power source. The output voltage generator generates a constant output voltage based on the input voltage. The reference voltage generator generates a reference voltage. The voltage divider divides the constant output voltage into a divided voltage in accordance with a voltage dividing ratio variable in response to an externally-input control signal. The voltage control circuit controls the output voltage generator to regulate the constant output voltage such that the divided voltage from the voltage divider is equalized to the reference voltage.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: July 12, 2005
    Assignee: Ricoh Company, Ltd.
    Inventors: Masahiro Matsuo, Shoichi Nitta, Ritsuko Nomura
  • Patent number: 6882136
    Abstract: An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance element is connected in series in a mirrored configuration about the center impedance element.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: April 19, 2005
    Assignee: Winbond Electronics Corporation
    Inventors: Hagop A. Nazarian, William Tang, Zhan Duan, Chao-Ming Tsai, Lawrence D. Engh
  • Patent number: 6882943
    Abstract: A system, method and computer program for configuring power supply apparatus to supply a voltage optimized to tolerate a range about a nominal operating voltage of a device comprises a tester to test and communicate to a comparator a present utility voltage value. The comparator compares the present utility voltage with a present nominal operating voltage of the device. A configurator responds to the present utility voltage falling within an upper half of a first range having a centre point higher than the present nominal operating voltage and lower than an upper out-of-tolerance voltage of the device or within a lower half of a second range having a centre point lower than the present nominal operating voltage and higher than a lower out-of-tolerance voltage of the device, by configuring the power supply apparatus to supply a voltage respectively within the first range or the second range.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: April 19, 2005
    Assignee: International Business Machines Corporation
    Inventor: Paul Jonathan Quelch
  • Publication number: 20040217751
    Abstract: An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance elements is connected in series in a mirrored configuration about the center impedance element.
    Type: Application
    Filed: May 26, 2004
    Publication date: November 4, 2004
    Inventors: Hagop A. Nazarian, William Tang, Zhan Duan, Chao-Ming Tsai, Lawrence D. Engh
  • Publication number: 20040196020
    Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.
    Type: Application
    Filed: April 2, 2004
    Publication date: October 7, 2004
    Inventors: Chun-Mai Liu, Hagop A. Nazarian
  • Patent number: 6788042
    Abstract: An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance elements is connected in series in a mirrored configuration about the center impedance element.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: September 7, 2004
    Assignee: Winbond Electronics Corporation
    Inventors: Hagop A. Nazarian, William Tang, Zhan Duan, Chao-Ming Tsai, Lawrence D. Engh
  • Patent number: 6771053
    Abstract: A digital potentiometer, configurable and programmable using nonvolatile memory is disclosed. A unity-gain configured, rail-to-rail operational amplifier, used as voltage follower of buffer, can be inserted, by programming, between an internal wiper terminal and an output terminal of the digital potentiometer. This way, in certain applications, it is possible to take advantage of the low output resistance given by an analog buffer. The operational amplifier can be shutdown and bypassed by a switching device to provide a circuit behavior similar to a digital potentiometer without an output buffer. Using a dual-writing circuitry, first the complemented data, then the data itself, are written in the nonvolatile memory, improving the reliability. A Gray-code counter having a single bit changed at one time and no decode glitch is present. A make-before-break circuitry gives a short overlap conduction time for any adjacent pair of switches; one being turned-off while the other is turned-on.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: August 3, 2004
    Assignee: Catalyst Semiconductor, Inc.
    Inventors: Cornel D. Stanescu, Adrian M. Tache, Horia Profeta, Radu H. Iacob, Adam P. Cosmin
  • Patent number: 6744244
    Abstract: An impedance network. The network includes a plurality of impedance elements, at least one end terminal, and a wiper terminal. The network also includes a first plurality of switching elements selectively providing tap positions to the at least one end terminal, selectable at a first specified increment of impedance elements in the plurality of impedance elements. The network further includes a second plurality of switching elements selectively providing a tap positions to the wiper terminal, selectable at a second specified increment of impedance elements in the plurality of impedance elements.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: June 1, 2004
    Assignee: Winbond Electronics Corporation
    Inventors: Chun-Mai Liu, Hagop A. Nazarian
  • Patent number: 6664775
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: December 16, 2003
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Michael W. Morrow, Gregory B. Tucker, Yuan-Po Ypt Tseng, Ali Minaei, Jay Heeb
  • Patent number: 6614210
    Abstract: A system includes a processor and a flash memory block that may receive an operating voltage potential sufficient for reading a memory cell. A Power-Supply-In-Package (PSIP) block may adjust a supply voltage in accordance with received data values and be used to power the flash memory block.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: September 2, 2003
    Assignee: Intel Corporation
    Inventors: Rajesh Sundaram, Jahanshir J. Javanifard
  • Publication number: 20030155902
    Abstract: A digital potentiometer, configurable and programmable using nonvolatile memory is disclosed. A unity-gain configured, rail-to-rail operational amplifier, used as voltage follower of buffer, can be inserted, by programming, between an internal wiper terminal and an output terminal of the digital potentiometer. This way, in certain applications, it is possible to take advantage of the low output resistance given by an analog buffer. The operational amplifier can be shutdown and bypassed by a switching device to provide a circuit behavior similar to a digital potentiometer without an output buffer. Using a dual-writing circuitry, first the complemented data, then the data itself, are written in the nonvolatile memory, improving the reliability. A Gray-code counter having a single bit changed at one time and no decode glitch is present. A make-before-break circuitry gives a short overlap conduction time for any adjacent pair of switches; one being turned-off while the other is turned-on.
    Type: Application
    Filed: February 20, 2002
    Publication date: August 21, 2003
    Inventors: Cornel D. Stanescu, Adrian M. Tache, Horia Profeta, Radu H. Iacob, Adam P. Cosmin
  • Publication number: 20030111992
    Abstract: An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance elements is connected in series in a mirrored configuration about the center impedance element.
    Type: Application
    Filed: March 20, 2002
    Publication date: June 19, 2003
    Inventors: Hagop A. Nazarian, William Tang, Zhan Duan, Chao-Ming Tsai, Lawrence D. Engh
  • Patent number: 6555996
    Abstract: Disclosed are solid-state potentiometers having high resolution and high accuracy. An exemplary potentiometer comprises a first main terminal, a second main terminal, a wiper terminal, and a resistor stack comprising a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes. Each of the resistors in the stack has substantially the same value of RS ohms. The potentiometer further comprises a first variable resistance network coupled between one end of the resistor stack and the potentiometer's first main terminal, and a second variable resistance network coupled between the other end of the resistor stack and the potentiometer's second main terminal. The first variable resistance network has a variable resistance value R1 which varies between zero ohms and RP ohms. The second variable resistance network has a variable resistance value R2 which is maintained substantially at value of (RP−R1).
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: April 29, 2003
    Assignee: Xicor, Inc.
    Inventors: Joseph Drori, Allan Ming-Lun Lin
  • Patent number: 6552519
    Abstract: A variable impedance network for the use in building potentiometers and digital-to-analog converters (DAC) is disclosed. The impedance network is constructed such that it reduces the overhead circuits associated with it compared to conventional approach. The percent reduction of overhead circuitry including the wiper transistors increases exponentially as the number of the taps required for the potentiometer increases.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: April 22, 2003
    Assignee: Winbond Electronics Corporation
    Inventor: Hagop A. Nazarian