Environmental Control Patents (Class 324/750.14)
  • Patent number: 11631470
    Abstract: A semiconductor chip may include a memory, a power supply line, a noise generator and a switch. The power supply line may include first and second power supply line portions. The power supply line may be configured to provide a power supply signal through each of the first power supply line portion and the second power supply line portion. The noise generator may be connected to the second power supply line portion. The noise generator may be configured to receive the power supply signal from the second power supply line portion, and output a noisy power supply signal based on the power supply signal. The switch may be coupled to the memory, the first power supply line portion, and the noise generator. The switch may be configured to selectively electrically connect the memory to one of the first power supply line portion and the noise generator.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: April 18, 2023
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Szu Huat Goh, Shaalini Sivaramakrishnan, Li Song, Wei Fong Soh
  • Patent number: 11614483
    Abstract: A test apparatus and an automatic test equipment having the same are disclosed. The test apparatus includes a test head having a test area, a socket board combined to the test area of the test, the socket board including a socket body and an active device attached on a first surface of the socket body, the active device configured to operate a semiconductor package, and a heat exchanger arranged on an upper portion of the test head, the heat exchanger being in contact with the socket board.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: March 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dahm Yu, Hyunmin Kwon, Jaehyun Kim
  • Patent number: 11513138
    Abstract: Provided is a semiconductor inspection device capable of high-speed response analysis as defect analysis of a fine-structured device constituting an LSI. Therefore, the semiconductor inspection device includes a vacuum chamber 3, a sample table 4 which is disposed in the vacuum chamber and on which a sample 6 is placed, an electron optical system 1 disposed such that an electron beam is emitted from above the sample, a plurality of probe units 24 connected to external devices 11 and 12 disposed outside the vacuum chamber via a coaxial cable 10, and an electrode 5 provided on or in the vicinity of the sample table. The probe unit 24 includes a measurement probe 8 configured to come into contact with the sample, a GND terminal 9 configured to come into contact with the electrode 5, and a probe holder 7 configured to hold the measurement probe and the GND terminal, connect a signal line of the coaxial cable to the measurement probe, and connect a GND line of the coaxial cable to the GND terminal.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 29, 2022
    Assignee: Hitachi High-Tech Corporation
    Inventors: Masaaki Komori, Katsuo Oki
  • Patent number: 11360115
    Abstract: An inspection system configured to inspect a device within a substrate is provided. The inspection system includes an inspection module, an alignment module, a supporting device and a fixing device. The inspection module has multiple testers and multiple inspection chambers. The multiple testers are allowed to be accommodated in the multiple inspection chambers, respectively. The alignment module has an aligner. The aligner is placed in an alignment space. The aligner is configured to adjust a position of the substrate to be inspected with respect to one tester of the multiple testers, which is accommodated in the alignment space. The supporting device is configured to support the tester accommodated in the alignment space from below. The fixing device is configured to fix the tester accommodated in the alignment space in cooperation with the supporting device.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 14, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takanori Hyakudomi, Jun Fujihara, Hiroaki Sakamoto, Tomoya Endo, Xingjun Jiang
  • Patent number: 11215660
    Abstract: The disclosed computer-implemented method may include providing test signals from a panel test board included in a fixture to a device under test included in a carrier including providing interface signals from the panel test board to a connector included on a fixture interposer block included in the fixture, interfacing the connector on the fixture interposer block with one or more pogo pins included on a panel interposer board included in the carrier, the interfacing providing the interface signals as inputs to a re-timer circuit included on the panel interposer board, generating, by the re-timer circuit, output interface signals whose signal strength is greater than a signal strength of the interface signals input to the re-timer circuit, and providing the interface signals output from the re-timer circuit to the device under test. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: January 4, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Ye Yin, Rui Zhang
  • Patent number: 11215641
    Abstract: Probe pin arrangements in a vertical-type probe card assembly for an automated test equipment (ATE) are disclosed. In some embodiments, one or more additional conductive regions are provided in between adjacent probe pins. The additional conductive regions may reduce spacing between probe pins connected to adjacent probe card pads, and may in turn reduce or adjust inductance between the two probe cards pads to provide improved signal impedance matching or lower power impedance. In one embodiment, the additional conductive region is a short probe pin. In another embodiment, the additional conductive region is a protrusion on a vertical probe pin.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: January 4, 2022
    Assignee: Teradyne, Inc.
    Inventor: Brian Brecht
  • Patent number: 11199578
    Abstract: A testing apparatus for testing an integrated circuit package having a plurality of electrical terminals includes a base, a socket, a plurality of conductive pins and a plurality of conductive pillars. The base includes a plurality of electrical contacts. The socket is disposed on the base and includes a bended portion bended away from the base and a plurality of through holes distributed in the socket. The conductive pins are disposed in the through holes respectively and electrically connected to the electrical contacts, wherein each of the conductive pins protrudes from an upper surface of the socket for forming temporary electrical connections with one of the electrical terminals. The conductive pillars are disposed on the base and connected to the bended portion, wherein each of the conductive pillars electrically connects one of the conductive pins and one of the electrical contacts.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tang-Jung Chiu, Hung-Chih Lin, Mill-Jer Wang
  • Patent number: 11181574
    Abstract: The present invention provides a testing device for electrically testing integrated circuits on a wafer. The testing device comprises a vacuum chamber, a chuck for holding the wafer, a probe card for electrically contacting the integrated circuits, means for moving the chuck relative to the probe card, a first radiation shield arranged inside the vacuum chamber and enclosing the chuck and the probe card, and a cooling unit thermally connected to the first radiation shield. The means for moving the chuck relative to the probe card comprises a supporting column having a first end and a second end, the first end of the supporting column being attached to the chuck, and the first radiation shield comprises a first fixed part having a first aperture through which the supporting column is arranged to pass, and a first movable part that is attached to the supporting column and arranged to cover the first aperture.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 23, 2021
    Assignees: Afore Oy, Bluefors Cryogenics Oy
    Inventors: Aki Junes, Ari Kuukkala, Timo Salminen, Vesa Henttonen, Matti Manninen, David Gunnarsson, Leif Roschier
  • Patent number: 11035899
    Abstract: The present disclosure relates to a detection system, and, more particularly, to system for detection of passive voltage contrast and methods of use. The system includes a chamber; a stage provided within the chamber, configured to stage a target structure; an electron beam apparatus which is structured to emit an e-beam toward the stage; and a laser source which emits a laser signal toward the stage, at a same area as the e-beam.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 15, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Changqing Chen, Fransiscus X. G. Rivai, Choon Seng Adrian Ng, Kay Guan Chia
  • Patent number: 10901028
    Abstract: Provided is a substrate inspection method capable of accurately performing inspection. A wafer inspection device includes a chuck top on which a wafer having a semiconductor device formed thereon is mounted and a probe card disposed above the chuck top so as to face the chuck top. The probe card includes a plurality of contact probes protruding toward the wafer. When bringing the chuck top close to the probe card, a tubular expandable/contractible bellows extending downward from the probe card side so as to surround the contact probes is attracted to the chuck top via a lip seal before the contact probes come into contact with the semiconductor device.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 26, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroshi Yamada, Jun Fujihara
  • Patent number: 10707652
    Abstract: An example method includes stacking a plurality of laser diode bars proximate an alignment plate. Each respective laser diode bar has a front edge through which the respective laser diode bar emits light. The alignment plate has a first side that provides a common plane for aligning the front edges of the laser diode bars and a second side opposite the first side. The alignment plate has a plurality of microholes extending between the first and second sides. The method also includes applying suction to the plurality of laser diode bars through the plurality of microholes. The suction draws the front edges of the laser diode bars against the first side of the alignment plate such that the front edges of the laser diode bars are aligned in the common plane. Conductive plates used to clamp the plurality of laser diodes therebetween may be aligned in a similar fashion.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 7, 2020
    Assignee: Waymo LLC
    Inventors: Augusto Tazzoli, Pierre-Yves Droz, Nathaniel Golshan
  • Patent number: 10620236
    Abstract: A probe card for testing dies of a substrate during a wafer sort process includes a printed circuit board (PCB) and a test site arranged to connect respectively to one of the dies during a test cycle. The test site includes a first pin connecting band and a first pin set. The first pin connecting band is connected to the PCB. The first pin set is connected to the first pin connecting band and includes a pin configuration for a testing device to perform a first type of test on a first die. The test site includes only pins in the first pin set. A number of pins in the first pin set is less than a number of pins used to perform a second type of test on the first die. The second type of test is performed at a slower processing speed than the first type of test.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: April 14, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: David Ganapol, Michael Gonia, Scott Wu, Marc Jacobs
  • Patent number: 10622087
    Abstract: In example implementations, an integrated characterization vehicle is provided. The integrated characterization vehicle includes a memristor, a configuration cache and an analog measurement tile. The memristor has a driving unit to limit an amount of current that is driven through the memristor during testing. The configuration cache provides test parameters to control the testing of the memristor. The analog measurement tile provides a voltage to the memristor in accordance with the test parameters and to record a response of the memristor.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jeffrey Alan Lucas, Tommy Miles, James Ignowski, William L. Wilson, Richard H. Henze
  • Patent number: 10510564
    Abstract: A system for controlling temperature of a substrate, which is arranged on a substrate support assembly, includes first and second sources to respectively supply a fluid at first and second temperatures at a fixed flow rate. First and second three-way proportional valves receive the fluid from the first and second sources, mix first portions of the received fluid to supply the fluid having a predetermined temperature to the substrate support assembly at a predetermined flow rate, and return second portions of the received fluid to the first and second sources. A third three-way proportional valve receives the fluid from the substrate support assembly and returns the received fluid to the first and second sources. A controller controls the first and second valves to supply the fluid to the substrate support assembly and controls the third valve to divide the fluid between the first and second sources.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: December 17, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventor: Alexander Charles Marcacci
  • Patent number: 10488852
    Abstract: The invention relates to a method for regulating the operation of an electromechanical apparatus (1), for example an EBM apparatus, in order to obtain certified processed products, wherein it is provided an initial calibration step that is intended to check the proper functioning of all the component parts of the apparatus (1) structured to ensure the complete functionality and a subsequent quality control step carried out on the obtained products by the carried out working process.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: November 26, 2019
    Assignee: LIMACORPORATE S.P.A.
    Inventors: Michele Pressacco, Marco Regis
  • Patent number: 10361656
    Abstract: The present invention uses a power supply to splay a forward bias to a concentrating solar cell. Then the solar cell will emit red light (electroluminescence). After passing the secondary optical device packaged on the solar cell, the red light will exhibit specific light distribution. According to the light distribution, the accuracy of the packaging location of the solar cell, the forming precision of the secondary optical device, and whether the optical devices are defective can be examined.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: July 23, 2019
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.O.C.
    Inventors: Chun-Yi Chen, Yueh-Mu Lee, Hwen-Fen Hong
  • Patent number: 10281487
    Abstract: Apparatus for facilitating analytical probing of a packaged electronic device is provided. The device may provide a test chamber that holds the device to be tested and provides an elevated or reduced temperature environment to conduct testing of the device at end-use application temperature levels. The apparatus includes a test chamber having perimeter walls and a configurable cover. The cover includes an adjustable position probe entry port or aperture that may be positioned to provide probe access to any point within the test chamber, and may comprise a cover with such positionable port or a plurality of overlapping plates such as a first plate with a cutout quadrant that can be oriented to expose any quadrant of the test chamber and a second plate with at least one probe entry port that can be situated in the cutout to provide the probe entry port above a desired test area of the electronic device.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: May 7, 2019
    Assignee: The Micromanipulator Company, LLC
    Inventors: Michael Stanley Jackson, Clint Andrew Waggoner
  • Patent number: 10281492
    Abstract: Shielded probe systems are disclosed herein. The shielded probe systems are configured to test a device under test (DUT) and include an enclosure that defines an enclosure volume, a translation stage with a stage surface, a substrate-supporting assembly extending from the stage surface, an electrically conductive shielding structure, an isolation structure, and a thermal shielding structure. The substrate-supporting assembly includes an electrically conductive support surface, which is configured to support a substrate that includes the DUT. The electrically conductive shielding structure defines a shielded volume. The isolation structure electrically isolates the electrically conductive shielding structure from the enclosure and from the translation stage. The thermal shielding structure extends within the enclosure volume and at least partially between the enclosure and the substrate-supporting assembly.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 7, 2019
    Assignee: FormFactor Beaverton, Inc.
    Inventors: Michael Teich, Karsten Stoll, Walter Matthias Clauss, Swen Schmiedchen
  • Patent number: 10175266
    Abstract: A wafer level electrical probe system with multiple wavelength and intensity illumination capability system that enables concurrent reliability studies of illumination stimulation, electrical stimulation, and the interplay of both electrical and illumination stimulation. The probe system includes five sub-systems: a controllable wavelength and intensity illumination input sub-system with two different configurations; a wafer level electrical probe sub-system; an illumination intensity calibration sub-system; an illumination delivery sub-system; and an illumination wavelength calibration sub-system.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: January 8, 2019
    Assignee: The United States of America as Represented by the Secretary of the Army
    Inventors: Jeffrey J. Siddiqui, Ajit Sandhu, Joe Y. Liu
  • Patent number: 10170893
    Abstract: An example method includes stacking a plurality of laser diode bars proximate an alignment plate. Each respective laser diode bar has a front edge through which the respective laser diode bar emits light. The alignment plate has a first side that provides a common plane for aligning the front edges of the laser diode bars and a second side opposite the first side. The alignment plate has a plurality of microholes extending between the first and second sides. The method also includes applying suction to the plurality of laser diode bars through the plurality of microholes. The suction draws the front edges of the laser diode bars against the first side of the alignment plate such that the front edges of the laser diode bars are aligned in the common plane. Conductive plates used to clamp the plurality of laser diodes therebetween may be aligned in a similar fashion.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: January 1, 2019
    Assignee: Waymo LLC
    Inventors: Augusto Tazzoli, Pierre-Yves Droz, Nathaniel Golshan
  • Patent number: 10060950
    Abstract: Shielded probe systems are disclosed herein. The probe systems are configured to test a device under test (DUT) and include a measurement chamber that at least partially bounds an enclosed volume, an aperture defined by the measurement chamber, a probing assembly, and a shielding structure. The probing assembly includes a probe, which is oriented within the enclosed volume, a probe arm, which is operatively attached to the probe, and a manipulator, which is operatively attached to the probe arm. At least a portion of the probing assembly extends through the aperture. The shielding structure extends between the measurement chamber and the probing assembly and is configured to restrict fluid flow through the aperture and shield the enclosed volume from an ambient environment that surrounds the measurement chamber while maintaining at least a threshold separation distance from the probe arm throughout a probe arm range-of-motion thereof.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: August 28, 2018
    Assignee: FormFactor Beaverton, Inc.
    Inventors: Michael E Simmons, Bryan Conrad Bolt, Christopher Anthony Storm, Kazuki Negishi, Joseph George Frankel, Robbie Ingram-Goble
  • Patent number: 10025202
    Abstract: Methods, systems, and apparatus for the loading and unloading of substrates, such as semiconductor wafers, involving microlithography and similar nano-fabrication techniques. The system includes two or more pedestals; a substrate chuck including two or more channels; a turntable having a top surface and a first end positioned opposite a second end, each of the first and second ends including a respective opening, each opening including two or more cutouts and two or more tabs, the turntable rotatable between first and second positions and an actuator system to adjust distances between the turntable and the substrate chuck and between the turntable and the pedestals.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 17, 2018
    Assignee: Molecular Imprints, Inc.
    Inventors: Roy Patterson, Christopher John Fleckenstein, Matthew S. Shafran, Charles Scott Carden, Satish Sadam, Ryan Christiansen
  • Patent number: 10006961
    Abstract: In a transfer method for transferring a substrate in an inspection system configured to perform a test on electrical characteristics of the substrate, the inspection system including an inspection unit including a plurality of test devices configured to perform the test on the electrical characteristics of a substrate, a loader unit configured to mount a cassette which accommodates a plurality of substrates, and a transfer device configured to transfer a substrate between the inspection unit and the loader unit, an inspected substrate is received by the transfer device from the inspection unit. The inspected substrate received from the inspection unit is transferred toward the loader unit in a state where an opening portion of a transfer arm container of the transfer device. Then, the inspected substrate is delivered to the loader unit.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: June 26, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Hosaka, Masahiko Akiyama
  • Patent number: 10006940
    Abstract: Reliability of an electrical test of a semiconductor wafer is improved. A method of manufacturing a semiconductor device includes a step of performing an electrical test of a semiconductor element by allowing contact portions (tips) of a force terminal (contact terminal) and a sense terminal (contact terminal) held by a probe card (first card) to come into contact with an electrode terminal of a semiconductor wafer. In the step of performing the electrical test, the contact portions of the force terminal and the sense terminal move in a direction away from each other after coming into contact with the first electrode terminal.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 26, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Saito
  • Patent number: 9939386
    Abstract: The disclosure is directed to systems and methods for sample inspection and review. In some embodiments, images are collected and/or defects are located utilizing separately addressable red, green, and blue (RGB) illumination sources to improve image quality. In some embodiments, illumination sources are pulse width modulated for substantially consistent light intensity in presence of variable sample motion. In some embodiments, a stage assembly is configured to support the sample without blocking access to the supported surface of the sample, and further configured to reduce oscillations or vibrations of the sample. In some embodiments, an illumination system includes an imaging path and a focusing path to allow full field of view focusing.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 10, 2018
    Assignee: KLA—Tencor Corporation
    Inventors: Isabella T. Lewis, Yakov Bobrov
  • Patent number: 9921268
    Abstract: A test probe aligner for aligning a test probe card with devices under test of a wafer is provided. The test probe aligner includes a backer plate arranged with its bottom side to the test probe card, and a stiffener mounted to the test probe card outside a horizontal dimension of the backer plate. The stiffener and a top side of the backer plate end in a same plane above the test probe card. The alignment further includes a bridge beam locked to a top side of the stiffener. Furthermore, the test probe aligner also includes at least two actuators and at least two corresponding force measurement sensors below a top surface of the bridge beam, arranged such that forces are applicable to the test probe card.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eberhard Dengler, Gabriele Kuczera, Eckhard Kunigkeit, Siegfried Tomaschko, Quintino Lorenzo Trianni
  • Patent number: 9835694
    Abstract: Methods and configuration are disclosed for providing higher magnetic sensitivity magnetometers through fluorescence manipulation by phonon spectrum control. A method for increasing the magnetic sensitivity for a DNV sensor may include providing a diamond having nitrogen vacancies of a DNV sensor and an acoustic driver and acoustically driving the diamond with the acoustic driver to manipulate a phonon spectrum of the DNV sensor. A DNV sensor may include a diamond having nitrogen vacancies, a photo detector configured to detect photon emissions from the diamond responsive to laser excitation of the diamond and an acoustic driver configured to manipulate a phonon spectrum for the DNV sensor by acoustically driving the diamond.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: December 5, 2017
    Assignee: Lockheed Martin Corporation
    Inventors: David N. Coar, Jeff D. Cammerata
  • Patent number: 9784763
    Abstract: Shielded probe systems are disclosed herein. The shielded probe systems are configured to test a device under test (DUT) and include an enclosure that defines an enclosure volume, a translation stage with a stage surface, a substrate-supporting stack extending from the stage surface, an electrically conductive shielding structure, an isolation structure, and a thermal shielding structure. The substrate-supporting stack includes an electrically conductive support surface and a temperature-controlled chuck. The electrically conductive shielding structure defines a shielded volume. The isolation structure electrically isolates the electrically conductive shielding structure from the enclosure and from the translation stage. The thermal shielding structure extends within the enclosure volume and at least partially between the enclosure and the substrate-supporting stack.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: October 10, 2017
    Assignee: Cascade Microtech, Inc.
    Inventors: Michael Teich, Karsten Stoll, Walter Matthias Clauss, Swen Schmiedchen
  • Patent number: 9369085
    Abstract: In an example embodiment, an apparatus includes an LC circuit having a capacitive circuit and an inductive circuit connected in a circuit loop. The inductive circuit includes one or more inductive elements and a switching circuit. In a first mode, the switching circuit provides a direct-current charge voltage across the LC circuit and prevents oscillation of energy between the capacitive circuit and the inductive circuit by opening a switch in the circuit loop of the LC circuit. In a second mode, the switching circuit enables oscillation of energy between the capacitive circuit and the inductive circuit by closing the switch in the circuit loop.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: June 14, 2016
    Assignee: NXP B.V.
    Inventors: Frank Leong, Yuan Gao, Robert Bogdan Staszewski
  • Patent number: 9310431
    Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ling Liu, Nan-Hsin Tseng, Ji-Jan Chen, Wei-Pin Changchien, Samuel C. Pan
  • Patent number: 9153649
    Abstract: A semiconductor layer with a low density of trap states is provided. A transistor with stable electrical characteristics is provided. A transistor having high field-effect mobility is provided. A semiconductor device including the transistor is provided. A method for evaluating a semiconductor layer is provided. A method for evaluating a transistor is provided. A method for evaluating a semiconductor device is provided. Provided is, for example, a semiconductor layer with a low defect density which can be used for a channel formation region of a transistor, a transistor including a semiconductor layer with a low defect density in a channel formation region, or a semiconductor device including the transistor.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: October 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hiroshi Kanemura, Yasuharu Hosaka, Shuhei Yokoyama, Toshimitsu Obonai
  • Publication number: 20150145540
    Abstract: Provided are a semiconductor inspection system and a method for preventing condensation at an interface part. The inspection system is characterized by being equipped with: a probe apparatus configured to bring a probe into contact with a target object whose temperature is controlled so that the probe is electrically connected with the target object; a tester configured to inspect the target object by supplying an inspection signal to the target object and detect an output signal outputted from the target object; an interface part which electrically connects the probe with the tester; a vacuum seal mechanism configured to seal the interface part in an airtight state; a gas exhaust unit configured to evacuate the interior of the interface part to a depressurized atmosphere; and a dry gas supply unit configured to supply a dry gas into the evacuated interface part while controlling a flow rate of the dry gas.
    Type: Application
    Filed: June 18, 2013
    Publication date: May 28, 2015
    Inventors: Shigekazu Komatsu, Takaaki Hoshino
  • Publication number: 20150109010
    Abstract: An electrostatic discharge (ESD) test apparatus includes a chamber with a supporting plate, a test bench mounted on the supporting plate, a first supporting bracket, a camera installed in the chamber, and a control apparatus. The first supporting bracket includes a first rail mounted on the supporting plate, a supporting pole movably connected to the first rail, a first adjusting pole movably installed to the supporting pole, an ESD gun rotatably installed to the first adjusting pole, a first driving assembly driving the supporting pole, a second driving assembly driving the first adjusting pole, and a third driving assembly driving the ESD gun to rotate. The camera captures images and further transmits the images to the control apparatus. The control apparatus controls the first driving assembly, the second driving assembly, and the third driving assembly.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 23, 2015
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventor: Xiao-Lian HE
  • Patent number: 8988062
    Abstract: A branch circuit monitoring system (BCMS) for monitoring branch circuit currents in one or more electrical circuit panels is described. The system is comprised of a data center server, one or more panel processors, each with one or more collection devices, and one or more current sensors per collection device. The BCMS is designed to be installed entirely inside the panel without the need for a dedicated enclosure or power supply to facilitate ease of installation and low-cost. The BCMS also allows for future upgradability through standard software updates so that the system can be updated or patched easily. The BCMS data center server collects, aggregates, stores, and serves historical branch circuit current data from the panel processors to networked users via a web server to provide visualization of data such as tables, charts, and gauges.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 24, 2015
    Assignee: Precision Air & Energy Services, LLC
    Inventors: Montgomery J. Sykora, Daniel L. Janovy, David L. Janovy
  • Publication number: 20150054535
    Abstract: Provided is a probing testing apparatus of a semiconductor wafer with excellent repeatability and ease of maintenance. A gas injection port supplying oxidation preventing gas for preventing oxidation of a probe needle is provided on an inner side wall of a shielding structure mounted to a wafer probing stage within a prober so as to surround an outer side surface of a wafer. By allowing an oxidation preventing gas to flow to a part of the probe needle that is brought into contact with the wafer through an outer circumference and an upper surface of the wafer, a gas atmosphere around the probe needle is maintained by the oxidation preventing gas. With this configuration, since it is unnecessary to provide a spray nozzle above a probe card, position adjustment of the nozzle accompanying replacement of the probe card is not needed. Further, regardless of a configuration of the probe card, it is possible to blow the oxidation preventing gas even in a vertical-type probe card.
    Type: Application
    Filed: January 30, 2013
    Publication date: February 26, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Kohji Yoshioka
  • Patent number: 8917103
    Abstract: A testing method for testing a semiconductor device includes heating the semiconductor device until the temperature of the semiconductor device reaches a predetermined temperature; conducting other functional tests other than testing of the overheat protection function in a second step after the temperature of the semiconductor device has reached the predetermined temperature; allowing the semiconductor device to generate heat by itself such that the overheat protection function of the semiconductor device is activated, detecting a first diode forward voltage of a desired diode contained in the semiconductor device when the overheat protection function of the semiconductor device is activated and computing a first computational temperature of the semiconductor device based on the detected first diode forward voltage of the desired diode contained in the semiconductor device; and determining whether the computed first computational temperature of the semiconductor device resides in the overheat protection func
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 23, 2014
    Assignee: Ricoh Company, Ltd.
    Inventors: Koichi Morino, Kouichi Ikeda
  • Patent number: 8866505
    Abstract: A measurement apparatus for surface analysis carried out in a gaseous environment such as air comprises a measurement device capable of measuring a contact potential difference between a probe and a surface, and a light source that triggers photoelectric emission from a sample. The apparatus may operate in “dual” photoemission and contact potential difference (CPD) measurement modes.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: October 21, 2014
    Assignee: KP Technology Ltd.
    Inventor: Iain Baikie
  • Patent number: 8860445
    Abstract: A testing method for testing a semiconductor device includes heating the semiconductor device until the temperature of the semiconductor device reaches a predetermined temperature; conducting other functional tests other than testing of the overheat protection function in a second step after the temperature of the semiconductor device has reached the predetermined temperature; allowing the semiconductor device to generate heat by itself such that the overheat protection function of the semiconductor device is activated, detecting a first diode forward voltage of a desired diode contained in the semiconductor device when the overheat protection function of the semiconductor device is activated and computing a first computational temperature of the semiconductor device based on the detected first diode forward voltage of the desired diode contained in the semiconductor device; and determining whether the computed first computational temperature of the semiconductor device resides in the overheat protection func
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 14, 2014
    Assignee: Ricoh Company, Ltd.
    Inventors: Koichi Morino, Kouichi Ikeda
  • Patent number: 8854069
    Abstract: Production test of integrated circuit face thermal management challenges with higher power devices. Current production handlers do not have adequate thermal management characteristics. This invention employs thermal diodes on each device under test and a closed loop microprocessor controlled feedback system for thermal control during production test. The feedback system controls the open/close state of a valve supplying cooling fluid to bathe the integrated circuit based upon the difference between a temperature indicated by at least one thermal diode and a set point temperature.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph Shelton Mayfield, Nolan Riley, Chad Turner, Angelo Sanchez
  • Patent number: 8847586
    Abstract: A magnetic sensor inspection apparatus has a rectangular frame including a stage, a probe card, and a plurality of magnetic field generating coils. A wafer-like array of magnetic sensors is mounted on the stage, which is movable in horizontal and vertical directions. The probe card includes a plurality of probes which are brought into contact with a plurality of magnetic sensors encompassed in a measurement area. The magnetic field generating coils are driven to generate a magnetic field toward the stage. A plurality of magnetic field environment measuring sensors is arranged in the peripheral portion of the probe card surrounding the probes. A magnetic field controller controls magnetic fields generated by the magnetic field generating coils based on the measurement result of the magnetic field environment measuring sensors. Thus, it is possible to concurrently inspect a wafer-like array of magnetic sensors with the probe card.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: September 30, 2014
    Assignee: Yamaha Corporation
    Inventor: Takashi Suzuki
  • Patent number: 8836356
    Abstract: A vertical probe assembly includes an upper die; a lower die; a plurality of probes, the probes including an electrically conductive material, wherein the probes extend from the upper die through the lower die; and an air channel located between the upper die and the lower die, such that airflow through the air channel passes through the plurality of probes.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: David M. Audette, Dustin M. Fregeau, David L. Gardell, Daniel J. Murphy, Grant Wagner
  • Patent number: 8823408
    Abstract: An evaluation system 1 according to the present invention includes: a light source 2 for exposing a pulsed white light or a pulsed laser light onto a sample; a microwave exposing and detecting unit 8 for exposing a microwave onto an organic material 12 and for detecting the intensity of the microwave which has passed through the organic material 12; a microwave passing unit 7 for making the microwave pass through the organic material 12 a plurality of times; and an evaluating unit 10 for evaluating the photoelectric conversion characteristics of the sample based on the intensity of the microwave which has passed through the organic material 12 when the pulsed white light or the pulsed laser light is exposed and the intensity of the microwave which has passed through the organic material 12 when the pulsed white light or the pulsed laser light is not exposed.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 2, 2014
    Assignee: Japan Science and Technology Agency
    Inventors: Akinori Saeki, Shuhei Seki
  • Publication number: 20140210500
    Abstract: A semiconductor evaluating device includes a chuck stage for holding a semiconductor device serving as a measuring object, a contact probe for evaluating an electrical characteristic of the semiconductor device by getting contact with the semiconductor device held on the chuck stage, and a fluid spraying portion for spraying a fluid onto the semiconductor device.
    Type: Application
    Filed: October 28, 2013
    Publication date: July 31, 2014
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hajime AKIYAMA, Akira OKADA, Kinya YAMASHITA
  • Publication number: 20140184003
    Abstract: Systems and methods for rotational alignment of a device under test are disclosed herein. These systems include a chuck that includes a rotational positioning assembly that includes a lower section and an upper section that is configured to selectively rotate relative to the lower section about a rotational axis. The rotational positioning assembly further includes a first bearing that is configured to support a radial load between the upper section and the lower section and a second bearing that is configured to support a thrust load between the upper section and the lower section. The methods include providing a fluid stream to the second bearing to permit rotation of the upper section relative to the lower section, rotating the upper section relative to the lower section, and ceasing the providing the fluid stream to the second bearing to restrict rotation of the upper section relative to the lower section.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: CASCADE MICROTECH, INC.
    Inventors: Jorg Kiesewetter, Karsten Stoll
  • Patent number: 8766656
    Abstract: The present invention relates generally to a system and a method for thermal control. More particularly, the invention encompasses an apparatus for thermal control and management of at least one device under test (DUT). The inventive thermal control and management apparatus also allows for the management of a plurality of devices under test, and with each device under test having its own testing regimen. The thermal control and management of the device under test (DUT) is managed using at least one thermoelectric element or cooler (TEC), which can be used to either heat or cool the corresponding device under test (DUT).
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: July 1, 2014
    Assignee: Silicon Turnkey Solutions Inc.
    Inventors: Zafar Malik, David Jackson
  • Publication number: 20140176170
    Abstract: A test table including a chuck base, a flow guide mechanism and a dry air generator is provided. The chuck base includes a test area. The flow guide mechanism is disposed around the chuck base. The dry air generator connects to the flow guide mechanism for generating a dry air. The flow guide mechanism guides the dry air to flow toward the test area to cover the test area and the object to be tested and to create a dry environment to prevent dew condensation.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 26, 2014
    Applicant: CHROMA ATE INC.
    Inventors: Xin-Yi WU, Hsuan-Jen SHEN, Hung-Ta KAO
  • Publication number: 20140167799
    Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mill-Jer WANG, Ching-Nen PENG, Hung-Chih LIN, Hao CHEN
  • Publication number: 20140125368
    Abstract: An apparatus and method for increasing uniformity in light from a light source at a plurality of targets of the light include a plurality of movable aperture elements, locatable between the light source and the targets, each aperture element defining an aperture through which the light passes from the light source to an associated one of the plurality of targets associated with the aperture element along a longitudinal axis of the aperture element. A holder movably holds the plurality of aperture elements, each of the plurality of aperture elements being movable within the holder along the longitudinal axis of the aperture element to change a feature of light incident on the target associated with the aperture element.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Chih-Pin Jen, Ming-Chang Yang, Sheng-Kuai Yang
  • Patent number: 8717049
    Abstract: A system for testing a computer includes a single chip microcontroller (SCM), an environmental test chamber, and a control device connected to the SCM and the environmental test chamber. The SCM repeatedly switches the computer on and off and monitors the computer's response. The environmental test chamber accommodates the computer. The control device receives monitored data from the SCM and controls temperature and humidity in the environmental test chamber.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: May 6, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Ling-Yu Xie, Xing-Ping Xie
  • Patent number: 8610446
    Abstract: A testing device includes a pressure vessel, a mounting stand disposed in an internal space of the pressure vessel, on which a device to be tested is mounted, test electrodes, disposed in the internal space of the pressure vessel, that supply a test voltage to the device to be tested mounted on the mounting stand, and a pressurization unit that raises the pressure of the internal space of the pressure vessel. The test voltage is supplied from the test electrodes to the device to be tested mounted on the mounting stand, and testing of the device to be tested is carried out, in a condition that the pressure of the internal space of the pressure vessel is raised by the pressurization unit.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: December 17, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Atsushi Yoshida, Hiroyuki Toya, Toru Nishizawa, Seizo Uchiyama