Of Individual Circuit Component Or Element Patents (Class 324/537)
  • Patent number: 10837994
    Abstract: An electrical test device may include a power supply, a conductive probe element, and a spectral analysis block. The power supply may be connected to an external power source. The conductive probe element may be connected to the power supply and may be configured to be energized by the power supply. The probe element may be configured to be placed in contact with an electrical system under test and apply an input signal containing current for measuring at least one parameter of the electrical system. The spectral analysis block may be connected to the probe element and may be configured to receive an output signal from the electrical system in response to the application of the current to the electrical system. The spectral analysis block may be configured to analyze frequency spectra of the output signal and detect a broadband increase in energy of the frequency spectra above a predetermined energy threshold.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: November 17, 2020
    Assignee: Power Probe, Inc.
    Inventors: Jeff Whisenand, Randy Cruz
  • Patent number: 10838033
    Abstract: In one embodiment, a tester calibration device includes a first board to be installed on one of a plurality of sockets of a tester for testing a semiconductor device, when the tester is to be calibrated. The device further includes a plurality of first pins provided on a first face of the first board, and to be made contact with the one socket when the tester is to be calibrated. The device further includes a wiring configured to electrically connect some of the plurality of first pins with each other.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuhito Hayasaka
  • Patent number: 10782316
    Abstract: An integrated circuit device testing system includes a socket configured to receive an integrated circuit device, wherein the socket comprises at least one conductive trace made of a material with a resistivity that is a function of temperature, and wherein the socket is configured such that, when the integrated circuit device is located in the socket, the at least one conductive trace extends along a surface of the integrated circuit device. The integrated circuit device testing system further includes a controller or active circuit configured to determine a temperature at the surface of the integrated circuit device based on a measured resistance of the at least one conductive trace.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: September 22, 2020
    Assignee: DELTA DESIGN, INC.
    Inventor: Jerry Ihor Tustaniwskyj
  • Patent number: 10756538
    Abstract: A technique for operating a driver includes enabling the driver to provide a first current through a first terminal of a driver device of the driver in a first mode of operation. The method includes sensing a voltage drop across the first terminal and a second terminal of the driver device to generate a sensed voltage level indicative of the voltage drop. The method includes generating a comparison output signal indicative of a comparison of the sensed voltage level to a threshold voltage level. The method includes selectively enabling the driver to provide a second current in a second mode of operation based on the comparison output signal. The first current may be less than the second current. The enabling may include enabling a first portion of the driver device using a first control signal, while a second portion of the driver device is disabled using a second control signal.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: August 25, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Pranav R. Kaundinya, Sean A. Lofthouse
  • Patent number: 10753972
    Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 25, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Patent number: 10739418
    Abstract: A method of reading out a Hall plate which comprises at least 4 contacts. The method comprises: reading out two of the contacts while biasing two other contacts of the at least 4 contacts thereby obtaining a readout signal; switching biasing and readout contacts according to a random or pseudo-random sequence of phases, each phase corresponding with a different permutation of biasing and readout contacts selected from the at least 4 contacts of the Hall plate wherein the biasing and readout contacts are selected such that the readout signal is a measure for the magnetic field; processing of the readout signal to obtain a readout of the Hall plate representative for the magnetic field.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: August 11, 2020
    Assignee: Melexis Technologies SA
    Inventors: Johan Raman, Pieter Rombouts
  • Patent number: 10732219
    Abstract: An apparatus for testing semiconductor devices and a system including the same includes a socket unit having a plurality of sockets into which a plurality of semiconductor devices are inserted, respectively. Also included is a module unit including a first sub-module for receiving a test signal from a host and providing the same test signal to each of the plurality of sockets, and a second sub-module including the same structure as the first sub-module. The first sub-module includes a first buffer unit including an amplifier having an input terminal to which an input signal is inputted and an output terminal to amplify and output the input signal inputted based on a reference voltage (VT), and a reference resistor having one end connected to the input terminal of the amplifier and the other end to which the reference voltage is applied, and a second buffer unit including the same structure as the first buffer unit.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ki Jae Song
  • Patent number: 10733345
    Abstract: A method for automatically finding a verification test of a plurality of verification tests that were executed in a verification process of a design under test (DUT) that satisfies a criterion, may include using a processor, obtaining from a user a criterion that relates to one or more test actions; using a processor, obtaining a log with logged execution data that includes start and end times for each action of each of the tests of the plurality of verification tests during an execution run of that test; and for each test of the plurality of verification tests, using a processor, determining from the logged data whether that test satisfies the obtained criterion, and if a test of the plurality of verification tests was determined to satisfy the obtained criterion, using a processor, executing that test on the DUT.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 4, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Meir Ovadia, Matan Vax
  • Patent number: 10715123
    Abstract: Circuits and methods for correction of errors in multi-stage stepwise signal modification circuits. Embodiments of the invention also provide flexibility to correct accuracy errors over a range of conditions, such as differences in signal frequency and/or temperature. A first embodiment includes sorting actual values of a multi-stage stepwise signal modification circuit to generate a monotonic listing of actual values; mapping input codes to a new order of codes corresponding to the sorted actual values; and providing mapping functionality to convert each input code into a mapped output code. A second embodiment includes searching, for each ideal value corresponding to an input code, all actual values of a multi-stage stepwise signal modification circuit for the actual value closest to the ideal value; mapping input codes to a new order of codes corresponding to the closest actual values; and providing mapping functionality to convert each input code into a mapped output code.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 14, 2020
    Assignee: pSemi Corporation
    Inventor: Mark James O'Leary
  • Patent number: 10705938
    Abstract: An improved method for telecommunication analysis and monitoring employing a logic analyzer device. The logic analyzer device provides a plurality of concurrent graphic depictions of different electronic signals under differing electronic protocols for signal error determination on a communications channel. Error source determination is enabled through the provided concurrent depiction of digital and analog signal characteristics in the differing protocols, including digital data packets, signal voltages and timing. Through this concurrent depiction the user can visually discern potential causation for electronic communication errors caused by non-continuous signal anomalies affecting one or more of the protocols.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: July 7, 2020
    Inventor: David Webster
  • Patent number: 10679533
    Abstract: Methods and systems to provide baseline measurements for aging compensation for a display device are disclosed. An example display system has a plurality of active pixels and a reference pixel. Common input signals are provided to the reference pixel and the plurality of active pixels. The outputs of the reference pixel is measured and compared to the output of the active pixels to determine aging effects. The display system may also be tested applying a first known reference current to a current comparator with a second variable reference current and the output of a device under test such as one of the pixels. The variable reference current is adjusted until the second current and the output of the device under test is equivalent of the first current. The resulting current of the device under test is stored in a look up table for a baseline for aging measurements during the display system operation.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 9, 2020
    Assignee: Ignis Innovation Inc.
    Inventors: Gholamreza Chaji, Joseph Marcel Dionne, Yaser Azizi, Javid Jaffari, Abbas Hormati, Tong Liu, Stefan Alexander
  • Patent number: 10673223
    Abstract: An arc fault detection arrangement for a DC electric bus, the DC electric bus having one or more electric lines adapted to electrically connect a source section and a load section of an electric apparatus, the arc fault detection arrangement including an arc fault detector adapted to receive and process detection signals indicative of AC currents flowing along the electric lines.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 2, 2020
    Assignee: ABB Schweiz AG
    Inventors: Sauro Macerini, Mirco Mirra
  • Patent number: 10663505
    Abstract: A test system for performing a test on a device under test is provided. The test system comprises, at least one test device, configured for performing the test on the device under test, and at least one camera, configured for recording video data of the device under test and/or the at least one test device. Moreover, the test system comprises a storage unit, which is configured for storing the recorded video data and a video reproduction unit, which is configured for reproducing the recorded video. The video reproduction unit is moreover configured for reproducing the recorded video at an adjustable speed.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: May 26, 2020
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Doug Jones
  • Patent number: 10641819
    Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee
  • Patent number: 10613134
    Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 7, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Sigfredo E. Gonzalez Diaz, Benjamin Lee Amey, Patrick Michael Teterud, Hung Nguyen
  • Patent number: 10606329
    Abstract: An integrated circuit comprising: an input terminal configured to receive a failure-event-signal representative of a failure event; a first output terminal configured to provide a first-failure-signal; and a second output terminal configured to provide a second-failure-signal; and a processing block configured to: set the first-failure-signal based on the failure-event-signal; and set the second-failure-signal, at a predetermined time interval after the first-failure-signal is set. The processing block further comprises a switch configured selectively, based on a received digital-error-signal to either: set the second-failure-signal based on a digital-counter-output-signal; or set the second-failure-signal based on an analogue-trigger-signal.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 31, 2020
    Assignee: NXP USA, Inc.
    Inventors: Philippe Mounier, Eric Pierre Rolland, Guillaume Founaud, Maxime Clairet
  • Patent number: 10605865
    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: March 31, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10591517
    Abstract: An electrical fault detector is shown for installation in electrical network (101) of the type comprising a first voltage source (104) and a second voltage source (107), each of which have a respective positive rail (105,108) connected by a positive concentrator (110) and a respective negative rail (106,109) connected by a negative concentrator (111). The detector comprises an inductor (112) for location in one of: the positive concentrator between the connections of the positive rails thereto, and the negative concentrator between the connections of the negative rails to thereto. The detector also comprises a fault identification device (113) configured to monitor the voltage across the inductor, and generate a fault signal in response to the voltage across the inductor exceeding a threshold.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 17, 2020
    Assignee: ROLLS-ROYCE PLC
    Inventors: Steven Fletcher, Stuart J. Galloway, Patrick Norman
  • Patent number: 10591536
    Abstract: An apparatus includes a linear analog circuit and data-check circuit. The linear analog circuit receives analog input signals and provides processed analog output signals. The linear analog circuit includes voltage-changing and voltage-impedance circuitry that perform processing of the analog input signals by the linear analog circuit and an analog test bus circuit (ATB) that selectively passes different ones of a plurality of input ports to at least one output port. A data-check circuit is communicatively coupled to the ATB and includes a data-processing circuit that detects an error conveyed by the linear analog circuit by applying a control signal, while the linear analog circuit and the data-check circuit facilitate testing of the linear analog circuit, to cause the ATB to selectively pass the different ones of the plurality of input ports.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: March 17, 2020
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 10564210
    Abstract: A life determination device for a DC capacitor includes: a current detecting unit that detects a current outputted from a rectifier; a voltage detecting unit that detects a voltage of the DC capacitor; an initial charging device that performs initial charging of the DC capacitor up to a predetermined voltage value with the current outputted from the rectifier; a current integrating unit that integrates the current detected by the current detecting unit during a period of the initial charging; a capacitance estimating unit that calculates an estimated capacitance of the DC capacitor from the current integration value, the predetermined voltage value, and the voltage of the DC capacitor prior to the initial charging; and life determination unit that determines whether the DC capacitor is at the end of its life based on an initial capacitance value of the DC capacitor in an unused state and the estimated capacitance.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: February 18, 2020
    Assignee: FANUC CORPORATION
    Inventor: Tomokazu Yoshida
  • Patent number: 10564211
    Abstract: Disclosed are devices, systems and methods for assessing the integrity of electrical connections between elements of interfacing electronic devices. In some aspects, a system includes an analysis device having electronics that interface with an assay cartridge inserted into the analysis device, wherein the analysis device is configured to conduct a preflight test in which impedance values for each circuit between the assay cartridge and analysis device are rearranged and assessed to determine the electrical connection integrity of the assay cartridge to the analysis device prior to implementing the assay.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: February 18, 2020
    Assignee: GENMARK DIAGNOSTICS, INC.
    Inventor: Roger Harry Taylor
  • Patent number: 10551419
    Abstract: A capacitance value measurement method and a capacitance value measurement device are provided. The capacitance value measurement method includes steps of: acquiring a first mapping relation; setting a standard temperature t0 of one analog-to-digital conversion circuit; and turning off all switching elements of a corresponding switching circuit other than an Ath switching element, turning on the Ath switching element, measuring a real-time temperature t of an analog-to-digital conversion sub-circuit of the analog-to-digital conversion circuit, measuring a real-time capacitance value Cn of an nth testing point, and acquiring a parasitic capacitance value of an external compensation sense line connected to the Ath switching element at the real-time temperature t of the analog-to-digital conversion sub-circuit in accordance with the real-time capacitance value Cn and the first mapping relation, where A is a positive integer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: February 4, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xuehuan Feng, Yongqian Li
  • Patent number: 10514619
    Abstract: The disclosure provides a sensor arrangement for sensing a position of an optical element in a lithography system. The sensor arrangement includes: a first capacitive sensor device having a position-dependent variable first sensor capacitance that can be sensed using a first excitation signal; a second capacitive sensor device having a position-dependent variable second sensor capacitance that can be sensed using a second excitation signal; and a control device configured to produce the first and second excitation signals so that charges present on a parasitic capacitance associable with the first sensor device are at least partially compensated for by charges that are present on a parasitic capacitance associable with the second sensor device via a signal path outside the first and/or the second excitation signal path.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 24, 2019
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Ulrich Bihr, Markus Holz, Jan Horn
  • Patent number: 10481209
    Abstract: A method for checking a wire connection comprises providing a first current by a first power channel and measuring a first voltage by a first measuring channel when each of a positive terminal of the first measuring channel and a positive terminal of the first power channel is connected to one of positive terminals of batteries and each of a negative terminal of the first measuring channel and a negative terminal of the second measuring channel is connected to one of negative terminals of the batteries after measuring the first voltage, providing a second current by the first power channel and measuring a second voltage by the first measuring channel, and determining whether the first measuring channel and the first power channel are connected to a same battery of the batteries.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: November 19, 2019
    Assignee: CHROMA ATE INC.
    Inventors: Chih-Hsien Wang, Kun-Che He, Chung-Kuan Huang, Hong-Yu Lin
  • Patent number: 10466293
    Abstract: Provided is an inspection device that can determine by itself whether a power-supply-side circuit (11, 22, 23) including a solar-cell string (11) is electrically isolated from a PCS (13, 130). The inspection device (14, 140) measures the impedance of the power-supply-side circuit including the solar-cell string (11) and determines whether the power-supply-side circuit is electrically isolated from the PCS (13, 130) on the basis of the capacitive component of the measured impedance.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: November 5, 2019
    Assignee: OMRON Corporation
    Inventors: Shuichi Misumi, Akihiko Sano
  • Patent number: 10467935
    Abstract: Briefly, a method for verifying the visual perceptibility of a display is provided. An intended message is written to a bistable display. Pixels that comprise portions of the message are measured and evaluated to determine if the message actually displayed on the bistable display was perceptible by a human or a machine. In some cases, information regarding the message actually perceivable from the display may be stored for later use. Responsive to determining that a message is perceivable or not perceivable, alarms may be set, one or more third parties notified, or additional display features may be set.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: November 5, 2019
    Assignee: Chromera, Inc.
    Inventors: John Rilum, Paul Atkinson
  • Patent number: 10459287
    Abstract: A dismantling device and a method for dismantling a backlight unit are provided, and the dismantling method includes: placing a liquid crystal module that includes a liquid crystal panel and a backlight unit placed oppositely and connected by a bonding portion onto a supporting table; bringing a line cutting portion that includes two ends and a cutting line therebetween into a gap between the liquid crystal panel and the backlight unit, with at least one of the two ends and the liquid crystal module configured to be movable with respect to each other; and applying a cutting force upon the bonding portion with the line cutting portion along a plane where the bonding portion is located, so as to separate the backlight unit from the liquid crystal panel. This method decreases the force upon the backlight unit to reduce chances of damaging the backlight unit during dismantling the same.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: October 29, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Linlin Wang, Zhiyu Qian, Qinglong Meng, Yinchu Zhao
  • Patent number: 10461689
    Abstract: A method tests the strings of a photovoltaic system, and a photovoltaic inverter has for each string a relay, a current-measuring device and a voltage measuring device, connected to a control device. The control device is designed to control each relay, each current-measuring device and the voltage-measuring device in such a way as to automatically ascertain at least individual values of the U/I characteristic curve of each string. The control device is connected to at least one interface for connection to sensors for measuring environmental parameters in the region of the string and is connected to a memory for storing the ascertained values for creating a test report. The control device is further designed to convert the ascertained values optionally to Standard Test Conditions under defined environmental conditions and to compare the ascertained values with values which are stored in the memory.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 29, 2019
    Assignee: FRONIUS INTERNATIONAL GMBH
    Inventors: Thomas Ringer, Hannes Schwarzkogler, Johannes Schubert, Thomas Sieberer
  • Patent number: 10447029
    Abstract: Disclosed is a connection circuit capable of detecting erroneous wiring of an interconnect device in order to prevent a safety fuse from being melted and quickly perform an overcurrent protection in the event of erroneous wiring or the like. In this connection circuit of the interconnect device, a preliminary wiring check operation is performed when a power control unit receives a power-on signal. It is detected whether or not a power line and a ground line are short-circuited in the preliminary wiring check operation. When the power line and the ground line are not short-circuited, an operation instruction is output from the power control unit to a power unit. As a result, power is turned on after it is checked whether or not the power line and the ground line are short-circuited in advance. Therefore, it is possible to prevent the safety fuse from being melted.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 15, 2019
    Assignee: Fanuc Corporation
    Inventor: Taisei Fujimoto
  • Patent number: 10440825
    Abstract: In various embodiments, a chip card module is provided. The chip card module includes a chip card module contact array having six contact pads that are arranged in two rows having three contact pads each in accordance with ISO 7816, and three additional contact pads that are arranged between the two rows. Each additional contact pad is electrically conductively connected to a respective associated contact pad from a row from the two rows.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pueschner, Peter Stampka, Jens Pohl, Marcus Janke
  • Patent number: 10436616
    Abstract: A system has at least one sensor and a control for analyzing a signal from the sensor. The sensor is operable to send a signal indicative of a presence of a particular occurrence to the control. The sensor also sends a background signal even without the presence of the particular occurrence. The control evaluates the background signal to identify a need for calibration. A method is also disclosed.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 8, 2019
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Kenneth Carney
  • Patent number: 10429441
    Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Tapan Jyoti Chakraborty, Alvin Leng Sun Loke, Hong Dai, Thomas Clark Bryan
  • Patent number: 10429437
    Abstract: A method of operating a data processing system to generate a diagram indicative of an experimental setup includes a device to be tested (DUT) and a plurality of test instruments is disclosed. The method includes detecting a first test instrument that is connected to the data processing system and determining connection points to the first test instrument. A script that specifies tests for the DUT using the plurality of test instruments and includes instructions specifying measurements to be made by the first test instrument is examined. A first connection between the DUT and the first test instrument is determined. An initial diagram on a display controlled by the data processing system is generated. The initial diagram includes a first node representing the first test instrument, a second node representing the DUT and a line representing the first connection between the first and second nodes.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: October 1, 2019
    Assignee: Keysight Technologies, Inc.
    Inventor: Jonathan Helfman
  • Patent number: 10389291
    Abstract: A motor drive device includes an inverter that drives a motor, a power source smoothing capacitor of the inverter, and a control unit that controls the inverter to drive the motor. The control unit precharges the capacitor with a power source voltage, and calculates a capacity value of the capacitor, based on a ratio of the power source voltage and a voltage with which the capacitor is charged, or an amount of time taken until the voltage with which the capacitor is charged, after the passage of a predetermined amount of time from the start of the precharge, reaches a voltage corresponding to the power source voltage. The control unit performs torque limitation of the motor when the capacity value of the capacitor has decreased.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 20, 2019
    Assignee: Hitachi Automotive Sytems, Ltd.
    Inventor: Yawara Kato
  • Patent number: 10382029
    Abstract: The disclosure relates to a control device for controlling a load, wherein the control device comprises the following elements: a first current control valve between a first port of the load and a first potential of an operating voltage; a second current control valve between a second port of the load and a second potential of the operating voltage; a processor configured to actuate the second current control valve when the first current control valve is closed, in order to control a current through the load; and a sampling device for determining an input voltage through the first current control valve, wherein the processor is configured to determine the presence of a short circuit between the first port and the first potential if the input voltage does not increase when the first current control valve is opened gradually.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 13, 2019
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventors: Paul Bange, Thomas Maier
  • Patent number: 10379153
    Abstract: A printed circuit board (PCB) test coupon for thermal exposure and electrical testing includes a double sided or multi-layer substrate with a plurality of vias formed within the substrate of the test coupon (blind, buried, stacked vias) or extending through the entire substrate (through hole/via) from a first surface on the first side of the plated hole/via to a second surface on the second side of the plated hole/via. Each of a first plurality of trace patterns interconnect a subset of the plurality of plated holes/vias on the first side of the plated holes/vias, and each of a second plurality of trace patterns interconnect a different subset of the plurality of plated holes/vias on the second side of the plated holes/vias. The first and second pluralities of trace patterns have different patterns and connect to connection points in a connector pattern defined in the substrate.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 13, 2019
    Assignee: Greater Asia Pacific Limited
    Inventor: Robert Neves
  • Patent number: 10352983
    Abstract: Disclosed are devices, systems and methods for assessing the integrity of electrical connections between elements of interfacing electronic devices. In some aspects, a system includes an analysis device having electronics that interface with an assay cartridge inserted into the analysis device, wherein the analysis device is configured to conduct a preflight test in which impedance values for each circuit between the assay cartridge and analysis device are rearranged and assessed to determine the electrical connection integrity of the assay cartridge to the analysis device prior to implementing the assay.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: July 16, 2019
    Assignee: GENMARK DIAGNOSTICS, INC.
    Inventor: Roger Harry Taylor
  • Patent number: 10352987
    Abstract: A solid state switch power emulator circuit, the circuit including a high voltage section including a high voltage power supply (HVPS); a high voltage capacitor (HVC) electronically connected to the HVPS in parallel; a high voltage switch (HVS) electronically connected to the HVC and the HVPS in series; and a high voltage load (HVL) electronically connected to the HVS in series; a low voltage section including a low voltage power supply (LVPS); a low voltage capacitor (LVC) electronically connected to the LVPS in parallel; a low voltage switch (LVS) electronically connected to the LVPS and the LVC in series; a low voltage load (LVL) electronically connected to the LVS in series; and a high voltage diode (HVD) electronically connected to the LVL in series, wherein voltage levels associated with the low voltage section are less than voltage levels associated with the high voltage section.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: July 16, 2019
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Richard L. Thomas, Jr.
  • Patent number: 10352812
    Abstract: A circuit, a method, and a computer program configured to detect mechanical stress and a circuit, a method, and a computer program configured to monitor safety of a system is disclosed. The detection circuit is configured to monitor a mechanical stress level of a semiconductor circuit. The detection circuit includes a stress monitor circuit configured to monitor a signal comprising mechanical stress level information of the semiconductor circuit, a reference circuit to generate a reference signal, and a calibration circuit configured to modify at least one of the stress signal or the reference signal based on calibration information for the semiconductor circuit to obtain a at least one modified signal.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Hammerschmidt, Friedrich Rasbornig, Michael Strasser
  • Patent number: 10330703
    Abstract: Probe systems and methods including electric contact detection. The probe systems include a probe assembly and a chuck. The probe systems also include a translation structure configured to operatively translate the probe assembly and/or the chuck and an instrumentation package configured to detect contact between the probe system and a device under test (DUT) and to test operation of the DUT. The instrumentation package includes a continuity detection circuit, a test circuit, and a translation structure control circuit. The continuity detection circuit is configured to detect electrical continuity between a first probe electrical conductor and a second probe electrical conductor. The test circuit is configured to electrically test the DUT. The translation structure control circuit is configured to control the operation of the translation structure. The methods include monitoring continuity between a first probe and a second probe and controlling the operation of a probe system based upon the monitoring.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: June 25, 2019
    Assignee: FormFactor Beaverton, Inc.
    Inventors: Sia Choon Beng, Kazuki Negishi
  • Patent number: 10315531
    Abstract: An electrical system for a vehicle includes a high-voltage DC power source electrically connected to a high-voltage bus, a first controller disposed to control electric power flow between the high-voltage bus and a first actuator, and a second controller disposed to control electric power flow between the high-voltage bus and a second actuator. A communication link is disposed to effect communication between the first controller and the second controller. An inertial sensor communicates with the second controller. The second controller includes an instruction set to monitor and determine a request to discharge the high-voltage bus based upon communication from the sensor. Upon determining that the first controller is incapable of discharging the high-voltage bus, the second actuator is controlled to discharge the high-voltage bus.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: June 11, 2019
    Assignee: GM Global Technology Operations LLC.
    Inventors: David J. Mifsud, Marjorie A. Bassham, Kyle Holihan, Emil Francu
  • Patent number: 10302689
    Abstract: An electronic device having at least one connector for at least one wired sensor. The device has a sensor break detection unit, wherein the sensor break detection unit comprises a pulse generator outputting pulses of different polarity being adapted to output at least one electrical signal to the wired sensor and detector means for detecting a response signal from the wired sensor.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 28, 2019
    Assignee: Eurotherm Limited
    Inventors: Jonathan Rich, Mike Newsome, Robert Donarski
  • Patent number: 10288664
    Abstract: The invention relates to a method and to an electrical protection device for detecting a disconnection of a protective conductor connection with a subsystem in ungrounded and grounded power supply systems and in a grounded power supply system comprising a converter system. The invention is based on the idea that the disconnection of the protective conductor connection with a subsystem will reduce the sum of the network leakage capacitances of the power supply system by the value of the network leakage capacitance of the subsystem. The necessary distinction between a subsystem in operation having a disconnected protective conductor connection and a shut-off subsystem is made by evaluating the current total power consumed via the power supply system. In the case of a converter system connected to the subsystem, the protective conductor disconnection is detected by examining the leakage current spectra that are characteristic of the converter system.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 14, 2019
    Assignee: BENDER GMBH & CO. KG
    Inventors: Dieter Hackl, Harald Sellner
  • Patent number: 10263546
    Abstract: A method for determining a motor current of an electric motor drive with a power source and with an electric motor and with a power converter connected therebetween, wherein an input current of the power source is converted by a pulse width modulated control of a number of semiconductor switches of the power converter into the motor current, wherein an intermediate circuit current of an intermediate circuit of the power source is influenced during the pulse width modulated control of the semiconductor switches, wherein an inductive voltage change is detected at a measuring point of the intermediate circuit due to the influence on the intermediate circuit current, and wherein a value for the generated motor current is determined based on the pulse width modulated control of the semiconductor switches and the inductive voltage change detected at the measuring point.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 16, 2019
    Assignee: Brose Fahrzeugteile GmbH & Co. Kommanditgesellschaft, Wuerzburg
    Inventor: Johannes Schwarzkopf
  • Patent number: 10215810
    Abstract: A battery monitoring system includes: an input circuit to which voltage signals of battery cells are inputted; a multiplexer selecting a battery cell for voltage detection from the battery cells, selecting voltage signals inputted from the input circuit, and outputting the selected voltage signals; first and a second voltage measuring circuits simultaneously measuring voltages based on the voltage signals in first and second routes outputted from the multiplexer; a comparator comparing measurement results by the first voltage measuring circuit and by the second voltage measuring circuit; and a control unit that judges, on a basis of a comparison result by the comparator, at least one of a voltage of each battery cell, an operation check of equalizing the voltages of the battery cells, a presence or absence of a disconnection of a detection line of each battery cell, and a presence or absence of a failure in the multiplexer.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 26, 2019
    Assignee: YAZAKI CORPORATION
    Inventor: Takaaki Izawa
  • Patent number: 10209308
    Abstract: A MV switching device (100) comprising: one or more electric poles, each comprising a movable contact (16) and a fixed contact (17) adapted to be coupled or uncoupled during the switching operations of said switching device; and an electromagnetic actuator (13) operatively coupled to the movable contacts of the electric poles, said electromagnetic actuator having at least an excitation winding (152); power supply means (60) for supplying electric power to said electromagnetic actuator; a power drive circuit (1) for driving said electromagnetic actuator, said power drive circuit comprising sensing means for providing signals indicative of the currents flowing along the circuit branches of said power drive circuit and of the voltages at the terminals of said power drive circuit.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: February 19, 2019
    Assignee: ABB SCHWEIZ AG
    Inventors: Andrea Ricci, Gabriele Valentino De Natale, Marco Testa
  • Patent number: 10200186
    Abstract: A system is connected to a single-wire communication line to perform bidirectional communication between a master side and a slave side, and an input clock-side transistor connected between a GND level and the communication line performs switching according to an input clock. A first transistor is connected between a first potential and the communication line, a second transistor has one end connected to a second potential, and a master-side resistor is connected between the other end of the second transistor and the other end of a third transistor. A fourth transistor is connected between the communication line and a third potential equal to or higher than the first potential, and a slave-side resistor is connected between the communication line and the GND level.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 5, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 10178734
    Abstract: An LED lighting circuit for detecting individual LED failure, including a lighting unit including a plurality of LEDs connected in series, and a plurality of LED sensors each associated with a respective one of the LEDs. Also included is a lighting unit status signal generator coupled to the plurality of LED sensors configured to provide a status signal indicating a fault when any individual LED is short circuited.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 8, 2019
    Assignee: Valeo North America, Inc.
    Inventors: Monji Moumen, Sylvain Larribe
  • Patent number: 10175296
    Abstract: A testing arrangement is provided which comprises: a board assembly comprising (i) a first connector configured to receive a first component while the board assembly is to operate in a regular mode of operation and (ii) a second connector configured to receive a second component while the board assembly is to operate in the regular mode of operation; a first test card configured to be attached to the first connector while the board assembly is to operate in a test mode of operation; and a second test card configured to be attached to the second connector while the board assembly is to operate in the test mode of operation, wherein while the board assembly is to operate in the test mode of operation, the first test card is configured to communicate with the second test card to facilitate testing of the board assembly.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Joseph W. Batz, Joseph R. Yuhas, Christopher Lewis, Elizabeth M. Yamada, Michael V. Hill, Ralph E. Rossknecht
  • Patent number: 10175292
    Abstract: In an embodiment, a method of testing a radio frequency integrated circuit (RFIC) includes generating high-frequency test signals using the on-chip test circuit, measuring signal levels using on-chip power detectors, and controlling and monitoring the on-chip test circuit using low-frequency signals. The RFIC circuit is configured to operate at high frequencies, and an on-chip test circuit that includes frequency generation circuitry configured to operate during test modes.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 8, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Johann-Peter Forstner