Of Individual Circuit Component Or Element Patents (Class 324/537)
  • Patent number: 11221361
    Abstract: An example test system includes an output stage to source at least one of voltage or current to a channel of a test instrument; a tracking circuit to detect a channel voltage following the output stage and to control a supply voltage to the output stage based on the channel voltage; and a controller to determine a power dissipation of the output stage based on the supply voltage and the channel voltage, and to control the output stage based on the power dissipation in the output stage.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 11, 2022
    Assignee: TERADYNE, INC.
    Inventors: Jason A. Messier, Bryce M. Wynn, William Bowhers
  • Patent number: 11215676
    Abstract: The present invention relates to a power circuit, which comprises a detection circuit. The detection circuit includes an abnormality detection circuit. The abnormality detection circuit is coupled to an input terminal or/and an output terminal of the power circuit. An input power is provided to the input terminal, and an output power is provided to the output terminal. The abnormality detection circuit controls the paths from a plurality of energy storage elements to the input terminal and the output terminal of the power circuit. The energy storage elements store the energy of the input power to generate the output power. The abnormality detection circuit detects the state of the input power or/and the output power, and cuts off the paths from a portion of the energy storage elements to the input terminal and the output terminal.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: January 4, 2022
    Assignee: Forcelead Technology Corp.
    Inventors: Ta-Hung Chiu, Mao-Hsiang Yeh
  • Patent number: 11215640
    Abstract: There is provided a prober provided with a plurality of inspection chambers. Each inspection chambers includes: a probe card having a plurality of probes; a probe card holder configured to hold the probe card; a chuck top configured to place a cleaning wafer thereon; an aligner configured to drive the chuck top in a vertical direction when the probe card is cleaned using the cleaning wafer; a seal mechanism configured to allow a sealed space to be provided between the probe card holder and the chuck top; a pressure sensor configured to detect an internal pressure of the sealed space, which fluctuates with an operation of the chuck top driven by the aligner; and an electro-pneumatic regulator configured to control the internal pressure of the sealed space by performing an intake or exhaust operation with respect to the sealed space based on the internal pressure detected by the pressure sensor.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 4, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Jun Fujihara
  • Patent number: 11204368
    Abstract: A first signal line pattern has one end electrically connected to a first connector. A second signal line pattern has one end electrically connected to a second connector. The second signal line pattern has the other end facing the other end of the first signal line pattern. A conductive block has a convex portion. The convex portion of the conductive block is electrically connected to a third portion of the conductive pattern positioned between the other end of the first signal line pattern and the other end of the second signal line pattern of the wiring board.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: December 21, 2021
    Assignee: Yokowo Co., Ltd.
    Inventors: Masaki Noguchi, Takahiro Nagata, Tsuyoshi Yamato
  • Patent number: 11181566
    Abstract: A detection circuit of electromagnetic fault injection includes: a shielding layer configured to shield interference; at least one group of metal-oxide semiconductor MOS transistors, where a source end of the at least one group of MOS transistors is connected to the shielding layer; at least one latch, where a drain end of the at least one group of MOS transistors is connected to an input end of the at least one latch; and a signal output module, where an input end of the signal output module is connected to an output end of the at least one latch. The detection circuit could detect in real time and alarm electromagnetic fault injection in time to ensure robustness and safety of a chip.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 23, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Jianfeng Xue, Jiang Yang
  • Patent number: 11184015
    Abstract: In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: November 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ankur Chauhan, Abhrarup Barman Roy
  • Patent number: 11156709
    Abstract: A radar system includes a first radar chip with a first RF contact, a second radar chip with a second RF contact, an RF signal path connecting the first RF contact to the second RF contact, and a local oscillator arranged in the first radar chip and configured to generate an RF oscillator signal, and which is coupled to the first RF contact to transmit the RF oscillator signal to the second radar chip. A feedback circuit arranged in the second radar chip is switchably connected to the second RF contact and is configured to reflect at least part of the RF oscillator signal arriving over the RFRF signal path as an RF feedback signal. A measurement circuit, arranged in the first radar chip, coupled to the first RF contact via a coupler receives the RF feedback signal and is configured to determine a signal that represents a phase shift.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: October 26, 2021
    Inventors: Alexander Melzer, Bernhard Gstoettenbauer, Alexander Onic, Clemens Pfeffer, Christian Schmid
  • Patent number: 11146201
    Abstract: A current value determination device provided with: a capacitor current computation unit for computing the capacitor current of a capacitor included in a high-voltage circuit that drives a motor, on the basis of the input voltage of an inverter included in the high-voltage circuit and the revolution speed of the motor; and a capacitor current determination unit for determining the value of capacitor current on the basis of the input voltage of the inverter, the revolution speed of the motor, the capacitor current computed by the capacitor current computation unit, and a prescribed model for determination.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: October 12, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES THERMAL SYSTEMS, LTD.
    Inventors: Makoto Hattori, Takayuki Takashige, Kyohei Watanabe
  • Patent number: 11137417
    Abstract: A sensor device is provided for testing electrical connections in a DUT using contactless fault detection. The sensor device includes main traces for conducting an RF signal supplied by a signal source; at least one inductor connected to at least one of the main traces; and a slit formed between opposing conductor portions at a tip of the sensor device for sensing open circuits and/or short circuits in portions of the DUT located in a sensing region below the slit, the tip being at an end of the sensor device opposite ends of the main traces connected to the signal source. An electric field, generated by the sensor device in response to the RF signal, substantially concentrates in the slit, enhancing the sensing of the open and/or the short circuits during the contactless fault detection.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: October 5, 2021
    Assignee: Keysight Technologies, Inc.
    Inventors: Tie Qiu, Andrew Choon Kait Tek, Huang Shaoying
  • Patent number: 11115650
    Abstract: A system and a method for monitoring a video communication device configured to monitor an activation state of a video capturing module are provided. A detection circuit is configured to detect an operation current input to the video capturing module. A control circuit is electrically connected to the detection circuit and determines whether the video capturing module is activated according to a magnitude of the operation current.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 7, 2021
    Assignee: Acer Incorporated
    Inventors: Ming-Feng Hsieh, Sheng-Yu Weng, Chun-Chih Kuo, Chih-Cheng Chen
  • Patent number: 11102921
    Abstract: A method of assessing a cleanliness of an assembly in a panel during a manufacturing process is provided, wherein an electrical signal of at least one of a predetermined voltage, current or frequency is applied across a first subset and a second subset of nonconnected electrical contacts in a test coupon associated with the assembly, such that the first subset and the second subset have different pitches. In one configuration, the test coupon is tested at higher voltages, currents or frequencies to a point of failure or above a predetermined threshold.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 24, 2021
    Assignee: IEC Electronics Corp.
    Inventor: Mark Northrup
  • Patent number: 11094237
    Abstract: A display device includes a display panel including first to fourth panel pads and a connection board including first to fourth connection board pads coupled to the first to fourth pads, respectively. The first and second panel pads are electrically connected to each other, and the third and fourth panel pads are electrically connected to each other. The connection board includes a driving circuit which generates a first test result signal based on a first panel test signal transmitted to the first connection board pad and a first panel feedback signal received from the second connection board pad, generates a second test result signal based on a second panel test signal transmitted to the third connection board pad and a second panel feedback signal received from the fourth connection board pad, and sequentially outputs the first and second test result signals as a test result signal.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sung-Jun Kim, Myung-Seok Kwon, Deok-Hwan Kim, Yun-Tae Kim, Jeong-Hyun Kim, Hasook Kim, Bongchun Park
  • Patent number: 11005642
    Abstract: A circuit includes a source device coupled to an output circuit. The source device is configured to produce a sequence of digital values at a rate defined by a data period. The output circuit is configured to receive the sequence of digital values from the source device, generate a copy of each digital value at a predetermined point during the respective data period, and responsive to initiation of a data transaction during a given data period but before the predetermined point, output the digital value from the source device, whereas responsive to initiation of a data transaction during the given data period but after the predetermined point, output the copy of the digital value.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 11, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shawn Xianggang Yu, Venkata Krishnan Kidambi Srinivasan
  • Patent number: 10989766
    Abstract: A test system for checking electrical connections, especially solder connections, between electronic components with a circuit board to be checked, characterized in that the test system includes a communication interface with at least three electrically-conductive contact tips, which by contact with a contacting arrangement on the circuit board having a number of contacting locations enable a data exchange with a data memory and/or a communication module of a circuit board, wherein the data exchange occurs according to a communication protocol.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: April 27, 2021
    Assignee: Endress+Hauser Flowtec AG
    Inventors: Thomas Böhler, Matthias Brudermann, Christoph Werle, Markus Wucher, Daniel Kollmer, Ludovic Adam
  • Patent number: 10985696
    Abstract: A method, an apparatus, and a device for identifying a cell string fault in an optoelectronic system, where the method includes obtaining at least two groups of current-voltage (I-V) values of a first cell string in the optoelectronic system, performing fitting processing according to the at least two groups of I-V values using a predetermined physical string model to obtain at least one characteristic parameter of the first cell string, and comparing the at least one characteristic parameter with a pre-obtained standard characteristic parameter to determine whether the first cell string is faulty, or performing curve fitting processing on collected data using the physical string model. Therefore, identifying the cell string fault in the optoelectronic system is not affected by inconsistency of environments, and processing efficiency and accuracy of string fault identification are effectively improved.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 20, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Guangping Yang, Yongbing Gao
  • Patent number: 10983164
    Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: April 20, 2021
    Assignees: SK hynix Inc., Korea University Research and Business Foundation
    Inventors: Chul Woo Kim, Dong Yoon Kim, In Hwa Jung, Yong Ju Kim
  • Patent number: 10978259
    Abstract: A circuit breaker includes: a live line between a live supply connecting terminal and a live load connecting terminal; a neutral line between a neutral supply connecting terminal and a neutral load connecting terminal; a processing unit; a mechanical switch located in the live line, which mechanical switch is controllable by the processing unit; a trigger for interrupting the live line and/or the neutral line; and an auxiliary line connecting the neutral line with the live line between the mechanical switch and the live load connecting terminal, the auxiliary line including serially a current limiting resistor and a control switch controllable by the processing unit. The processing unit controls the control switch and to open and close at least the mechanical switch for a removal of oxidation layers of mechanical contacts of at least the mechanical switch by controlled arcing.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: April 13, 2021
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventor: Kenan Askan
  • Patent number: 10979041
    Abstract: A system is provided. The system includes a semi-conductor device and a gate drive board. The gate drive board provides a voltage to the semi-conductor device. The system also includes a controller and a monitoring circuit. The controller drives the voltage provided by the gate drive board. The monitoring circuit is coupled to the gate drive board to monitor operations of the controller and the semi-conductor device.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 13, 2021
    Assignee: HAMILTON SUNSTRAND CORPORATION
    Inventors: Christopher J. Courtney, Gary L. Miles
  • Patent number: 10955465
    Abstract: Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: March 23, 2021
    Assignee: Teradyne, Inc.
    Inventors: Anthony J. Suto, John Joseph Arena, Joseph Francis Wrinn
  • Patent number: 10944276
    Abstract: The device housing includes a roller cradle. The device can include a device support roller rotationally located in the roller cradle, the device support roller being removably couplable with the roller cradle. Also, a release mechanism can be include, where the release mechanism includes a push button operably coupled to a coupler mechanism that is operably coupled to the device support roller. The release mechanism and/or coupler mechanism are biased. When the release mechanism is not activated, the device support roller is engaged, and when the release mechanism is active, the device support roller is disengaged. The system can include a plurality of device support rollers, each device support roller having a device-receiving slot, each device-receiving slot being of a different shape and/or dimension from the other device-receiving slots of the other device support rollers.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 9, 2021
    Assignee: REMVO Inc.
    Inventor: John S. Smith
  • Patent number: 10931101
    Abstract: The present invention discloses an electrostatic discharge (ESD) protection circuit, including: a first terminal configured to receive a first voltage; a second terminal configured to receive a second voltage; a detection voltage generating circuit configured to provide a detection voltage according to the first voltage and the second voltage; a warning circuit configured to generate a control signal according to the detection voltage, in which the control signal indicates a normal condition when the detection voltage satisfies predetermined voltage setting, and the control signal indicates an abnormal condition when the detection voltage does not satisfy the predetermined voltage setting; and a protected circuit configured to carry out a self-protection operation when receiving the control signal indicating the abnormal condition.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 23, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Ming Wu, Jian-Ru Lin, Liang-Huan Lei, Cheng-Pang Chan
  • Patent number: 10928461
    Abstract: Battery management systems and methods for operation of same are provided. A first switchable resistance may be connected between a cell stack positive end and ground. A second switchable resistance may be connected between a cell stack negative end and ground. The switches for each resistance may be alternately opened and closed, with comparison of the resulting currents through each resistance being indicative of a location of isolation leakage current within a battery system cell stack, and/or the magnitude of isolation leakage current. Currents through the first and/or second switchable resistances may also be indicative of Y capacitance. The first and second switchable resistances may further be used to reduce energy stored by Y capacitance.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: February 23, 2021
    Inventor: Erik Stafl
  • Patent number: 10921202
    Abstract: A tamper detection system includes a detector that measures a value of a parameter for each connection of multiple breakable remakeable connections between first and second components. The system includes an analyzer that compares the measured parameter value for each connection or a representative value derived from measured parameter values of the connections to an expected value. Based on the comparisons, the analyzer determines whether the multiple breakable remakeable connections between the first and second components have been broken and remade.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 16, 2021
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Warren B. Jackson, Eugene M. Chow
  • Patent number: 10914791
    Abstract: A test system for testing electrical connections, especially soldered connections, between electronic components and a circuit board to be tested, characterized in that the test system has a communication interface, which by contacting the circuit board enables a data exchange with a data memory or a communication module of the circuit board to be tested, wherein the communication interface is arranged within a housing of the test system freely movably in at least two spatial directions, preferably three spatial directions.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: February 9, 2021
    Assignee: Endress+Hauser Flowtec AG
    Inventors: Thomas Böhler, Matthias Brudermann, Christoph Werle, Markus Wucher, Daniel Kollmer, Ludovic Adam
  • Patent number: 10917976
    Abstract: A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: February 9, 2021
    Assignee: Juniper Networks, Inc.
    Inventors: Steve M. Wilkinson, Daniel J. Prezioso
  • Patent number: 10897275
    Abstract: In a modulation correction method, an adjusted amplitude is determined based on an amplitude between adjacent zero crossings of a modulated signal, the adjacent zero crossings are shifted to determine shifted zero crossings, and the modulated signal is adapted based on the adjusted amplitude and the shifted zero crossings to generate a corrected modulated signal corresponding to the modulated signal.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Christoph Preissl, Tobias Buckel, Thomas Mayer, Peter Preyler
  • Patent number: 10890618
    Abstract: Various embodiments are described that relate to failure determination for an integrated circuit. An integrated circuit can be tested to determine if the integrated circuit is functioning properly. The integrated circuit can be subjected to a specific radiation such that the integrated circuit produces a response. This response can be compared against an expected response to determine if the response matches the expected response. If the response does not match the expected response, then the integrated circuit fails the test. If the response matches the expected response, then the integrated circuit passes the test.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 12, 2021
    Assignee: The Government of the United States, as represented by the Secretary of the Army
    Inventors: Greg Rupper, John Suarez, Sergey Rudin, Meredith Reed, Michael Shur
  • Patent number: 10890610
    Abstract: According to some embodiments, a tester tests one or more DUTs by utilizing one or more respective reference devices. The tester comprises one or more test sites and one or more test circuits operatively coupled to each of the test sites. Each test site is configured to: hold a reference device and a DUT, transmit a transmitted electromagnetic RF signal including a test data pattern to the DUT, and receive a received electromagnetic RF signal emitted from the DUT. The test circuits are configured to: receive a first electrical signal converted from the received electromagnetic RF signal, extract first data from the first electrical signal, determine a first error rate between the test data pattern and the first data, and generate a test result on the basis of the first error rate.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: January 12, 2021
    Assignee: Keyssa Systems, Inc.
    Inventors: Srikanth Gondi, Arunprasad Ramiya Mothilal
  • Patent number: 10886086
    Abstract: For providing a very simple and reliable monitoring of the functionality of contacts together with a high flexibility of selection of the contacts a method for monitoring the functionality of redundantly interconnected contacts is provided, preferably within a load current circuit, wherein said n contacts, n=2, provide an electrical connection between a power supply and a load, wherein said n contacts are switchable by a controller and wherein each of said n contacts is designed for providing the electrical connection between the power supply and the load all alone.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 5, 2021
    Assignee: PEPPERL+FUCHS SE
    Inventors: Daniel Saulheimer, Friedrich Fuess
  • Patent number: 10867823
    Abstract: A fault detection method in a semiconductor fabricating factory is provided. The method includes delivering a test vehicle along a rail to a test region. The method further includes projecting a test signal from a transducer that is positioned on the test vehicle over a check board when the test vehicle is located within the test region. The check board and the test vehicle are arranged along an axis that is parallel to the rail. The method also includes performing an analysis of the test signal projected over the check board. In addition, the method includes issuing a warning alarm when an abnormality is detected based on the analysis result.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Jung Huang, Yung-Lin Hsu, Kuang-Huan Hsu, Wei-Chih Chen, Jen-Ti Wang, Chih-Hung Liu
  • Patent number: 10862173
    Abstract: A protection circuit board includes a printed circuit board having a circuit is printed on a board formed from an electrically insulating material and two or more connection components disposed on at least one surface of the printed circuit board and are coupled to an electrode terminal of a secondary battery. Additionally, at least one inspection slot having a shape recessed within the connection component and extending to a portion that the electrode terminal of the secondary battery is coupled thereto and is defined in the connection component.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 8, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Jin Oh Yang, Young Su Son, Suk Jin Song, Jae Young Jang
  • Patent number: 10854247
    Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Harish N. Venkata
  • Patent number: 10837994
    Abstract: An electrical test device may include a power supply, a conductive probe element, and a spectral analysis block. The power supply may be connected to an external power source. The conductive probe element may be connected to the power supply and may be configured to be energized by the power supply. The probe element may be configured to be placed in contact with an electrical system under test and apply an input signal containing current for measuring at least one parameter of the electrical system. The spectral analysis block may be connected to the probe element and may be configured to receive an output signal from the electrical system in response to the application of the current to the electrical system. The spectral analysis block may be configured to analyze frequency spectra of the output signal and detect a broadband increase in energy of the frequency spectra above a predetermined energy threshold.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: November 17, 2020
    Assignee: Power Probe, Inc.
    Inventors: Jeff Whisenand, Randy Cruz
  • Patent number: 10838033
    Abstract: In one embodiment, a tester calibration device includes a first board to be installed on one of a plurality of sockets of a tester for testing a semiconductor device, when the tester is to be calibrated. The device further includes a plurality of first pins provided on a first face of the first board, and to be made contact with the one socket when the tester is to be calibrated. The device further includes a wiring configured to electrically connect some of the plurality of first pins with each other.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuhito Hayasaka
  • Patent number: 10782316
    Abstract: An integrated circuit device testing system includes a socket configured to receive an integrated circuit device, wherein the socket comprises at least one conductive trace made of a material with a resistivity that is a function of temperature, and wherein the socket is configured such that, when the integrated circuit device is located in the socket, the at least one conductive trace extends along a surface of the integrated circuit device. The integrated circuit device testing system further includes a controller or active circuit configured to determine a temperature at the surface of the integrated circuit device based on a measured resistance of the at least one conductive trace.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: September 22, 2020
    Assignee: DELTA DESIGN, INC.
    Inventor: Jerry Ihor Tustaniwskyj
  • Patent number: 10756538
    Abstract: A technique for operating a driver includes enabling the driver to provide a first current through a first terminal of a driver device of the driver in a first mode of operation. The method includes sensing a voltage drop across the first terminal and a second terminal of the driver device to generate a sensed voltage level indicative of the voltage drop. The method includes generating a comparison output signal indicative of a comparison of the sensed voltage level to a threshold voltage level. The method includes selectively enabling the driver to provide a second current in a second mode of operation based on the comparison output signal. The first current may be less than the second current. The enabling may include enabling a first portion of the driver device using a first control signal, while a second portion of the driver device is disabled using a second control signal.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: August 25, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Pranav R. Kaundinya, Sean A. Lofthouse
  • Patent number: 10753972
    Abstract: A wafer inspection system is provided. The wafer inspection system comprises: a transfer region in which a transfer device is arranged; an inspection region in which test heads for inspecting a substrate are arranged; and a maintenance region in which the test heads are maintained. The inspection region is located between the transfer region and the maintenance region, a plurality of inspection rooms accommodating the test heads are adjacent to each other in the inspection region, and the test heads are configured to be unloaded from the inspection region to the maintenance region.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 25, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Junichi Hagihara, Shigekazu Komatsu, Kunihiro Furuya, Tadayoshi Hosaka, Naoki Muramatsu
  • Patent number: 10739418
    Abstract: A method of reading out a Hall plate which comprises at least 4 contacts. The method comprises: reading out two of the contacts while biasing two other contacts of the at least 4 contacts thereby obtaining a readout signal; switching biasing and readout contacts according to a random or pseudo-random sequence of phases, each phase corresponding with a different permutation of biasing and readout contacts selected from the at least 4 contacts of the Hall plate wherein the biasing and readout contacts are selected such that the readout signal is a measure for the magnetic field; processing of the readout signal to obtain a readout of the Hall plate representative for the magnetic field.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: August 11, 2020
    Assignee: Melexis Technologies SA
    Inventors: Johan Raman, Pieter Rombouts
  • Patent number: 10732219
    Abstract: An apparatus for testing semiconductor devices and a system including the same includes a socket unit having a plurality of sockets into which a plurality of semiconductor devices are inserted, respectively. Also included is a module unit including a first sub-module for receiving a test signal from a host and providing the same test signal to each of the plurality of sockets, and a second sub-module including the same structure as the first sub-module. The first sub-module includes a first buffer unit including an amplifier having an input terminal to which an input signal is inputted and an output terminal to amplify and output the input signal inputted based on a reference voltage (VT), and a reference resistor having one end connected to the input terminal of the amplifier and the other end to which the reference voltage is applied, and a second buffer unit including the same structure as the first buffer unit.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ki Jae Song
  • Patent number: 10733345
    Abstract: A method for automatically finding a verification test of a plurality of verification tests that were executed in a verification process of a design under test (DUT) that satisfies a criterion, may include using a processor, obtaining from a user a criterion that relates to one or more test actions; using a processor, obtaining a log with logged execution data that includes start and end times for each action of each of the tests of the plurality of verification tests during an execution run of that test; and for each test of the plurality of verification tests, using a processor, determining from the logged data whether that test satisfies the obtained criterion, and if a test of the plurality of verification tests was determined to satisfy the obtained criterion, using a processor, executing that test on the DUT.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 4, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Meir Ovadia, Matan Vax
  • Patent number: 10715123
    Abstract: Circuits and methods for correction of errors in multi-stage stepwise signal modification circuits. Embodiments of the invention also provide flexibility to correct accuracy errors over a range of conditions, such as differences in signal frequency and/or temperature. A first embodiment includes sorting actual values of a multi-stage stepwise signal modification circuit to generate a monotonic listing of actual values; mapping input codes to a new order of codes corresponding to the sorted actual values; and providing mapping functionality to convert each input code into a mapped output code. A second embodiment includes searching, for each ideal value corresponding to an input code, all actual values of a multi-stage stepwise signal modification circuit for the actual value closest to the ideal value; mapping input codes to a new order of codes corresponding to the closest actual values; and providing mapping functionality to convert each input code into a mapped output code.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 14, 2020
    Assignee: pSemi Corporation
    Inventor: Mark James O'Leary
  • Patent number: 10705938
    Abstract: An improved method for telecommunication analysis and monitoring employing a logic analyzer device. The logic analyzer device provides a plurality of concurrent graphic depictions of different electronic signals under differing electronic protocols for signal error determination on a communications channel. Error source determination is enabled through the provided concurrent depiction of digital and analog signal characteristics in the differing protocols, including digital data packets, signal voltages and timing. Through this concurrent depiction the user can visually discern potential causation for electronic communication errors caused by non-continuous signal anomalies affecting one or more of the protocols.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: July 7, 2020
    Inventor: David Webster
  • Patent number: 10679533
    Abstract: Methods and systems to provide baseline measurements for aging compensation for a display device are disclosed. An example display system has a plurality of active pixels and a reference pixel. Common input signals are provided to the reference pixel and the plurality of active pixels. The outputs of the reference pixel is measured and compared to the output of the active pixels to determine aging effects. The display system may also be tested applying a first known reference current to a current comparator with a second variable reference current and the output of a device under test such as one of the pixels. The variable reference current is adjusted until the second current and the output of the device under test is equivalent of the first current. The resulting current of the device under test is stored in a look up table for a baseline for aging measurements during the display system operation.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 9, 2020
    Assignee: Ignis Innovation Inc.
    Inventors: Gholamreza Chaji, Joseph Marcel Dionne, Yaser Azizi, Javid Jaffari, Abbas Hormati, Tong Liu, Stefan Alexander
  • Patent number: 10673223
    Abstract: An arc fault detection arrangement for a DC electric bus, the DC electric bus having one or more electric lines adapted to electrically connect a source section and a load section of an electric apparatus, the arc fault detection arrangement including an arc fault detector adapted to receive and process detection signals indicative of AC currents flowing along the electric lines.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 2, 2020
    Assignee: ABB Schweiz AG
    Inventors: Sauro Macerini, Mirco Mirra
  • Patent number: 10663505
    Abstract: A test system for performing a test on a device under test is provided. The test system comprises, at least one test device, configured for performing the test on the device under test, and at least one camera, configured for recording video data of the device under test and/or the at least one test device. Moreover, the test system comprises a storage unit, which is configured for storing the recorded video data and a video reproduction unit, which is configured for reproducing the recorded video. The video reproduction unit is moreover configured for reproducing the recorded video at an adjustable speed.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: May 26, 2020
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Doug Jones
  • Patent number: 10641819
    Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Mincent Lee
  • Patent number: 10613134
    Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 7, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Sigfredo E. Gonzalez Diaz, Benjamin Lee Amey, Patrick Michael Teterud, Hung Nguyen
  • Patent number: 10606329
    Abstract: An integrated circuit comprising: an input terminal configured to receive a failure-event-signal representative of a failure event; a first output terminal configured to provide a first-failure-signal; and a second output terminal configured to provide a second-failure-signal; and a processing block configured to: set the first-failure-signal based on the failure-event-signal; and set the second-failure-signal, at a predetermined time interval after the first-failure-signal is set. The processing block further comprises a switch configured selectively, based on a received digital-error-signal to either: set the second-failure-signal based on a digital-counter-output-signal; or set the second-failure-signal based on an analogue-trigger-signal.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 31, 2020
    Assignee: NXP USA, Inc.
    Inventors: Philippe Mounier, Eric Pierre Rolland, Guillaume Founaud, Maxime Clairet
  • Patent number: 10605865
    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: March 31, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10591536
    Abstract: An apparatus includes a linear analog circuit and data-check circuit. The linear analog circuit receives analog input signals and provides processed analog output signals. The linear analog circuit includes voltage-changing and voltage-impedance circuitry that perform processing of the analog input signals by the linear analog circuit and an analog test bus circuit (ATB) that selectively passes different ones of a plurality of input ports to at least one output port. A data-check circuit is communicatively coupled to the ATB and includes a data-processing circuit that detects an error conveyed by the linear analog circuit by applying a control signal, while the linear analog circuit and the data-check circuit facilitate testing of the linear analog circuit, to cause the ATB to selectively pass the different ones of the plurality of input ports.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: March 17, 2020
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat