Of Individual Circuit Component Or Element Patents (Class 324/537)
  • Patent number: 11885647
    Abstract: A sensor apparatus includes a resonator, a transducer, a damping resistor, a first switch, a filter stage, a second switch, and a noise rejection stage. The transducer is configured to detect a position of the resonator. The damping resistor is configured to electrostatically actuate the transducer and convert a thermomechanical noise of the resonator to an electromechanical noise. The first switch is configured to receive a first signal from the transducer. The filter stage is configured to receive the first signal and adjust a phase and a gain of the first signal and output a filtered first signal. The second switch is configured to receive a second signal from the transducer. The noise rejection stage is configured to receive the filtered first signal and the second signal and reduce the filtered first signal from an output signal.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: January 30, 2024
    Assignee: ROHM Co., Ltd.
    Inventor: Jonah Dewall
  • Patent number: 11860228
    Abstract: An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: January 2, 2024
    Assignee: XILINX, INC.
    Inventors: Albert Shih-Huai Lin, Niravkumar Patel, Amitava Majumdar, Jane Wang Sowards
  • Patent number: 11854640
    Abstract: A memory device includes: a plurality of channels, each including a memory cell array, the memory cell array including a normal cell array, the normal cell array including normal memory cells, and each of the normal memory cells being a volatile memory cell; a testing control circuit, configured to control testing of the normal cell array in the plurality of channels in response to a testing instruction, and to determine an access address of a normal memory cell failing the testing in the normal cell array in the plurality of channels to be a failure address; and a non-volatile memory cell array which includes a plurality of non-volatile memory cells and is configured to receive and store the failure address from the testing control circuit.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Patent number: 11846656
    Abstract: A current sensor for detecting a current based on a terminal voltage and a resistance value of a shunt resistor, includes: a resistance value correction circuit having: correction resistors; a signal application unit; a voltage detection unit that detects terminal voltages of the shunt resistor and a part of the correction resistors in a first period, and terminal voltages of all of the correction resistors in a second period; and a correction unit that corrects the resistance value for current detection based on a calculated resistance value of the shunt resistor. Resistance values and resistance accuracies of the correction resistors are higher as the plurality of correction resistors are disposed farther from the shunt resistor.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: December 19, 2023
    Assignees: DENSO CORPORATION, TOYOTA IDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventors: Tomohiro Nezuka, Yoshikazu Furuta, Shotaro Wada
  • Patent number: 11846280
    Abstract: A flushing pump including: a pump configured to draw fluid from a reservoir and expel the drawn fluid from a fluid outlet; a processor configured to control operation of the pump; and a remote controller connection port in electrical communication with the processor. The remote controller connection port including: an output system connection point; an input system connection point; a debugging connection point; and a ground connection point held at a reference voltage level. Wherein the processor is configured to output diagnostic information to the output system connection point in response to the debugging connection point receiving a signal at the reference voltage level.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: December 19, 2023
    Assignee: KEYMED (MEDICAL & INDUSTRIAL EQUIPMENT) LIMITED
    Inventors: Chu Wang, Simon Morrison, Gareth Sykes
  • Patent number: 11789046
    Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: October 17, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Davide Argento, Orazio Pennisi, Stefano Castorina, Vanni Poletto, Matteo Landini, Andrea Maino
  • Patent number: 11774489
    Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Justin Huttula
  • Patent number: 11762037
    Abstract: A method for identifying an inverter short circuit between two phases includes measuring AC current values of three phases. Values of a temporal current change are also identified based on the measured AC current values. A short circuit between two phases is then assumed if, in one phase at DC+ and one phase at DC?, the current rises more quickly or falls more quickly than a predetermined threshold value. In order to check this assumption, it is identified whether the value of the identified rise in a first phase possibly affected by the short circuit corresponds to the value of the identified fall in a second phase possibly affected by the short circuit. In the event that the assumption has been positively confirmed, it is also checked whether a current sum of the phases is still unchanged. A short circuit is established when the two checks have proven positive.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: September 19, 2023
    Assignee: Rolls-Royce Deutschland Ltd & Co KG
    Inventor: Marco Bohlländer
  • Patent number: 11757391
    Abstract: A motor drive system of a vehicle includes: an inverter that receives power from a power source via a bus, where the inverter is connected to a motor of the vehicle; a driver that drives the inverter; a filter that filters a current signal received from the bus to generate a filtered signal; and a control module that operates in an impedance determination mode. The impedance determination mode includes: based on the filtered signal, controlling the driver and the inverter to generate a pulsed signal applied to the power source; determining a current level and a voltage of the power source due to generation of the pulsed signal, and determining impedance based on the current level and the voltage. The control modules are configured to: determine a characterization parameter of the power source based on the impedance; and perform a control operation or a countermeasure based on the characterization parameter.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: September 12, 2023
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Lei Hao, Yue-Yun Wang, Steven E. Muldoon
  • Patent number: 11714115
    Abstract: An instrument interface method and device. Two capacitors, one capacitor has one end as input of the device, connected to live line of power output of a LISN, and has other end as output of the device, connected to one test port of an oscilloscope; the other capacitor has one end as input of the device, connected to neutral line of the power output of the LISN, and has other end as output of the device, connected to another test port of the oscilloscope; without changing the LISN design, existing LISN products can be used for conducted emission test with oscilloscope-based time-domain EMI measurement instruments by means of the method and device. Said two capacitors have a capacity of <0.09 ?F, which reduced the requirements of oscilloscope's A/D conversion, making low-cost oscilloscope can also be used for EMI testing.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 1, 2023
    Inventor: Wei Wu
  • Patent number: 11703546
    Abstract: A monitor circuit for use in a management system with modular subsystems includes: a sensor configured to measure parameter values of a monitored electrical component as a function of time; and storage coupled to the sensor and configured to store the parameter values. The monitor circuit also includes frame preparation circuitry coupled to the storage and configured to prepare frames that include the parameter values, wherein the prepared frames vary in length as a function of time.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: July 18, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Tomas Urban, Kyl Wayne Scott, Hans-Georg Christian Haeck, Ariton E. Xhafa
  • Patent number: 11668744
    Abstract: A contact for burning-in and testing a semiconductor IC and a socket device including the contact are proposed. The contact includes: an upper terminal part (111) having an upper tip part (111b) at an upper end part thereof; a lower terminal part (112) having a lower tip part (112c) at a lower end part thereof and provided on the same axis as the upper terminal part (111); and an elastic part (113) elastically supporting the upper terminal part (111) and the lower terminal part (112), wherein the upper terminal part (111) and the lower terminal part (112) include a shoulder part (111a) and a shoulder part (112a), respectively, formed by protruding therefrom in width directions thereof, and the elastic part (113) has a third width (w3), and includes a first strip (113a) and a second strip (113b).
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: June 6, 2023
    Inventors: Dong Weon Hwang, Logan Jae Hwang, Jae Baek Hwang
  • Patent number: 11644489
    Abstract: It is provided a current recording method, a current recording device and a current recording system by the embodiments of this disclosure. The current recording method comprises: acquiring a first current Fourier value, the first current Fourier value being a Fourier value acquired by Fourier transforming an instantaneous value of current at a first end of a power line; acquiring a second current Fourier value, the second current Fourier value being a Fourier value acquired by Fourier transforming an instantaneous value of current at a second end of the power line; time-alignment the first current Fourier value and the second current Fourier value, based on a first transmission delay for acquiring the first current Fourier value and a second transmission delay for acquiring the second current Fourier value; storing the aligned first current Fourier value and second current Fourier value into a storage.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 9, 2023
    Assignee: Schneider Electric Industries SAS
    Inventor: Wansen Du
  • Patent number: 11640888
    Abstract: Proposed are an input/output device and a control method for the same, the device including a first input/output terminal that receives a forward signal from a limit switch or outputs power to a sensor; a second input/output terminal that receives a backward signal from the limit switch or receives a sensing signal from the sensor; and an integrated circuit unit that determines a communication target for exchanging a signal through the first input/output terminal and the second input/output terminal, and selectively receives or outputs the forward signal, the backward signal, the power of the sensor and the sensing signal based on the determination result.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: May 2, 2023
    Assignee: HYUNDAI TRANSYS INCORPORATED
    Inventors: Jin Woo Lee, Se Min Kim
  • Patent number: 11619681
    Abstract: A method for detecting an isolation fault in an electrical installation comprises: measuring an AC electrical voltage between phase conductors of an electrical load to be monitored and ground, and an electric fault current flowing between said electrical load and ground; identifying, in the measured electrical voltage, at least one first component oscillating at the predefined first frequency and one second component oscillating at the predefined second frequency; calculating an impedance of the electrical fault from the measurements and an impedance of the electrical installation from the identified first and second components; selecting a predetermined case from a predefined list; and identifying an operating condition of the electrical installation on the basis of the selected predetermined case.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: April 4, 2023
    Assignee: Schneider Electric Industries SAS
    Inventors: François Vincent, Jiri Stepanek
  • Patent number: 11567121
    Abstract: An integrated circuit, comprising a plurality of pins, including a signal output pin. The integrated circuit also comprises a plurality of signal nodes. Each node in the plurality of signal nodes is operable to store a respective internal data signal. The integrated circuit also comprises a plurality of testing circuits. Each testing circuit in the plurality of testing circuits configured to sample a respective internal data state and in response to concurrently couple a unique output signal to a same pin in the plurality of pins, other than the signal output pin.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 31, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: George Earl Fleming, Adrian Poh Siang Chan
  • Patent number: 11561255
    Abstract: An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 24, 2023
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Xiankun Jin, Srikanth Jagannathan
  • Patent number: 11552230
    Abstract: A pixel array substrate includes a base, pixel structures, first bonding pads, first wirings, and a first testing element. The pixel structures are disposed on an active area of a first surface of the base. The first bonding pads are disposed on a peripheral region of the first surface. Each of the first wirings is disposed on a corresponding first bonding pad, a first sidewall of the base, and a corresponding second bonding pad. The first testing element is disposed on the active area of the first surface and has a first testing line. The first testing line is electrically connected to at least one of the first bonding pads, and an end of the first testing line is substantially aligned with an edge of the base.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 10, 2023
    Assignee: Au Optronics Corporation
    Inventors: Shang-Jie Wu, Hao-An Chuang, Yu-Chieh Kuo, He-Yi Cheng, Che-Chia Chang, Yi-Jung Chen, Yi-Fan Chen, Yu-Hsun Chiu, Mei-Yi Li, Yu-Chin Wu
  • Patent number: 11532998
    Abstract: A power supply circuit for measuring transient thermal resistances includes an inverter circuit provided on a primary side of a transformer and controlled by a PWM signal, a rectifier circuit provided on a secondary side of the transformer and including a DC reactor, and a control circuit controlling the PWM signal so as to output a pulsed output current from the rectifier circuit to a semiconductor device to be measured. The control circuit sets a first PWM frequency at rising timing of the output current, and sets a second PWM frequency when a predetermined time t1 elapses from the rising timing of the output current. The control circuit sets the first PWM frequency higher than the second PWM frequency.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 20, 2022
    Assignee: Sansha Electric Manufacturing Co., Ltd.
    Inventors: Naoki Nishimura, Masashi Fukai
  • Patent number: 11506726
    Abstract: A system and method for detecting the location of coil open and coil short faults. The method includes obtaining an instantaneous admittance signature of each solenoid coil, sending out a periodic test signal to each valve, obtaining a new admittance signature; and calculating the coil-open and coil-short faults.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 22, 2022
    Assignee: DANFOSS POWER SOLUTIONS II TECHNOLOGY A/S
    Inventors: Mayura Arun Madane, Nilesh Surase, Arjun Tr, Amogh Kank
  • Patent number: 11500012
    Abstract: A semiconductor component burn-in test module includes a burn-in board and an external power transmission component. The burn-in board includes a plurality of burn-in seats, wherein a plurality of chips are disposed on the burn-in seats. The external power transmission component is arranged at opposite two sides of the burn-in board, where the external power transmission component includes a plurality of conductive members and a plurality of terminal seats. The burn-in board is provided with a plurality of wirings corresponding to the external power transmission component. As such, electric power can be conveyed to the plural burn-in seats of the burn-in board, through the plural terminal seats and the plural conductive strips. This decreases the length and the number of copper foil wirings in the burn-in boards for power transmission, so as to lower the cost of the burn-in boards.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: November 15, 2022
    Assignee: KING YUAN ELECTRONICS CO., LTD.
    Inventors: Chia-Hung Tsai, Kuo-Jung Wu, Hsing-Yueh Liang, Po-Wei Liao, Yi-Ting Wang
  • Patent number: 11491738
    Abstract: Provided among other things is a method of affixing a small, single chip to a plastic item, the chip having a top surface having length and width dimensions, and having a height, the method comprising: (1) vacuum adhering a top-oriented surface of the chip to a probe of outer dimensions comparable to or smaller than those of the length and width; (2) conveying heat to the chip via the probe such that a bottom-oriented surface of the chip is sufficiently hot to melt the plastic; (3) applying via the probe the chip to the plastic such that the chip embeds in the plastic; and (4) releasing the chip from the probe, wherein the largest of the length and width is about 500 microns or less, and height is no more than about the smallest of length and width.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: November 8, 2022
    Assignee: P-CHIP IP HOLDINGS INC.
    Inventors: Ziye “Jay” Qian, Wlodek Mandecki
  • Patent number: 11448681
    Abstract: An insulation monitoring electric circuit of an electric-motor controller, includes: a first voltage sampling circuit and a second voltage sampling circuit; the first voltage sampling circuit is connected to an input anode (+VBUS) of a busbar, an input cathode (PGND) of the busbar and a busbar-voltage sampled-signal (HV_VDC) line, and a busbar-voltage sampled-signal (HV_VDC) line is connected to the electric-motor controller; the second voltage sampling circuit is connected to the input anode (+VBUS) of the busbar, the input cathode (PGND) of the busbar and an insulation-voltage sampled signal (HV_VDC) line, and an insulation-voltage sampled signal (HV_VISO) line is connected to the electric-motor controller; and the electric-motor controller is configured to compare a busbar-voltage value gathered by the first voltage sampling circuit and an insulation-voltage value gathered by the second voltage sampling circuit, and when the busbar-voltage value and the insulation-voltage value are different, emit an insul
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 20, 2022
    Assignee: Jing-Jin Electric Technologies Co., Ltd.
    Inventors: Yuxia Qu, Fuxiang Wan, Lingling Tan
  • Patent number: 11444566
    Abstract: An overcurrent protection circuit and a controller are provided. The overcurrent protection circuit includes a sampling circuit, a comparator circuit, a D flip-flop, and an output signal control circuit. The sampling circuit samples a current of a controlled circuit to obtain a sample signal. The comparator circuit compares the sample signal with a reference signal, and generates an overcurrent signal if the sample signal is greater than the reference signal. The D flip-flop generates a first level signal in response to the overcurrent signal. The output signal control circuit outputs, in response to the first level signal, a control signal for reducing the current of the controlled circuit. The controller includes a controlled circuit and the overcurrent protection circuit.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 13, 2022
    Assignee: Hangzhou Leaderway Electronics Co., Ltd.
    Inventors: Yongsong Lv, Qi Wang
  • Patent number: 11428711
    Abstract: A testing apparatus includes a chip carrying device and a pressing device. The chip carrying device includes a circuit board and a plurality of electrically connecting units that are disposed on the circuit board and each can receive a chip. The pressing device includes a cover and an abutting member disposed between the cover and the electrically connecting units. The cover is disposed on the circuit board to jointly define an accommodating space that accommodates the abutting member and the electrically connecting units. The cover can be connected to an air suction apparatus for expelling air in the accommodating space. When the air suction apparatus performs a suction operation to expel the air in the accommodating space, the abutting member is abutted against the electrically connecting units and the chips so as to connect each of the electrically connecting units and the corresponding chip.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 30, 2022
    Assignee: ONE TEST SYSTEMS
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11413864
    Abstract: A die for a printhead is described herein. The die includes a number of fluid feed holes disposed in a line parallel to a longitudinal axis of the die, wherein the fluid feed holes are formed through a substrate of the die. A number of fluidic actuators are proximate to the fluid feed holes to eject fluid received from the plurality of fluid feed holes. The die includes logic circuitry to operate the fluidic actuators, wherein the logic circuitry is disposed on a first side of the plurality of fluid feed holes. Power circuitry to power the plurality of fluidic actuators is disposed on an opposite side of the fluid feed holes from the logic circuitry. Activation traces are disposed between each of the fluid feed holes to couple the logic circuitry to the power circuitry.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: August 16, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James Michael Gardner, Anthony M. Fuller, Michael W. Cumbie, Scott A. Linn
  • Patent number: 11384675
    Abstract: The control section of a control apparatus executes a first control for operating a voltage application section such as to cause a current to flow in a first direction through a gas sensor in a first period, and a second control for operating the voltage application section such as to cause a current to flow in a second direction, opposite to the first direction, through the gas sensor in a second period. The control apparatus changes the length of at least one of the first period and the second period based on a comparison between a first measurement value, which is the absolute value of a value measured by a sweep measurement section during execution of the first control, and a second measurement value, which is the absolute value of a value measured by the sweep measurement section during execution of the second control.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: July 12, 2022
    Assignees: DENSO CORPORATION, MAZDA MOTOR CORPORATION
    Inventors: Tooru Matsumoto, Katsuhide Akimoto, Takahito Masuko, Keita Takagi, Tatsuhiro Ito, Yuki Sato, Ryo Teramoto, Takafumi Nishio
  • Patent number: 11385098
    Abstract: A system for determining a characteristic of a laser includes a collection housing receiving a laser beam comprising a first pulse, a second pulse and a time period between the first pulse and the second pulse. A photon counting detector receives photons from the laser beam disposed to generate photon signals from the laser beam and generating a start signal. A fast diode generates a stop signal to provide a time reference of counted photons ns. A controller is coupled to the photon counting detector and the fast diode. The controller counts photons from the photon counting detector occurring during the time period between the first and second pulse and generates a first output signal corresponding to a power during the time period between the first pulse and the second pulse.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: July 12, 2022
    Assignee: Board of Trustees of Michigan State University
    Inventor: Marcos Dantus
  • Patent number: 11387777
    Abstract: An active bypass control device and an active bypass control method for a photovoltaic module are provided. The device includes a power source, a sampling unit, a controller, N first driving circuits, and N first controllable switches. Each first controllable switch is connected between one pair of bypass ports and includes a first switch and a first diode that are antiparallel. The first diode is reversely connected between the pair of bypass ports, and a control end of the first switch is connected to the controller via the corresponding first driving circuit. Based on a sampling signal provided by the sampling unit, the controller determines whether analog quantity information of the first controllable switch meets a predetermined bypass condition. If the predetermined bypass condition is met, the first switch is controlled to be turned on by using the first driving circuit.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: July 12, 2022
    Assignee: SUNGROW POWER SUPPLY CO., LTD.
    Inventors: Zongjun Yang, Yanfei Yu, Hua Ni
  • Patent number: 11383514
    Abstract: A die for a printhead is described herein. The die includes a number of fluid feed holes disposed in a line parallel to a longitudinal axis of the die. A number of fluidic actuators are disposed in a line parallel to the fluid feed holes. A crack detector trace is routed between each of the plurality of fluid feed holes.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: July 12, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James Michael Gardner, Anthony M. Fuller, Scott A. Linn
  • Patent number: 11385079
    Abstract: A method and apparatus for obtaining a valid peak from an output signal of a resolver sensor are provided. The method includes inputting an excitation signal to a resolver sensor, receiving a resolver signal from the resolver sensor, receiving a high peak and a low peak from the received resolver signal, determining whether the high peak or the low peak falls within an effective range, and defining the high peak or the low peak as a valid peak when the high peak or the low peak falls within the effective range.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: July 12, 2022
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventor: Sung-Hoon Bang
  • Patent number: 11353494
    Abstract: A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: June 7, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sigfredo E. Gonzalez Diaz, Benjamin Lee Amey, Patrick Michael Teterud, Hung Nguyen
  • Patent number: 11347948
    Abstract: A payment reader is provided for use in a payment system. The payment reader includes a housing, a non-conductive cover covering the housing and forming an internal compartment, electronic circuitry within the internal compartment and surrounded by the cover, and a mesh of conductive traces provided on the cover and in communication with the electronic circuitry. The cover has an upper wall and interconnected side walls depending downwardly from the upper wall. The lower surface of the upper wall which faces the internal compartment has its entire surface area which is formed of at least one three-dimensional shape which extends outwardly from an x-y plane in the z-direction.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 31, 2022
    Assignee: Molex, LLC
    Inventors: Tsuey Choo Lily Chang, Yan Pan, Steven Zeilinger
  • Patent number: 11342389
    Abstract: A display panel, a display device comprising the display panel, and a method for detecting a defect thereof are provided. The method can include preparing the display panel including a first sensing pattern connected to a touch sensor and a second sensing pattern extended from a light emitting device in an active area of the display panel to a non-active area of the display panel, wherein at least one of the first sensing pattern and the second sensing pattern protrudes farther than an end of an encapsulation stack, and the encapsulation stack covers a second electrode of the light emitting device in the active area; detecting a parasitic capacitance between the touch sensor and the second electrode in the active area; comparing the parasitic capacitance with a designated value; and determining that the display panel is defective based on a result of the comparing.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 24, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Eun-Ah Song
  • Patent number: 11327476
    Abstract: A computer implemented method includes turning off a sensor, receiving fall curve data from the sensor, and comparing the received fall curve data to a set of fall curve signatures to identify the sensor or a sensor fault.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 10, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Tusher Chakraborty, Akshay Uttama Nambi Srirangam Narashiman, Ranveer Chandra, Rahul Anand Sharma, Manohar Swaminathan, Zerina Kapetanovic, Jonathan Appavoo
  • Patent number: 11329675
    Abstract: A radio frequency module includes a transmit filter of Band A and Band B, a transmit amplifier, and a switch circuit and can perform CA using a transmit signal of Band A and a receive signal of Band B, a transmit band of Band B including a receive band of Band C. The switch circuit includes a switch switching connection between a common terminal and a first selection terminal, a switch switching connection between the common terminal and a second selection terminal, and a switch switching connection between the second selection terminal and a third selection terminal. The common terminal is connected to the transmit amplifier. The first selection terminal is connected to the transmit filter of Band A. The second selection terminal is connected to the transmit filter of Band B. The third selection terminal is connected to a receive path of Band C.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 10, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenji Tahara
  • Patent number: 11315841
    Abstract: A pattern design for defect inspection, the pattern design including a first floating conductive line; a second floating conductive line; and a grounded conductive line disposed between the first floating conductive line and the second floating conductive line. The first floating conductive line, the second floating conductive line, and the grounded conductive line are divided into a main pad region, a plurality of subregions, a plurality of sub-pad regions, and a ground region. The main pad region is positioned at a first end portion of the pattern design. The ground region is positioned at a second end portion of the pattern design. The plurality of subregions and the plurality of sub-pad regions are positioned between the main pad region and the ground region.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: April 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Soo Baek, Jin Myoung Lee, Min Soo Kang, Hyun Ah Roh, Bo Young Lee
  • Patent number: 11315453
    Abstract: An electronic device includes a substrate having a top surface, a bottom surface and a side surface between the top surface and the bottom surface, and a test circuit disposed on the substrate. The test circuit extends from the top surface to the bottom surface through the side surface of the substrate and has a current terminal for an ammeter and a voltage terminal for a voltmeter, both of which are disposed on the bottom surface.
    Type: Grant
    Filed: November 8, 2020
    Date of Patent: April 26, 2022
    Assignee: InnoLux Corporation
    Inventor: Shuhei Hosaka
  • Patent number: 11287858
    Abstract: A display device may include a display panel including a signal pad and a circuit board including a connection pad having a first connection pad portion and a second connection pad portion. The second connection pad portion may be thicker than the first connection pad portion and may not be overlapped with the first connection pad portion in a plan view. The connection pad may be in contact with the signal pad. A first surface roughness between the first connection pad portion and the signal pad may be greater than a second surface roughness between the second connection pad portion and the signal pad.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoungyong Kim, Seongtaek Lee, Young-Min Park
  • Patent number: 11243242
    Abstract: A system for testing a traction block, such as a railway traction block, includes two zones that are physically separated from one another, an operational zone located in a container and divided into at least two parts. One part is a command part accessible by an operator during testing, and the other part is a high-voltage part inaccessible during testing. The system also includes a test zone located outside the container, and configured to receive the traction block to be tested. The test zone is able to be supplied with electricity during the test by the operational zone using dedicated connections.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 8, 2022
    Assignee: ALSTOM Transport Technologies
    Inventor: Laurent Collongues
  • Patent number: 11238301
    Abstract: A computer-implemented method of detecting a foreign object on a background object in an image is provided. The computer-implemented method includes extracting image features of the image based on image characteristics of the background object and a suspected foreign object; detecting a salient region in the image based on a human visual attention model; generating a salient region mask based on detection of the salient region; obtaining the image features in a region surrounded by the salient region mask; perforating feature combination and feature vector length normalization on the image features of the region surrounded by the salient region mask to generate normalized feature vectors; and identifying the suspected foreign object using an image classifier, wherein the image classifier uses the normalized feature vectors as input for identifying the suspected foreign object.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: February 1, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Huanhuan Zhang, Jingtao Xu, Xiaojun Tang, Hui Li
  • Patent number: 11221361
    Abstract: An example test system includes an output stage to source at least one of voltage or current to a channel of a test instrument; a tracking circuit to detect a channel voltage following the output stage and to control a supply voltage to the output stage based on the channel voltage; and a controller to determine a power dissipation of the output stage based on the supply voltage and the channel voltage, and to control the output stage based on the power dissipation in the output stage.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 11, 2022
    Assignee: TERADYNE, INC.
    Inventors: Jason A. Messier, Bryce M. Wynn, William Bowhers
  • Patent number: 11215676
    Abstract: The present invention relates to a power circuit, which comprises a detection circuit. The detection circuit includes an abnormality detection circuit. The abnormality detection circuit is coupled to an input terminal or/and an output terminal of the power circuit. An input power is provided to the input terminal, and an output power is provided to the output terminal. The abnormality detection circuit controls the paths from a plurality of energy storage elements to the input terminal and the output terminal of the power circuit. The energy storage elements store the energy of the input power to generate the output power. The abnormality detection circuit detects the state of the input power or/and the output power, and cuts off the paths from a portion of the energy storage elements to the input terminal and the output terminal.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: January 4, 2022
    Assignee: Forcelead Technology Corp.
    Inventors: Ta-Hung Chiu, Mao-Hsiang Yeh
  • Patent number: 11215640
    Abstract: There is provided a prober provided with a plurality of inspection chambers. Each inspection chambers includes: a probe card having a plurality of probes; a probe card holder configured to hold the probe card; a chuck top configured to place a cleaning wafer thereon; an aligner configured to drive the chuck top in a vertical direction when the probe card is cleaned using the cleaning wafer; a seal mechanism configured to allow a sealed space to be provided between the probe card holder and the chuck top; a pressure sensor configured to detect an internal pressure of the sealed space, which fluctuates with an operation of the chuck top driven by the aligner; and an electro-pneumatic regulator configured to control the internal pressure of the sealed space by performing an intake or exhaust operation with respect to the sealed space based on the internal pressure detected by the pressure sensor.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 4, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Jun Fujihara
  • Patent number: 11204368
    Abstract: A first signal line pattern has one end electrically connected to a first connector. A second signal line pattern has one end electrically connected to a second connector. The second signal line pattern has the other end facing the other end of the first signal line pattern. A conductive block has a convex portion. The convex portion of the conductive block is electrically connected to a third portion of the conductive pattern positioned between the other end of the first signal line pattern and the other end of the second signal line pattern of the wiring board.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: December 21, 2021
    Assignee: Yokowo Co., Ltd.
    Inventors: Masaki Noguchi, Takahiro Nagata, Tsuyoshi Yamato
  • Patent number: 11181566
    Abstract: A detection circuit of electromagnetic fault injection includes: a shielding layer configured to shield interference; at least one group of metal-oxide semiconductor MOS transistors, where a source end of the at least one group of MOS transistors is connected to the shielding layer; at least one latch, where a drain end of the at least one group of MOS transistors is connected to an input end of the at least one latch; and a signal output module, where an input end of the signal output module is connected to an output end of the at least one latch. The detection circuit could detect in real time and alarm electromagnetic fault injection in time to ensure robustness and safety of a chip.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 23, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Jianfeng Xue, Jiang Yang
  • Patent number: 11184015
    Abstract: In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: November 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ankur Chauhan, Abhrarup Barman Roy
  • Patent number: 11156709
    Abstract: A radar system includes a first radar chip with a first RF contact, a second radar chip with a second RF contact, an RF signal path connecting the first RF contact to the second RF contact, and a local oscillator arranged in the first radar chip and configured to generate an RF oscillator signal, and which is coupled to the first RF contact to transmit the RF oscillator signal to the second radar chip. A feedback circuit arranged in the second radar chip is switchably connected to the second RF contact and is configured to reflect at least part of the RF oscillator signal arriving over the RFRF signal path as an RF feedback signal. A measurement circuit, arranged in the first radar chip, coupled to the first RF contact via a coupler receives the RF feedback signal and is configured to determine a signal that represents a phase shift.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: October 26, 2021
    Inventors: Alexander Melzer, Bernhard Gstoettenbauer, Alexander Onic, Clemens Pfeffer, Christian Schmid
  • Patent number: 11146201
    Abstract: A current value determination device provided with: a capacitor current computation unit for computing the capacitor current of a capacitor included in a high-voltage circuit that drives a motor, on the basis of the input voltage of an inverter included in the high-voltage circuit and the revolution speed of the motor; and a capacitor current determination unit for determining the value of capacitor current on the basis of the input voltage of the inverter, the revolution speed of the motor, the capacitor current computed by the capacitor current computation unit, and a prescribed model for determination.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: October 12, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES THERMAL SYSTEMS, LTD.
    Inventors: Makoto Hattori, Takayuki Takashige, Kyohei Watanabe
  • Patent number: RE48963
    Abstract: A connection device for computing devices is described. In one or more implementations, a connection device comprises a plurality of connection portions that are physically and communicatively coupled, one to another. Each of the plurality of connection portions has at least one communication contact configured to form a communicative coupling with a respective one of a plurality of computing devices and with at least one other communication contact of another one of the connections portions to support communication between the plurality of computing devices. Each of the plurality of connection portions also includes a magnetic coupling device to form a removable magnetic attachment to the respective one of the plurality of computing devices.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 8, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Steven Nabil Bathiche, Flavio Protasio Ribeiro, Nigel Stuart Keam, Bernard K. Rihn, Panos C. Panay, David W. Voth