Of Individual Circuit Component Or Element Patents (Class 324/537)
  • Patent number: 10447029
    Abstract: Disclosed is a connection circuit capable of detecting erroneous wiring of an interconnect device in order to prevent a safety fuse from being melted and quickly perform an overcurrent protection in the event of erroneous wiring or the like. In this connection circuit of the interconnect device, a preliminary wiring check operation is performed when a power control unit receives a power-on signal. It is detected whether or not a power line and a ground line are short-circuited in the preliminary wiring check operation. When the power line and the ground line are not short-circuited, an operation instruction is output from the power control unit to a power unit. As a result, power is turned on after it is checked whether or not the power line and the ground line are short-circuited in advance. Therefore, it is possible to prevent the safety fuse from being melted.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 15, 2019
    Assignee: Fanuc Corporation
    Inventor: Taisei Fujimoto
  • Patent number: 10440825
    Abstract: In various embodiments, a chip card module is provided. The chip card module includes a chip card module contact array having six contact pads that are arranged in two rows having three contact pads each in accordance with ISO 7816, and three additional contact pads that are arranged between the two rows. Each additional contact pad is electrically conductively connected to a respective associated contact pad from a row from the two rows.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pueschner, Peter Stampka, Jens Pohl, Marcus Janke
  • Patent number: 10436616
    Abstract: A system has at least one sensor and a control for analyzing a signal from the sensor. The sensor is operable to send a signal indicative of a presence of a particular occurrence to the control. The sensor also sends a background signal even without the presence of the particular occurrence. The control evaluates the background signal to identify a need for calibration. A method is also disclosed.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 8, 2019
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Kenneth Carney
  • Patent number: 10429437
    Abstract: A method of operating a data processing system to generate a diagram indicative of an experimental setup includes a device to be tested (DUT) and a plurality of test instruments is disclosed. The method includes detecting a first test instrument that is connected to the data processing system and determining connection points to the first test instrument. A script that specifies tests for the DUT using the plurality of test instruments and includes instructions specifying measurements to be made by the first test instrument is examined. A first connection between the DUT and the first test instrument is determined. An initial diagram on a display controlled by the data processing system is generated. The initial diagram includes a first node representing the first test instrument, a second node representing the DUT and a line representing the first connection between the first and second nodes.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: October 1, 2019
    Assignee: Keysight Technologies, Inc.
    Inventor: Jonathan Helfman
  • Patent number: 10429441
    Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Tapan Jyoti Chakraborty, Alvin Leng Sun Loke, Hong Dai, Thomas Clark Bryan
  • Patent number: 10389291
    Abstract: A motor drive device includes an inverter that drives a motor, a power source smoothing capacitor of the inverter, and a control unit that controls the inverter to drive the motor. The control unit precharges the capacitor with a power source voltage, and calculates a capacity value of the capacitor, based on a ratio of the power source voltage and a voltage with which the capacitor is charged, or an amount of time taken until the voltage with which the capacitor is charged, after the passage of a predetermined amount of time from the start of the precharge, reaches a voltage corresponding to the power source voltage. The control unit performs torque limitation of the motor when the capacity value of the capacitor has decreased.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 20, 2019
    Assignee: Hitachi Automotive Sytems, Ltd.
    Inventor: Yawara Kato
  • Patent number: 10382029
    Abstract: The disclosure relates to a control device for controlling a load, wherein the control device comprises the following elements: a first current control valve between a first port of the load and a first potential of an operating voltage; a second current control valve between a second port of the load and a second potential of the operating voltage; a processor configured to actuate the second current control valve when the first current control valve is closed, in order to control a current through the load; and a sampling device for determining an input voltage through the first current control valve, wherein the processor is configured to determine the presence of a short circuit between the first port and the first potential if the input voltage does not increase when the first current control valve is opened gradually.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 13, 2019
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventors: Paul Bange, Thomas Maier
  • Patent number: 10379153
    Abstract: A printed circuit board (PCB) test coupon for thermal exposure and electrical testing includes a double sided or multi-layer substrate with a plurality of vias formed within the substrate of the test coupon (blind, buried, stacked vias) or extending through the entire substrate (through hole/via) from a first surface on the first side of the plated hole/via to a second surface on the second side of the plated hole/via. Each of a first plurality of trace patterns interconnect a subset of the plurality of plated holes/vias on the first side of the plated holes/vias, and each of a second plurality of trace patterns interconnect a different subset of the plurality of plated holes/vias on the second side of the plated holes/vias. The first and second pluralities of trace patterns have different patterns and connect to connection points in a connector pattern defined in the substrate.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 13, 2019
    Assignee: Greater Asia Pacific Limited
    Inventor: Robert Neves
  • Patent number: 10352812
    Abstract: A circuit, a method, and a computer program configured to detect mechanical stress and a circuit, a method, and a computer program configured to monitor safety of a system is disclosed. The detection circuit is configured to monitor a mechanical stress level of a semiconductor circuit. The detection circuit includes a stress monitor circuit configured to monitor a signal comprising mechanical stress level information of the semiconductor circuit, a reference circuit to generate a reference signal, and a calibration circuit configured to modify at least one of the stress signal or the reference signal based on calibration information for the semiconductor circuit to obtain a at least one modified signal.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Dirk Hammerschmidt, Friedrich Rasbornig, Michael Strasser
  • Patent number: 10352987
    Abstract: A solid state switch power emulator circuit, the circuit including a high voltage section including a high voltage power supply (HVPS); a high voltage capacitor (HVC) electronically connected to the HVPS in parallel; a high voltage switch (HVS) electronically connected to the HVC and the HVPS in series; and a high voltage load (HVL) electronically connected to the HVS in series; a low voltage section including a low voltage power supply (LVPS); a low voltage capacitor (LVC) electronically connected to the LVPS in parallel; a low voltage switch (LVS) electronically connected to the LVPS and the LVC in series; a low voltage load (LVL) electronically connected to the LVS in series; and a high voltage diode (HVD) electronically connected to the LVL in series, wherein voltage levels associated with the low voltage section are less than voltage levels associated with the high voltage section.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: July 16, 2019
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Richard L. Thomas, Jr.
  • Patent number: 10352983
    Abstract: Disclosed are devices, systems and methods for assessing the integrity of electrical connections between elements of interfacing electronic devices. In some aspects, a system includes an analysis device having electronics that interface with an assay cartridge inserted into the analysis device, wherein the analysis device is configured to conduct a preflight test in which impedance values for each circuit between the assay cartridge and analysis device are rearranged and assessed to determine the electrical connection integrity of the assay cartridge to the analysis device prior to implementing the assay.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: July 16, 2019
    Assignee: GENMARK DIAGNOSTICS, INC.
    Inventor: Roger Harry Taylor
  • Patent number: 10330703
    Abstract: Probe systems and methods including electric contact detection. The probe systems include a probe assembly and a chuck. The probe systems also include a translation structure configured to operatively translate the probe assembly and/or the chuck and an instrumentation package configured to detect contact between the probe system and a device under test (DUT) and to test operation of the DUT. The instrumentation package includes a continuity detection circuit, a test circuit, and a translation structure control circuit. The continuity detection circuit is configured to detect electrical continuity between a first probe electrical conductor and a second probe electrical conductor. The test circuit is configured to electrically test the DUT. The translation structure control circuit is configured to control the operation of the translation structure. The methods include monitoring continuity between a first probe and a second probe and controlling the operation of a probe system based upon the monitoring.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: June 25, 2019
    Assignee: FormFactor Beaverton, Inc.
    Inventors: Sia Choon Beng, Kazuki Negishi
  • Patent number: 10315531
    Abstract: An electrical system for a vehicle includes a high-voltage DC power source electrically connected to a high-voltage bus, a first controller disposed to control electric power flow between the high-voltage bus and a first actuator, and a second controller disposed to control electric power flow between the high-voltage bus and a second actuator. A communication link is disposed to effect communication between the first controller and the second controller. An inertial sensor communicates with the second controller. The second controller includes an instruction set to monitor and determine a request to discharge the high-voltage bus based upon communication from the sensor. Upon determining that the first controller is incapable of discharging the high-voltage bus, the second actuator is controlled to discharge the high-voltage bus.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: June 11, 2019
    Assignee: GM Global Technology Operations LLC.
    Inventors: David J. Mifsud, Marjorie A. Bassham, Kyle Holihan, Emil Francu
  • Patent number: 10302689
    Abstract: An electronic device having at least one connector for at least one wired sensor. The device has a sensor break detection unit, wherein the sensor break detection unit comprises a pulse generator outputting pulses of different polarity being adapted to output at least one electrical signal to the wired sensor and detector means for detecting a response signal from the wired sensor.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 28, 2019
    Assignee: Eurotherm Limited
    Inventors: Jonathan Rich, Mike Newsome, Robert Donarski
  • Patent number: 10288664
    Abstract: The invention relates to a method and to an electrical protection device for detecting a disconnection of a protective conductor connection with a subsystem in ungrounded and grounded power supply systems and in a grounded power supply system comprising a converter system. The invention is based on the idea that the disconnection of the protective conductor connection with a subsystem will reduce the sum of the network leakage capacitances of the power supply system by the value of the network leakage capacitance of the subsystem. The necessary distinction between a subsystem in operation having a disconnected protective conductor connection and a shut-off subsystem is made by evaluating the current total power consumed via the power supply system. In the case of a converter system connected to the subsystem, the protective conductor disconnection is detected by examining the leakage current spectra that are characteristic of the converter system.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 14, 2019
    Assignee: BENDER GMBH & CO. KG
    Inventors: Dieter Hackl, Harald Sellner
  • Patent number: 10263546
    Abstract: A method for determining a motor current of an electric motor drive with a power source and with an electric motor and with a power converter connected therebetween, wherein an input current of the power source is converted by a pulse width modulated control of a number of semiconductor switches of the power converter into the motor current, wherein an intermediate circuit current of an intermediate circuit of the power source is influenced during the pulse width modulated control of the semiconductor switches, wherein an inductive voltage change is detected at a measuring point of the intermediate circuit due to the influence on the intermediate circuit current, and wherein a value for the generated motor current is determined based on the pulse width modulated control of the semiconductor switches and the inductive voltage change detected at the measuring point.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 16, 2019
    Assignee: Brose Fahrzeugteile GmbH & Co. Kommanditgesellschaft, Wuerzburg
    Inventor: Johannes Schwarzkopf
  • Patent number: 10215810
    Abstract: A battery monitoring system includes: an input circuit to which voltage signals of battery cells are inputted; a multiplexer selecting a battery cell for voltage detection from the battery cells, selecting voltage signals inputted from the input circuit, and outputting the selected voltage signals; first and a second voltage measuring circuits simultaneously measuring voltages based on the voltage signals in first and second routes outputted from the multiplexer; a comparator comparing measurement results by the first voltage measuring circuit and by the second voltage measuring circuit; and a control unit that judges, on a basis of a comparison result by the comparator, at least one of a voltage of each battery cell, an operation check of equalizing the voltages of the battery cells, a presence or absence of a disconnection of a detection line of each battery cell, and a presence or absence of a failure in the multiplexer.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 26, 2019
    Assignee: YAZAKI CORPORATION
    Inventor: Takaaki Izawa
  • Patent number: 10209308
    Abstract: A MV switching device (100) comprising: one or more electric poles, each comprising a movable contact (16) and a fixed contact (17) adapted to be coupled or uncoupled during the switching operations of said switching device; and an electromagnetic actuator (13) operatively coupled to the movable contacts of the electric poles, said electromagnetic actuator having at least an excitation winding (152); power supply means (60) for supplying electric power to said electromagnetic actuator; a power drive circuit (1) for driving said electromagnetic actuator, said power drive circuit comprising sensing means for providing signals indicative of the currents flowing along the circuit branches of said power drive circuit and of the voltages at the terminals of said power drive circuit.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: February 19, 2019
    Assignee: ABB SCHWEIZ AG
    Inventors: Andrea Ricci, Gabriele Valentino De Natale, Marco Testa
  • Patent number: 10200186
    Abstract: A system is connected to a single-wire communication line to perform bidirectional communication between a master side and a slave side, and an input clock-side transistor connected between a GND level and the communication line performs switching according to an input clock. A first transistor is connected between a first potential and the communication line, a second transistor has one end connected to a second potential, and a master-side resistor is connected between the other end of the second transistor and the other end of a third transistor. A fourth transistor is connected between the communication line and a third potential equal to or higher than the first potential, and a slave-side resistor is connected between the communication line and the GND level.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 5, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masashi Akahane
  • Patent number: 10178734
    Abstract: An LED lighting circuit for detecting individual LED failure, including a lighting unit including a plurality of LEDs connected in series, and a plurality of LED sensors each associated with a respective one of the LEDs. Also included is a lighting unit status signal generator coupled to the plurality of LED sensors configured to provide a status signal indicating a fault when any individual LED is short circuited.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 8, 2019
    Assignee: Valeo North America, Inc.
    Inventors: Monji Moumen, Sylvain Larribe
  • Patent number: 10175292
    Abstract: In an embodiment, a method of testing a radio frequency integrated circuit (RFIC) includes generating high-frequency test signals using the on-chip test circuit, measuring signal levels using on-chip power detectors, and controlling and monitoring the on-chip test circuit using low-frequency signals. The RFIC circuit is configured to operate at high frequencies, and an on-chip test circuit that includes frequency generation circuitry configured to operate during test modes.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 8, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Johann-Peter Forstner
  • Patent number: 10175296
    Abstract: A testing arrangement is provided which comprises: a board assembly comprising (i) a first connector configured to receive a first component while the board assembly is to operate in a regular mode of operation and (ii) a second connector configured to receive a second component while the board assembly is to operate in the regular mode of operation; a first test card configured to be attached to the first connector while the board assembly is to operate in a test mode of operation; and a second test card configured to be attached to the second connector while the board assembly is to operate in the test mode of operation, wherein while the board assembly is to operate in the test mode of operation, the first test card is configured to communicate with the second test card to facilitate testing of the board assembly.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Joseph W. Batz, Joseph R. Yuhas, Christopher Lewis, Elizabeth M. Yamada, Michael V. Hill, Ralph E. Rossknecht
  • Patent number: 10175281
    Abstract: The invention relates to a device for predicting faults in a harness formed by a plurality of cables gathered together, in particular electrical cables, comprising a protective sheath (10) intended to surround the harness, the sheath (10) comprising a plurality of braided elements (100), said braided elements (100) being braided together to form a tubular sheath, each braided element (100) comprising a plurality of longitudinal braiding strands (101) arranged to form a web, characterised in that the sheath (100) comprises at least one electrically conductive detection strand (102), said detection strand (102) being arranged with the braiding strands (101) of a braided element (100) so as to be incorporated into the web forming said braided element (100), the detection strand (102) being electrically insulated from the braiding strands (100) of said braided element (100).
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: January 8, 2019
    Assignee: SAFRAN ELECTRICAL & POWER
    Inventors: Jerome Genoulaz, Stephane Brendle, Michel Dunand
  • Patent number: 10139454
    Abstract: A test device is provided. The test device includes test components, power supplies, an alternating current (AC) power detection circuit and an alert module. The power supplies convert an AC power through a first wire, a second wire and an earth wire to a direct current (DC) power and supply the DC power to the test components. The AC power detection circuit receives the AC power through the first wire, the second wire and the earth wire to determine whether both of voltage differences between the first wire and the earth wire and between the second wire and the earth wire is outside of respective predetermined ranges. When both of the voltage differences are outside of the corresponding predetermined range, the AC power detection circuit controls the alert module to generate an alerting signal.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: November 27, 2018
    Assignee: Test Research, Inc.
    Inventors: Hsin-Wei Huang, Chien-Wei Chen
  • Patent number: 10128842
    Abstract: Methods, systems, and devices for output impedance calibration for signaling are described. Techniques are provided herein to adjust impedance levels associated with data transmitted using signaling and related techniques. In some cases, the signaling may be multi-level signaling. Such signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 13, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Feng Lin
  • Patent number: 10123417
    Abstract: A dual printed circuit board assembly, a printed circuit board, and a modular printed circuit board are provided. The printed circuit board includes a plurality of first connection points. The modular printed circuit board includes a plurality of second connection points. The modular printed circuit board is adapted to be mounted on the printed circuit board and includes a sensing unit, a first detecting unit, and a first notifying unit. The sensing unit outputs a detecting voltage according to a contact state between the first connection points and the second connection points. The first detecting unit determines whether the first connection points are respectively connected to the corresponding second connection points according to the detecting voltage. When one of the first connection points is not connected to the corresponding one of the second connection points, the first detecting unit controls the first notifying unit to issue a notification.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 6, 2018
    Assignee: Wistron NeWeb Corp.
    Inventors: Cheng-Hsien Hsu, Chih-Yuan Chiang, Cheng-Huang Chen
  • Patent number: 10114068
    Abstract: An integrated circuit capable of monitoring aging effects on an integrated circuit device is disclosed. The integrated circuit includes a control circuit that obtains a clock signal at different frequencies. A sense circuit may receive the clock signal. First and second control signals may be asserted on the integrated circuit with the control circuit. The first control signal may activate a stress mode, and the second control signal may activate a measurement mode. During stress mode, the sense circuit may receive the clock signal. Any changes in predetermined electrical parameters of one or more transistors in the sense circuit may be monitored and measured during the measurement mode. Aging compensation may be performed when aging effect is detected on the sense circuit.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: October 30, 2018
    Assignee: Altera Corporation
    Inventors: Christopher Sun Young Chen, Jeffrey T. Watt
  • Patent number: 10109369
    Abstract: A test device for testing a plurality of semiconductor devices, each of which includes a plurality of functional blocks and a plurality of test pads coupled to the functional blocks. The test device includes a test header including a plurality of test channels, a plurality of test sites on which the semiconductor devices are installed, and a test control device. The test control device allocates the test channels to at least some of the test pads of the semiconductor devices to test more than two of the semiconductor devices simultaneously. The number of the test sites is greater than a value generated by dividing the number of the test channels by the number of the test pads of each of the semiconductor devices.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Shik Kang, Hyun-Sil Lim, Min-Suk Choi
  • Patent number: 10082856
    Abstract: A device may select a power supply module (PSM), from a plurality of PSMs that operate in a current sharing mode, for performing a health check. The device may perform the health check on the selected PSM by iteratively modifying an output voltage of the selected PSM and monitoring for a corresponding modification in an output current of the selected PSM. The device may determine whether the selected PSM is capable of delivering a particular load without a failure based on performing the health check. The device may perform an action based on whether the selected PSM is capable of delivering the particular load without the failure.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: September 25, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: David K. Owen, Jaspal S. Gill, Katsuhiro Okamura, Sylvia Toma, Subramanyam Tallak
  • Patent number: 10067178
    Abstract: A system is disclosed. The system includes an antenna and a processor. The processor has at least four ports: a first input port coupled to a first portion of the continuity component; a first output port coupled in series to a first resistor coupled to the first portion of the antenna and to ground via a second resistor; a second output port coupled through a third resistor to the first portion of the antenna; and a second input port coupled to a second portion of the antenna and through a fourth resistor to ground. The processor is operable to activate and deactivate the appropriate ports to put the processor in one of three operating modes: an AC detection mode, an AC self-test mode, and a continuity test mode.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 4, 2018
    Assignee: SOUTHWIRE COMPANY, LLC
    Inventors: Richard Allan Duke, John Lawrence Payne
  • Patent number: 10048313
    Abstract: Systems and methods for semiconductor design evaluation. IC layout information of a circuit design is received, and the circuit design is decomposed into smaller circuit pieces. Each circuit piece has IC layout information and a netlist. For each circuit piece, a set of strike models is selected based on the layout information and the net-list of the circuit piece and received radiation environment information. Each strike model has circuit components with voltage values corresponding to a respective particle strike. For each selected strike model of a circuit piece: a radiation susceptibility metric is determined by comparing functional results of simulation of the of the strike model with functional results of simulation of the circuit piece. For each circuit piece, a radiation susceptibility metric is determined based on the radiation susceptibility metrics generated for each selected strike model of the circuit piece.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 14, 2018
    Assignee: Lucid Circuit, Inc.
    Inventor: Michel D Sika
  • Patent number: 10046645
    Abstract: An ECU (Electronic Control Unit) controls a converter such that the converter is stopped when a fail signal FCV is output. The ECU further controls an inverter such that power operation and regenerative operation by a motor generator are performed in a state in which output of an ON signal to an IGBT (Insulated Gate Bipolar Transistor) element is set non-executable, when the fail signal FCV is output due to the IGBT element becoming short-circuited.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: August 14, 2018
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tomoko Oba, Atsushi Nomura
  • Patent number: 10044266
    Abstract: The proposed disclosure combines peak-mode monitoring with valley-mode control, in a Buck switching converter, by means of a peak-current sampling circuit, not to turn the high side device off, but to control a slow loop, which in turn controls a variable offset incorporated into the loop control current. This helps the loop control current define the exact peak current, regardless of what other offsets, compensation ramp or peak-to-peak current ripple, are applied to the loop control current. The peak current is determined by an operational transconductance amplifier (OTA), whose maximum current is clamped to a programmed value. The loop control current is most likely implemented using a digital successive approximation register (SAR) system, but may also be implemented using a slow analog control loop.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 7, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Mark Childs, Michele DeFazio, Carsten Barth
  • Patent number: 10020661
    Abstract: A voltage detection device for detecting a voltage across both ends of each of plural unit batteries which are connected to each other in series. The voltage detection device includes lowpass filters which are connected to the respective unit batteries, a first voltage detector which detects a voltage across both ends of each of the unit batteries that is supplied via a corresponding lowpass filter, a second voltage detector which detects a voltage across both ends of each of the unit batteries that is supplied without passage through the corresponding lowpass filter, and a failure detector which detects whether the lowpass filter is failing by comparing a voltage detection value detected by the first voltage detector with a voltage detection value detected by the second voltage detector.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: July 10, 2018
    Assignee: Yazaki Corporation
    Inventors: Hironao Fujii, Takaaki Izawa
  • Patent number: 10012718
    Abstract: The present invention is directed to an electrical wiring device that includes a test circuit that is configured to generate a recurring simulated fault signal. A detection circuit is configured to generate a test detection signal in response to the recurring simulated fault signal. An end-of-life monitor circuit is configured to generate an end-of-life detection signal if the test detection signal is not generated within a first predetermined period of time. At least one indicator is configured to emit an indication signal in response to the end-of-life detection signal. A response mechanism is configured to decouple the plurality of line terminals from the plurality of load terminals after a second predetermined period of time has elapsed following the end-of-life detection signal.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: July 3, 2018
    Assignee: PASS & SEYMOUR, INC.
    Inventors: Bruce F. Macbeth, David A. Finlay, Sr., Jeffrey C. Richards
  • Patent number: 10014899
    Abstract: In described examples of a device with built-in-self-test, a multiplexer has at least first and second input terminals and is coupled to receive a first input signal at the first input terminal, a second input signal at the second input terminal, and selection signals. Also, the multiplexer is coupled to output: the first input signal in response to a first combination of the selection signals; the second input signal in response to a second combination of the selection signals; and an analog summation of the first and second input signals in response to a third combination of the selection signals.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert Floyd Payne, Lambert Jacob Helleman
  • Patent number: 10013660
    Abstract: A method and control system are disclosed for optimizing load scheduling for a power plant having one or more generation units. The method can include analyzing the operating state of one or more components of generation units in terms of one or more risk indices associated with one or more components of generation units; updating an objective function that reflects the state of one or more components of generation units; solving the objective function to optimize a schedule of the one or more generation units and operating state of one or more components of generation units; and operating the one or more generation units at optimized schedule and operating state.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: July 3, 2018
    Assignee: ABB Research Ltd
    Inventors: Gopinath Selvaraj, Senthil Kumar Sundaram, Mohan Kumar Shanmugam, Shrikant Bhat
  • Patent number: 10002003
    Abstract: A method for presenting initialization progress of hardware in a server, and a server where, before a basic input/output system (BIOS) runs to a preset process, an out-of-band central processing unit (CPU) in a hardware system in which a baseboard management controller (BMC) runs establishes a connection to a graphics card using a signal selection switch, the BIOS sends presentation information for representing initialization progress of hardware included in a server to the BMC, and then, the BMC presents the presentation information using the graphics card. Therefore, the presentation information can be always presented in an entire process in which the BIOS initializes the hardware in the server.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 19, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Fei Zhang, Jianfeng Yang
  • Patent number: 10001521
    Abstract: Microwave transistor test fixtures, both micro-strip and coaxial, include integrated wideband directional signal sensors/couplers and allow the detection of the main signal and its harmonic components, injected into and delivered by a transistor in high power operation mode, by using a phase-calibrated network or signal analyzer and allows this way the reproduction of real time signal waveforms. The fixtures are best calibrated using equivalent TRL calibrated fixtures allowing overcoming the incompatibility of the internal ports connecting to the transistor terminals with coaxial cables attached to VNA.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: June 19, 2018
    Inventor: Christos Tsironis
  • Patent number: 9990451
    Abstract: Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising: identifying a processing window limiting pattern (PWLP) from the pattern; determining a processing parameter under which the PWLP is processed; and determining or predicting, using the processing parameter, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the PWLP with the device manufacturing process.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: June 5, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Stefan Hunsche, Venu Vellanki
  • Patent number: 9989570
    Abstract: A method for evaluating a device including a plurality of electric circuits has: a step of finding a first malfunction frequency property for individual electric circuits included in the device, the first malfunction frequency property representing the magnitude of a critical noise signal at which each electric circuit causes a malfunction; and a step of finding a second malfunction frequency property based on the first malfunction frequency property found for each of the electric circuits, an equivalent circuit of the entire device, and an equivalent circuit of each of the electric circuits, the second malfunction frequency property representing the magnitude of a critical noise signal at which the entire device causes a malfunction.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: June 5, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Noriaki Hiraga
  • Patent number: 9987932
    Abstract: A battery system includes: a power detector that detects output power from an external power source; a charging mechanism that charges a main battery by external power; a temperature raising mechanism that raises a temperature of the main battery to a temperature not lower than a reference temperature; and a controller that controls the charging mechanism and the temperature raising mechanism, wherein when the detected output power is lower than a reference power, the controller prohibits a temperature raising process with an SOC of the main battery lower than a charge reference value and performs a charging process.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 5, 2018
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takashi Murata, Yusuke Kuruma
  • Patent number: 9977065
    Abstract: In at least one embodiment, an apparatus for performing a high voltage (HV) short circuit diagnosis and an impedance analysis for a vehicle is provided. The apparatus includes a controller configured to measure a first voltage associated with a battery and a first current that varies based on a HV power net during the pre-charge operation and to perform the short circuit diagnosis based on the first voltage and the first current. The controller is further configured to determine a difference between the first voltage and a pre-charge voltage across one of a capacitor and the HV power net and to measure a second current based at least on the difference. The controller is further configured to perform the impedance analysis for the vehicle based on the second current.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: May 22, 2018
    Assignee: Lear Corporation
    Inventors: Josep Jacas Miret, Marc Deumal Herraiz, Jordi Borras Gargallo
  • Patent number: 9973606
    Abstract: A method in a wireless communication device includes detecting, with one or more control circuits actuation of the user interface actuator. The one or more control circuit can then determine whether the wireless communication device is disposed at a first predefined location, such as a first receiver of a wireless communication device accessory or a second predefined location. Where the wireless communication device is disposed at the first predefined location, the one or more control circuits can cause a wireless communication circuit to enter a first mode of operation, which can be a searching pairing mode of operation. Where the wireless communication device is disposed at the second predefined location, the one or more control circuits can cause the wireless communication circuit to enter a second mode of operation, which can be a listening pairing mode of operation.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: May 15, 2018
    Assignee: Motorola Mobility LLC
    Inventors: Taneka L Frazier Fields, Donald L Cantrell, Marc B Riley
  • Patent number: 9953122
    Abstract: An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution information of the layout; and generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information; wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets; wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated. Associated non-transitory computer-readable medium is also disclosed.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Jen Chang, Kuo-Nan Yang, Jui-Jung Hsu, Chih-Hung Wu, Chung-Hsing Wang
  • Patent number: 9945902
    Abstract: A burn-in test process is omitted for some or all lots. In burn-in necessity determination processing, whether each semiconductor chip requires a burn-in test to be performed is determined based on measurement data obtained in a probe test process. In an assembly process, based on the results of determination made in the burn-in necessity determination processing, the assembled packages are sorted into a first lot which includes packages each including a semiconductor chip determined to require a burn-in test to be performed and a second lot which includes packages each including a semiconductor chip determined to require no burn-in test to be performed. In a burn-in test process, only the packages of the first lot are subjected to a burn-in test.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Nakamura, Tomoaki Tamura, Kouichi Kumaki
  • Patent number: 9939488
    Abstract: Automated test procedures, carried out under software control, can be employed to test a device, testing individual pins, and/or groups of pins, to detect and diagnose or characterize various types of failures. A distributed FA system includes a shared database for device definitions, test setups, and test results. Test platforms provide I/O curve tracing which can provide both a qualitative visual representation and a quantitative measured performance. The disclosed system enables and exploits front line testing of devices in the field. Response to the customer can be nearly immediate. Eliminate “false returns” by differentiation of use versus a real quality issue.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: April 10, 2018
    Assignee: TESEDA CORPORATION
    Inventors: Joseph M. Salazar, Rich Ackerman, John Raykowski, Armagan Akar, Ralph Sanchez
  • Patent number: 9933475
    Abstract: Provided is a semiconductor inspection circuit which is capable of inspecting connection states of power supply, ground, and signal bumps in a semiconductor package or a printed circuit board equipped with a semiconductor LSI mounted in a product operation state. As a means to solve the problem, a circuit capable of switching a path is provided at an input portion of a driver/receiver, a mechanism capable of transferring an output of a path switching circuit near a receiver circuit to a voltage waveform circuit with an internal variable terminal is provided, and a breakage state of a bump can be observed in the product operation state by observing a DC level at a terminal having a certain DC resistance when a signal bump connection state is observed and receiving a step wave and observing a response waveform thereof when an IO power supply bump connection state is observed.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 3, 2018
    Assignee: HITACHI, LTD.
    Inventors: Yutaka Uematsu, Hideki Osaka, Tadanobu Toba, Kenichi Shimbo
  • Patent number: 9934741
    Abstract: An active device array substrate is provided. The active device array substrate includes multiple pixel structures, a drive circuit, multiple signal lines and a control line. The pixel structures are disposed in a display area. The drive circuit is disposed outside the display area. The signal lines are electrically connected to the drive circuit and the pixel structures corresponded to the signal lines. The control lines are intersected with the signal lines. A method adapted for inspecting defects on the active device array substrate is also provided. First, a tested signal line is selected from the signal lines, and the control line and the tested-signal line are conducted. Second, a test signal is input from the control line to the tested-signal line to determine a location of a defect. Finally, the control line and the tested signal line are isolated.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: April 3, 2018
    Assignee: Au Optronics Corporation
    Inventor: Ying-Hao Pan
  • Patent number: 9893873
    Abstract: A method of determining a communication time delay in a communication network between a local terminal and one or more remote terminals within an electrical power network includes: selecting, in respect of the or each remote terminal a calculation node in the electrical power network; calculating respective node currents flowing into the corresponding calculation node from the local terminal and the or each remote terminal; equating, in respect of the or each remote terminal, a sum of node currents flowing into the corresponding calculation node to zero according to Kirchhoff's first law; and extracting, in respect of the or each remote terminal, a communication time delay between the local terminal and the said respective remote terminal from a corresponding equated sum of node currents.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 13, 2018
    Assignee: General Electric Technology GmbH
    Inventors: Hengxu Ha, Sankara Subramanian Sri Gopala Krishna Murthi