Built-in Test Circuit Patents (Class 324/750.3)
  • Patent number: 11951959
    Abstract: An apparatus for providing a sensor signal (SS) for evaluating a vehicle braking system, including: a first signal-path (SP) for outputting the SS to a first output-interface (OI) to a first converter-device (CD), the first SP having first electronic-components (EC), and is electrically connectable to an input-interface (II) to a vehicle sensor (VS); a first test-device (TD) for applying a first test-signal (TS) to the SS in the first SP, the first TD being electrically connectable to the first SP; a second SP for outputting the SS to a second OI to a second CD, the second SP having second EC, and is electrically connectable to the II to the VS; and a second TD for applying a second TS to the SS in the second SP, the second TD being electrically connectable to the second SP. Also described are a method, control unit, braking system, and computer readable medium.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 9, 2024
    Assignee: KNORR-BREMSE SYSTEME FUER NUTZFAHRZEUGE GMBH
    Inventors: Frank Scholl, Dieter Winz
  • Patent number: 11892499
    Abstract: Embodiments of the present application provide a testing equipment and a testing method. The testing equipment includes: a plurality of pad groups and a plurality of source measure units. Each of the pad groups has a stress pad. The stress pad is configured to connect an element under test. The source measure unit is configured to send an input signal to the element under test through the stress pad and measure an output signal of the element under test to acquire performance parameters of the element under test. The stress pads of at least two of the pad groups are connected to the corresponding source measure units at the same time. The embodiments of the present application help improve the testing efficiency.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kang Lv, Yang Xiong, Jian Hu
  • Patent number: 11892520
    Abstract: A method and device for power supply mapping detection, and medium include the following operations. A voltage value of a power supply signal is obtained according to the power supply signal currently received by a function module; it is detected whether the voltage value of the power supply signal matches a standard voltage value corresponding to the function module; and responsive to the voltage value of the power supply signal not matching the standard voltage value corresponding to the function module, it is determined that a connection error occurs in a power supply connection of the function module.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yu Li, Changqing Wu
  • Patent number: 11854914
    Abstract: A memory device includes a first memory block. The first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. The first memory block further includes a plurality of first interconnect structures electrically coupled to the first memory sub-array through the first interface portion, and a second plurality of interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a transistor. The memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. The first and second test structures are electrically coupled to each other and are each electrically isolated form the first memory block.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Chia-En Huang
  • Patent number: 11848259
    Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan
  • Patent number: 11774480
    Abstract: Systems, devices, and associated methods are provided for testing and tuning radiofrequency (RF) modules. An example system includes a test station including an imaging device, a measurement device, and a robotic arm. The system may include a rotary stage coupled with the robotic arm, measurement probes disposed in the rotary stage and operably coupled with the measurement device, and tuning tips disposed in the rotary stage. The system may include a galvo scanner and laser to remove conductive material. In operation, the test station may perform a testing procedure on an RF module where the measurement probes generate testing data indicative of testing parameters. The test station may perform a tuning procedure on the RF module where a tuning tip or the laser modifies the RF module based on the testing parameters. The testing and tuning may be performed by a user, semi-autonomously, or autonomously.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: October 3, 2023
    Assignee: CAES SYSTEMS LLC
    Inventors: James Scott Sacks, Baker M. Sharif, Thomas Matthew Graves, Nicholas Aaron Vong
  • Patent number: 11774493
    Abstract: A semiconductor integrated circuit inputs and outputs signals regarding a test using two terminals, having a bidirectional terminal for input and output of data and an input terminal for input of a clock signal. A signal is output via the bidirectional terminal in accordance with an output control signal output from an output control circuit. The output control circuit performs control in synchronization with the clock signal to prevent data input to the bidirectional terminal and an output permission signal based on the output control signal from overlapping each other.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: October 3, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichi Iwao, Eiki Aoyama
  • Patent number: 11761999
    Abstract: Systems, devices, and associated methods are provided for testing and tuning radiofrequency (RF) modules. An example system includes a test station including an imaging device, a measurement device, and a robotic arm. The system may include a rotary stage coupled with the robotic arm, measurement probes disposed in the rotary stage and operably coupled with the measurement device, and tuning tips disposed in the rotary stage. The system may include a galvo scanner and laser to remove conductive material. In operation, the test station may perform a testing procedure on an RF module where the measurement probes generate testing data indicative of testing parameters. The test station may perform a tuning procedure on the RF module where a tuning tip or the laser modifies the RF module based on the testing parameters. The testing and tuning may be performed by a user, semi-autonomously, or autonomously.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: September 19, 2023
    Assignee: CAES SYSTEMS LLC
    Inventors: James Scott Sacks, Baker M. Sharif, Thomas Matthew Graves, Nicholas Aaron Vong
  • Patent number: 11728227
    Abstract: Test structures on a wafer are provided. A plurality of cells are arranged in rows and columns of a test array. First and second output pads are formed on opposite sides of the test array. A first output pad is coupled to the cells in one half of the rows of the test array. A second output pad is coupled to the cells in the other half of the rows of the test array. Each first input pad is coupled to the cells in respective column of the test array. Each second input pad is coupled to the cells in respective row of the test array. When a first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads, current flowing through the turned-on cell is measured through the first or second output pad.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Yi Lin, Chih-Chuan Yang, Kuo-Hsiu Hsu, Lien-Jung Hung
  • Patent number: 11719734
    Abstract: Systems, devices, and associated methods are provided for testing and tuning radiofrequency (RF) modules. An example system includes a test station including an imaging device, a measurement device, and a robotic arm. The system may include a rotary stage coupled with the robotic arm, measurement probes disposed in the rotary stage and operably coupled with the measurement device, and tuning tips disposed in the rotary stage. The system may include a galvo scanner and laser to remove conductive material. In operation, the test station may perform a testing procedure on an RF module where the measurement probes generate testing data indicative of testing parameters. The test station may perform a tuning procedure on the RF module where a tuning tip or the laser modifies the RF module based on the testing parameters. The testing and tuning may be performed by a user, semi-autonomously, or autonomously.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: August 8, 2023
    Assignee: CAES SYSTEMS LLC
    Inventors: James Scott Sacks, Baker M. Sharif, Thomas Matthew Graves, Nicholas Aaron Vong
  • Patent number: 11646097
    Abstract: A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: May 9, 2023
    Assignee: SK hynix Inc.
    Inventors: Young Jun Park, Young Jun Ku, In Keun Kim, Sang Sic Yoon
  • Patent number: 11636786
    Abstract: A display device includes a display panel including a display area and a non-display area adjacent to the display area, and a driving circuit disposed on the non-display area. The driving circuit includes a plurality of bumps disposed in a plurality of rows, and a first alignment mark bump disposed at an end of at least one of the plurality of rows.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: April 25, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hongam Kim, Youngmin Cho
  • Patent number: 11626048
    Abstract: An electronic panel includes a base substrate having a first area, a second area adjacent to the first area, and a third area adjacent to the second area, a plurality of pixels in the second area, a plurality of pixel signal lines in the third area and connected to the pixels, a crack detecting pattern spaced apart from the pixels and in the first area, a first line spaced apart from the pixel signal lines, in the third area, and connected to a portion of the crack detecting pattern, and a second line spaced apart from the pixel signal lines, in the third area, connected to another portion of the crack detecting pattern, and spaced apart from the first line. The crack detecting pattern has a line-symmetrical shape with respect to a symmetry axis passing through a center of the first area.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 11, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jeongyun Han, Jong-Hwa Kim, Kyungsu Lee
  • Patent number: 11579188
    Abstract: Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: February 14, 2023
    Assignee: SK hynix Inc.
    Inventor: Tae-Pyeong Kim
  • Patent number: 11573263
    Abstract: The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M?1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the asymmetric ring oscillators are different.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: February 7, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Shengcheng Deng, Chia-Chi Hsu, Anping Qiu
  • Patent number: 11568950
    Abstract: A semiconductor device includes a plurality of first micro-bumps suitable for transferring normal signals; a plurality of a second micro-bumps suitable for transferring test signals; and a test circuit including a plurality of scan cells respectively corresponding to the first and second micro-bumps. The test circuit is suitable for applying signals stored in the respective scan cells to the first and second micro-bumps, feeding back the applied signals from the first and second micro-bumps to the respective scan cells, and sequentially outputting the signals stored in the scan cells to a test output pad.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: January 31, 2023
    Assignee: SK hynix Inc.
    Inventors: Youngjun Park, Youngjun Ku, Junil Moon, Byungkuk Yoon, Seokwoo Choi
  • Patent number: 11561115
    Abstract: Sensor devices and corresponding methods are provided. When a signal path output (COMP OUT) indicates no threshold crossings, diagnosis is performed with a timing based on a clock. In case threshold crossings are indicated, diagnosis is performed with a timing based on threshold crossings.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: January 24, 2023
    Assignee: Infineon Technologies AG
    Inventors: Dragos Vocurek, Hans-Joerg Wagner
  • Patent number: 11521527
    Abstract: A display device according to various embodiments comprises: a pixel layer comprising a plurality of pixels and having one or more parts of an area of an outer line, on which the plurality of pixels are disposed, depressively formed; and a wiring layer disposed along the depressively-formed one or more parts of the outer line, and comprising detection wiring for detecting cracks on an area adjacent to the pixel layer, wherein the wiring layer can be disposed below the pixel layer. Other various embodiments are possible.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: December 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungchul An, Sangseol Lee, Seungheon Lee, Kwangtai Kim, Hyungsup Byeon, Jiwoong Oh
  • Patent number: 11508274
    Abstract: The present disclosure relates to a technique for determining a fault of a data line disposed in a display panel using a data driving device. The data driving device may determine a fault of a data line by supplying a data voltage corresponding to a greyscale value to a data line and checking whether another data line is influenced by the data voltage.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: November 22, 2022
    Assignee: Silicon Works Co., Ltd.
    Inventor: Jung Min Choi
  • Patent number: 11495498
    Abstract: A semiconductor device may include: first to n-th through-electrodes; first to n-th through-electrode driving circuits suitable for charging the first to n-th through-electrodes to a first voltage level, or discharging the first to n-th through-electrodes to a second voltage level; and first to n-th error detection circuits, each suitable for storing the first voltage level or the second voltage level of a corresponding through-electrode of the first to n-th through-electrodes as a down-detection signal and an up-detection signal, and outputting a corresponding error detection signal of first to n-th error detection signals by sequentially masking the down-detection signal and the up-detection signal.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Jihwan Kim, Sangmuk Oh, Donguk Lee
  • Patent number: 11486937
    Abstract: The invention relates to an electric circuit arrangement (20) for the functional testing of a monitoring device (4) for a power supply system (2), the electric circuit arrangement (20) having a test resistance (Rf1, Rf2) which is switched between an active conductor (L1, L2) of the power supply system (2) and ground (PE) and has a settable actual resistance value (Rx). In this context, a bidirectional cascade (12) consisting of field-effect transistors as test resistances (Rf1, Rf2) and an analog control (10) for the continuous-value setting of the actual resistance value (Rx) to a predefined target resistance value (R0) are provided.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 1, 2022
    Assignee: BENDER GMBH & CO. KG
    Inventors: Julian Reitz, Karl Schepp
  • Patent number: 11489750
    Abstract: An automatic test device is disclosed. The automatic test device is includes connection ports, a processor, and a transmission integrated interface. The connection ports is configured to couple to a device under test. The processor is coupled to the connection ports and is configured to transmit a test instruction through the connection ports to the device under test. The device under test is in a test mode after receiving the test instruction, and the first processor is configured to receive a test signal transmitted through the connection ports from the device under test when the device under test is in the test mode. The transmission integrated interface is coupled between the connection ports and the processor, and is configured to transmit at least one of the test instructions to the connection ports or the processor. An automatic test system is also disclosed herein.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 1, 2022
    Assignee: AmTRAN Technology Co., Ltd.
    Inventors: Chin-Kun Huang, Yu-Ruei Li, Peng-Ta Chiu
  • Patent number: 11456283
    Abstract: A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die and coupled to each other through a plurality of through-electrodes and a reference through-electrode, wherein the base die includes a first test circuit suitable for transferring a test oscillating signal to at least one target through-electrode among the through-electrodes, and outputting a test output signal by comparing a test base signal generated based on the test oscillating signal, with a test core signal transferred through the reference through-electrode, during a test operation; and wherein each of the core dies includes a second test circuit suitable for generating the test core signal corresponding to the test oscillating signal transferred through the target through-electrode, and transferring the test core signal to the reference through-electrode, during the test operation.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: September 27, 2022
    Assignee: SK hynix Inc.
    Inventors: Sangmuk Oh, Kangseol Lee
  • Patent number: 11454656
    Abstract: A signal generating device for generation of measurement signals for an electrical system includes a housing which features an electrically conducting material, an energy reservoir arranged in the housing, a data interface arranged at the housing and designed to receive signal data, a coupling interface arranged at the housing and coupled to the electrical system, and a signal generator arranged in the housing. The signal generator is coupled to the electrical energy reservoir, to the data interface and to the coupling interface. The signal generator is designed, based on the signal data, to generate the measurement signals and to output them via the coupling interface. A corresponding measuring device is also included.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: September 27, 2022
    Assignee: LISA DRAEXLMAIER GMBH
    Inventors: Christian Zacherl, Andreas Kempf, Vencislav Todorov, Thomas Mayer
  • Patent number: 11448690
    Abstract: A testing method and apparatus is disclosed for testing an integrated circuit device (100) which has a dedicated ground bias pad (121) connected across a high voltage electrostatic discharge clamp circuit (123) to a well-driving ground pad (122) by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (103), where the first and second voltage create a stressing voltage across a buried insulator layer (102, 105) in the integrated circuit device so that a screening test can be conducted to screen for a defect (106) in the buried insulator layer by measuring a leakage current.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: September 20, 2022
    Assignee: NXP USA, INC.
    Inventors: Laurent Segarra, Maarten Jacobus Swanenberg, Pierre Turpin, Matthew Bacchi, Russell Schaller, Keith Jackoski, Ronghua Zhu
  • Patent number: 11436162
    Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 6, 2022
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l., STMicroelectronics International N.V.
    Inventors: Riccardo Gemelli, Denis Dutey, Om Ranjan
  • Patent number: 11415625
    Abstract: A method and device for monitoring a multi-die power module in a half-bridge switch configuration are provided. The method and device are designed to set dies in a non conductive state, select one die which is blocking a voltage, inject a current in a gate of the selected die in order to charge an input parasitic capacitance of the selected die, monitor a voltage that is representative of a voltage on the gate of the selected die, and memorize the value of the monitored voltage when the value of the monitored voltage is stabilized.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 16, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Jeffrey Ewanchuk
  • Patent number: 11408932
    Abstract: Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: August 9, 2022
    Assignee: PROTEANTECS LTD.
    Inventors: Eyal Fayneh, Inbar Weintrob, Evelyn Landman, Yahel David, Shai Cohen, Guy Redler
  • Patent number: 11403452
    Abstract: Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may be configured to support different phases of a yield learning ramp up process. The YLV may further include a yield learning controller configured to control circuit block testing, and bypasses configured to partially or fully replicate the behavior of improperly functioning or untested circuit blocks. Some embodiments may include techniques for software implementation of the YLV, such as by invoking a computer to receive data representative of a design of the YLV, and based on the data representative of the design of the integrated circuit, causing the computer to generate data representative of YLV.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 2, 2022
    Assignee: Synopsys, Inc.
    Inventor: Kee Sup Kim
  • Patent number: 11398361
    Abstract: A control system may include a processor that may receive a first dataset associated with a type of load device coupled to a relay device. The processor may then receive a second dataset associated with one or more operations of the load device over a period of time. The processor may also determine a switching profile to control moving an armature of the relay device between a first position and a second position based on the first dataset and the second dataset, such that the switching profile comprises a firing angle for moving the armature with respect to an electrical waveform. The processor may then control a current provided to a relay coil of the relay device based on the switching profile.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 26, 2022
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Ahmad K. Omari, Michael C. McOlash, Stefan T. Dziekonski, Andrew J. Jaap, Randall S. Langer, David Elmiger
  • Patent number: 11375877
    Abstract: A video bus (8) that the plug-in cards (7), which are inserted into the individual slots (13), acquire and/or evaluate information, which refers to and/or describes the assigned slot (13) and/or cores (12) already assigned by other plug-in cards (25) or cores (16) which are still free.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 5, 2022
    Assignee: Schölly Fiberoptic GmbH
    Inventors: Alexander Kohler, Daniel Harter
  • Patent number: 11378617
    Abstract: An apparatus comprising: a functional circuit comprising one or more circuit components configured to perform a function based on one or more first input signals; at least one failure-prediction circuit for use in predicting failure of the functional circuit, the failure-prediction circuit comprising a replica of the functional circuit in terms of constituent circuit components; wherein the failure-prediction circuit is configured to be more susceptible to failure than said functional circuit, wherein the apparatus is configured to provide a prediction of failure of the functional circuit based on a determination of failure of the failure-prediction circuit.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 5, 2022
    Assignee: NXP B.V.
    Inventors: Michael Doescher, Jan-Peter Schat
  • Patent number: 11378620
    Abstract: A method for detecting an abnormal die includes providing a wafer, determining the surrounding dies in accordance with a position of a target die on the wafer, calculating a difference between a value of an electrical characteristic of each of the surrounding dies and a value of an electrical characteristic of the target die to obtain the electrical characteristic deviations, ranking the absolute values of the electrical characteristic deviations to generate a ranking result, and determining the characteristic-related dies from the surrounding dies in accordance with the ranking result, determining a target-related area in accordance with the position of the target die, determining the target-related die from the characteristic-related dies in accordance with the target-related area and determining whether the target die is qualified in accordance with the target-related die.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 5, 2022
    Assignee: INTEGRATED SILICON SOLUTION INC.
    Inventors: Shou-Kang Fan, Lien-Sheng Yang
  • Patent number: 11335856
    Abstract: A display device includes a display area, a test pad, a plurality of first test transistors, and at least one outline. The display area includes pixels coupled to data lines and scan lines. The test pad receives a test signal. The first test transistors are coupled between the data lines of the display area and the test pad. The at least one outline is coupled between one of the first test transistors and the test pad. The at least one outline is located in a non-display area outside the display area.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 17, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Won-Kyu Kwak, Hwan-Soo Jang, Jae-Yong Lee
  • Patent number: 11328789
    Abstract: A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 10, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Gary D. Hamor, Michael R. Spica, Donald Shepard, Patrick Caraher, João Elmiro da Rocha Chaves
  • Patent number: 11302591
    Abstract: The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11287469
    Abstract: Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: March 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Tae-Pyeong Kim
  • Patent number: 11287455
    Abstract: A sensor interface circuit comprises an input arranged to receive a sensor signal being an electrical signal representative of an electrical quantity. The electrical quantity includes a physical quantity converted in a sensor. The sensor interface circuit includes conversion means arranged for converting the sensor signal into a digital signal, memory to store sensor characterisation data, signal processing means adapted to obtain a first sensor result by processing the digital signal using the sensor characterisation data, and an output unit arranged to receive and output the first sensor result, the digital signal and the sensor characterisation data.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 29, 2022
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Johan Vergauwen, Peter Vandersteegen, Asparuh Ivanov Grigorov
  • Patent number: 11282420
    Abstract: An electronic panel includes a base substrate having a first area, a second area adjacent to the first area, and a third area adjacent to the second area, a plurality of pixels in the second area, a plurality of pixel signal lines in the third area and connected to the pixels, a crack detecting pattern spaced apart from the pixels and in the first area, a first line spaced apart from the pixel signal lines, in the third area, and connected to a portion of the crack detecting pattern, and a second line spaced apart from the pixel signal lines, in the third area, connected to another portion of the crack detecting pattern, and spaced apart from the first line. The crack detecting pattern has a line-symmetrical shape with respect to a symmetry axis passing through a center of the first area.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 22, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jeongyun Han, Jong-Hwa Kim, Kyungsu Lee
  • Patent number: 11275111
    Abstract: Disclosed is a plurality of through-silicon vias (TSVs) and related systems, methods, and devices. An electronic device includes a stack of chips, a first TSV, and a second TSV. The stack of chips includes one or more side edges at a perimeter of the stack of chips. A TSV zone of the stack of chips is within a predetermined distance from the one or more side edges. The first TSV is within the TSV zone of the stack of chips at a first distance from the one or more side edges. The second TSV is within the TSV zone of the stack of chips at a second distance from the one or more side edges. The second distance is shorter than the first distance.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Naohisa Nishioka
  • Patent number: 11268980
    Abstract: An inference engine determines whether a device under test has become stuck in a test socket of an automated test system by analyzing measurement data sampled during normal execution of a production test program for the device. The inference engine is trained to identify stuck patterns in the measurement data for a particular device design. In the event a stuck condition is detected by the inference engine, testing by the automated test system is halted and an alert is transmitted to an operator.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: March 8, 2022
    Assignee: Invantest, Inc.
    Inventors: Wen Jau Lee, Jason Saw
  • Patent number: 11272616
    Abstract: An example apparatus includes a first printed circuit board (PCB) having a power layer, a ground layer, and a slot. The slot includes a first power electrical contact that is electrically connected to the power layer and a first ground electrical contact that is connected to the ground layer. The slot extends orthogonally or obliquely through multiple layers of the first PCB. A second PCB includes a second power electrical contact, a second ground electrical contact, and capacitors electrically connected between the second power electrical contact and the second ground electrical contact. The second PCB is configured for insertion into the slot to form an electrical connection between the first power electrical contact and the second power electrical contact and between the first ground electrical contact and the second ground electrical contact.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 8, 2022
    Assignee: TERADYNE, INC.
    Inventors: Brian Brecht, Roger A. Plante, Richard Pye, Julie Robison, Alfred M. Zakarian, William Patti, Mark Garcia, Shih-Fan Chen, Kenneth L. Degan, Heng-Kit Too
  • Patent number: 11251139
    Abstract: A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 15, 2022
    Assignee: X-Celeprint Limited
    Inventors: Ronald S. Cok, Joseph Carr
  • Patent number: 11240878
    Abstract: A test system includes: a signal processor configured to generate a plurality of orthogonal baseband sequences; a signal generator configured to supply the plurality of orthogonal baseband sequences to a corresponding plurality of RF transmitters of a device under test (DUT), wherein the RF transmitters each employ the corresponding orthogonal baseband sequence to generate a corresponding RF signal on a corresponding channel among a plurality of channels of the DUT such that the RF transmitters output a plurality of orthogonal RF signals at a same time; a combiner network configured to combine the plurality of orthogonal RF signals and to output a single signal under test; and a single channel measurement instrument configured to receive the single signal under test and to measure independently therefrom at least one characteristic of each of the RF transmitters. Orthogonal RF test signals may be used similarly to test RF receivers of the DUT.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 1, 2022
    Assignee: Keysight Technologies, Inc.
    Inventors: Stephen G. Duffy, Xu Zhao, Hong-Wei Kong, Ya Jing
  • Patent number: 11240453
    Abstract: A photoelectric conversion device includes a plurality of pixels arranged in an array to form a plurality of rows and a plurality of columns. Each of the plurality of pixels includes a photon detection element that outputs an output signal generated by avalanche multiplication in accordance with incidence of a photon, a quench element connected to the photon detection element, a waveform shaper that is connected to the photon detection element and generates a detection signal based on the output signal, and a signal processing circuit that performs signal processing on the detection signal output from the waveform shaper. The signal processing circuit includes a counting unit that performs a counting process of counting the detection signal output from the waveform shaper, and a calculation unit that performs a predetermined calculation process on a count result output from the counting unit.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: February 1, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yu Maehashi
  • Patent number: 11221379
    Abstract: Systems and methods for detecting the presence and/or location of defects (e.g., incomplete solders, broken cables, misconnections, defective sockets, opens, shorts, etc.) along electrical lines are described. The systems and methods described herein may use time-domain reflectometry (TDR), a measurement technique used to determine the characteristics of electrical lines by observing reflected waveforms. TDR may be performed in some embodiments by determining the times when a first event and a second event occur, and by determining the space traveled by a probe signal based on these times. The first event may occur when a first signal transition crosses a first threshold and the second event may occur when a second signal transition crosses a second threshold, where the second signal transition may arise in response to the first signal transition reflecting against a defect along the electrical line.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: January 11, 2022
    Assignee: MEDIATEK Singapore Pte. Ltd.
    Inventors: Huan-Sheng Chen, Henry Arnold Park, Tamer Mohammed Ali
  • Patent number: 11183089
    Abstract: A display device includes a display panel having a plurality of pixels and a driving circuit. A plurality of driving lines electrically connects the driving circuit to the display panel and supplies driving signals from the driving circuit to the display panel. A switching unit connects each of the plurality of driving lines to a first end of an inspection line. An inspection circuit is connected to a second end of the inspection line. A line selection unit is configured to selectively connect one or more of the plurality of driving lines to the inspection circuit through the inspection line.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Do Hyung Ryu
  • Patent number: 11181589
    Abstract: A semiconductor device includes: a signal input circuit that receives a signal from an outside; a signal output circuit that outputs the signal to the outside; a coupling element connected between the signal input circuit and the signal output circuit; an inspection output circuit that causes the signal input circuit to output an inspection signal to the outside not via the coupling element or an inspection input circuit that causes the signal output circuit to receive the inspection signal from the outside not via the coupling element. The signal input circuit, the signal output circuit, and the coupling element are formed on a semiconductor chip and packaged.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: November 23, 2021
    Assignee: DENSO CORPORATION
    Inventors: Junichi Hasegawa, Yusuke Michishita
  • Patent number: 11177015
    Abstract: A system-on-chip (SoC) includes a processor, a built-in self-testing (BIST) circuitry, and an adaptive masking circuitry. The processor generates a sweep enable (SWEN) signal to initiate a self-testing operation of the SoC. The BIST circuitry receives the SWEN signal and generates a set of sweep events, such that a transition of the processor from a low power (LP) mode to an active mode is initiated based on the generation of each sweep event. The BIST circuitry further receives a status signal, and identifies a subset of sweep events at which the transition of the processor from the LP mode to the active mode failed, for generating sweep failure data. The adaptive masking circuitry receives the sweep failure data and generates a mask signal, to prevent a transition of the first processor from the LP mode to the active mode, during a non-testing operation of the SoC.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP USA, INC.
    Inventors: Nidhi Sinha, Garima Sharda, Dinesh Joshi, Akshay Pathak
  • Patent number: 11153007
    Abstract: An optical device has an optical transmitter circuit formed in a substrate, a first port configured to output an optical signal generated by the optical transmitter circuit from an edge of the substrate during services and to input a test light from the edge of the substrate during a test, and a photodetector configured to detect the test light input from the first port.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: October 19, 2021
    Assignee: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventor: Masaki Sugiyama