Abstract: An impedance adjusting circuit is provided. The impedance adjusting circuit of the disclosure includes a sensing node, a pull-up impedance generator, a zero quotient (ZQ) calibrating circuit and a controller. The pull-up impedance generator is coupled between an external voltage and the sensing node. The controller enables a detecting mode in response to a detecting command, and detect a sensing voltage on the sensing node in the detecting mode. When the sensing voltage is in a default voltage range, the controller controls the ZQ calibrating circuit to perform a ZQ calibrating operation on the pull-up impedance generator. When the sensing voltage is out of the default voltage range in the detecting mode, the controller provides a trimming command to the ZQ calibrating circuit. The ZQ calibrating circuit provides a build-in trim code to the pull-up impedance generator in response to the trimming command.

Abstract: A radio frequency switch generator applicable to 1.8 V and 1.2 V power supplies, which relates to the technical field of radio frequency switches. The present invention comprises a bandgap reference circuit, a linear voltage regulator circuit, a boost circuit, a ring oscillator circuit and a negative voltage circuit; wherein both the boost circuit and the ring oscillator circuit adopt an independent linear voltage stabilizing circuit as a power supply voltage source; square signals generated by the ring oscillator circuit are regarded as input signals of the boost circuit and the negative voltage circuit; and positive voltage is finally obtained after the boost circuit is subjected to double boosting twice, and negative voltage is finally obtained after the negative voltage circuit is subjected to three-level cascading.

Abstract: Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.

Abstract: A system for testing is provided. The system includes an electronic circuit and an automatic testing equipment (ATE). The electronic circuit includes a voltage monitor including a resistive divider receiving at its voltage input an input voltage and coupled at its output to an input of a comparator. A reference input of the comparator is coupled to a generator supplying a reference voltage setting one or more thresholds of the comparator. The electronic circuit includes a Built In Self Test Module coupled to the ATE and to the inputs and output of the comparator. The BIST module is being configured upon receiving respective commands from the ATE to test a reaction time of the comparator and an offset of the comparator. The ATE performs a respective test of the ratio of the resistor divider by a first voltage measurement and a test of the reference voltage provided by the generator.

Abstract: A method and apparatus is proposed for accurately evaluating the performance of optical transmitters under test conditions (such as high bit-rate modulation formats) that compromise the operability of standard test equipment used for this purpose. The proposed apparatus and method are similar to the elements associated with existing testing standards based on an optical eye diagram, with an important distinction that allows for accurate measurements of the transmitter's performance to be made. In particular, the sampling point for collecting eye diagram data samples in the inventive arrangement is shifted by half a period with respect to the conventional mid-eye sampling point, eliminating the need to include representative reference equalizer in the test equipment and providing an evaluation not influenced by the test equipment, resulting in a more accurate measurement of transmitter-related distortions.

Abstract: A signal driver may include a plurality of distributed drivers along a differential transmission line. Each of the plurality of the distributed drivers may include: an output tap configured to receive a portion of an incoming signal of the signal driver; and a T-coil connected to an output node of the output tap. The differential transmission line is connected to and intercepted by a first terminal and a second terminal of the T-coil, and a plurality of T-coils of the plurality of the distributed drivers are distributed along and spaced apart on the differential transmission line.

Abstract: A memory device includes a plurality of memory sub-arrays. Each of the memory sub-arrays is accessed through a staircase of word lines (WLs) and a plurality of interconnect structures. The memory device includes a plurality of test structures. Each of the test structures corresponds to one of the memory sub-arrays, and includes: (i) a staircase of test WLs that emulate the staircase of WLs coupled to the corresponding memory sub-array, and (ii) a plurality of test interconnect structures that emulate the interconnect structures coupled to the corresponding memory sub-array. The plurality of test structures are electrically coupled to one another in series.

Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

Abstract: Systems, devices, and associated methods are provided for testing and tuning devices under test (e.g., radiofrequency modules). An example system includes a test station including an imaging device, a measurement device, and a robotic arm. The system may include a rotary stage coupled with the robotic arm, measurement probes disposed in the rotary stage and operably coupled with the measurement device, and tuning tips disposed in the rotary stage. The system may include a galvo scanner and laser to remove conductive material. The test station may perform a testing procedure on an RF module where the measurement probes generate testing data indicative of testing parameters. The test station may perform a tuning procedure on the RF module where a tuning tip or the laser modifies the RF module based on the testing parameters. The testing and tuning may be performed by a user, semi-autonomously, or autonomously.

Abstract: A semiconductor integrated circuit includes: one input terminal; multiple output terminals; multiple first current control elements connected between the input terminal and the respective output terminals; a control circuit that controls the first current control elements; a fault detection circuit that includes multiple voltage comparator circuits each of which compares a voltage proportional to a voltage of one of the output terminals with a predetermined threshold voltage and that detects an open-circuit state or a short-circuit state of the output terminals; an external terminal connected to an external resistor; a voltage convertor circuit that generates the threshold voltage according to a voltage of the external terminal that is generated by flowing a current through the external resistor, the threshold voltage being applied to an input terminal of each of the voltage comparator circuits; and a detection result output terminal for outputting a detection result by the fault detection circuit.

Abstract: A semiconductor device in which a plurality of substrates including a first substrate and a second substrate are stacked, wherein the first substrate includes a pixel unit in which a plurality of pixels are arranged, the second substrate includes a control circuit configured to control the semiconductor device, and the first substrate further includes a detection circuit configured to detect a connection state of a connection portion between the first substrate and the second substrate.

Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.

Abstract: A probe position monitoring structure includes a first common line and a contact portion configured for being directly contacted with a probe. The contact portion includes a first zigzag structure, and a first end of the first zigzag structure is directly connected with the first common line. A method of monitoring a position of a probe includes the following steps. The probe position monitoring structure is provided. The first zigzag structure is directly contacted with a first probe. A resistance measurement is performed to measure a resistance of a portion of the first zigzag structure located between the first probe and the first end for monitoring a position of the first probe.

Abstract: Provided is a solid state power controller (SSPC). The SSPC comprises a power supply line configured to be connected between a power source and a load. Further, the solid state power controller comprises a semiconductor switching unit provided on the power supply line and configured to switch between at least two states according to a command signal. The at least two states include a conducting state and a non-conducting state. Further the solid state power controller comprises a state machine, which is configured to exhibit at least two states, including an ON state and an OFF state. The state machine is further configured to output the command signal according to a current state of the state machine.

Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a first output pad and a second output pad coupled to different cells, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. A first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads to turn on a cell, and a current flowing through the turned-on cell is measured.

Abstract: An electronic device includes a first substrate having a first bonding region, a first circuit, a second circuit, a third circuit, and a plurality of first conductive contacts. The first and second circuit are located at a first edge and a second edge of the first bonding region, the third circuit is located between the first and the second circuits. A second substrate having a second bonding region corresponding to the first bonding region in position and a fourth circuit, a fifth circuit, a sixth circuit, and a plurality of second conductive contacts. When the first substrate is bonded with the second substrate, the first circuit, the second circuit, the third circuit, the fourth circuit, the fifth circuit, and the sixth circuit form a loop, and the first and second conductive contacts are electrically connected to a plurality of signal circuits.

Abstract: An electronic panel includes a base substrate having a first area, a second area adjacent to the first area, and a third area adjacent to the second area, a plurality of pixels in the second area, a plurality of pixel signal lines in the third area and connected to the pixels, a crack detecting pattern spaced apart from the pixels and in the first area, a first line spaced apart from the pixel signal lines, in the third area, and connected to a portion of the crack detecting pattern, and a second line spaced apart from the pixel signal lines, in the third area, connected to another portion of the crack detecting pattern, and spaced apart from the first line. The crack detecting pattern has a line-symmetrical shape with respect to a symmetry axis passing through a center of the first area.

Abstract: An apparatus for providing a sensor signal (SS) for evaluating a vehicle braking system, including: a first signal-path (SP) for outputting the SS to a first output-interface (OI) to a first converter-device (CD), the first SP having first electronic-components (EC), and is electrically connectable to an input-interface (II) to a vehicle sensor (VS); a first test-device (TD) for applying a first test-signal (TS) to the SS in the first SP, the first TD being electrically connectable to the first SP; a second SP for outputting the SS to a second OI to a second CD, the second SP having second EC, and is electrically connectable to the II to the VS; and a second TD for applying a second TS to the SS in the second SP, the second TD being electrically connectable to the second SP. Also described are a method, control unit, braking system, and computer readable medium.

Abstract: Embodiments of the present application provide a testing equipment and a testing method. The testing equipment includes: a plurality of pad groups and a plurality of source measure units. Each of the pad groups has a stress pad. The stress pad is configured to connect an element under test. The source measure unit is configured to send an input signal to the element under test through the stress pad and measure an output signal of the element under test to acquire performance parameters of the element under test. The stress pads of at least two of the pad groups are connected to the corresponding source measure units at the same time. The embodiments of the present application help improve the testing efficiency.

Abstract: A method and device for power supply mapping detection, and medium include the following operations. A voltage value of a power supply signal is obtained according to the power supply signal currently received by a function module; it is detected whether the voltage value of the power supply signal matches a standard voltage value corresponding to the function module; and responsive to the voltage value of the power supply signal not matching the standard voltage value corresponding to the function module, it is determined that a connection error occurs in a power supply connection of the function module.

Abstract: A memory device includes a first memory block. The first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. The first memory block further includes a plurality of first interconnect structures electrically coupled to the first memory sub-array through the first interface portion, and a second plurality of interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a transistor. The memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. The first and second test structures are electrically coupled to each other and are each electrically isolated form the first memory block.

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

Abstract: A semiconductor integrated circuit inputs and outputs signals regarding a test using two terminals, having a bidirectional terminal for input and output of data and an input terminal for input of a clock signal. A signal is output via the bidirectional terminal in accordance with an output control signal output from an output control circuit. The output control circuit performs control in synchronization with the clock signal to prevent data input to the bidirectional terminal and an output permission signal based on the output control signal from overlapping each other.

Abstract: Systems, devices, and associated methods are provided for testing and tuning radiofrequency (RF) modules. An example system includes a test station including an imaging device, a measurement device, and a robotic arm. The system may include a rotary stage coupled with the robotic arm, measurement probes disposed in the rotary stage and operably coupled with the measurement device, and tuning tips disposed in the rotary stage. The system may include a galvo scanner and laser to remove conductive material. In operation, the test station may perform a testing procedure on an RF module where the measurement probes generate testing data indicative of testing parameters. The test station may perform a tuning procedure on the RF module where a tuning tip or the laser modifies the RF module based on the testing parameters. The testing and tuning may be performed by a user, semi-autonomously, or autonomously.

Abstract: Systems, devices, and associated methods are provided for testing and tuning radiofrequency (RF) modules. An example system includes a test station including an imaging device, a measurement device, and a robotic arm. The system may include a rotary stage coupled with the robotic arm, measurement probes disposed in the rotary stage and operably coupled with the measurement device, and tuning tips disposed in the rotary stage. The system may include a galvo scanner and laser to remove conductive material. In operation, the test station may perform a testing procedure on an RF module where the measurement probes generate testing data indicative of testing parameters. The test station may perform a tuning procedure on the RF module where a tuning tip or the laser modifies the RF module based on the testing parameters. The testing and tuning may be performed by a user, semi-autonomously, or autonomously.

Abstract: Test structures on a wafer are provided. A plurality of cells are arranged in rows and columns of a test array. First and second output pads are formed on opposite sides of the test array. A first output pad is coupled to the cells in one half of the rows of the test array. A second output pad is coupled to the cells in the other half of the rows of the test array. Each first input pad is coupled to the cells in respective column of the test array. Each second input pad is coupled to the cells in respective row of the test array. When a first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads, current flowing through the turned-on cell is measured through the first or second output pad.

Abstract: Systems, devices, and associated methods are provided for testing and tuning radiofrequency (RF) modules. An example system includes a test station including an imaging device, a measurement device, and a robotic arm. The system may include a rotary stage coupled with the robotic arm, measurement probes disposed in the rotary stage and operably coupled with the measurement device, and tuning tips disposed in the rotary stage. The system may include a galvo scanner and laser to remove conductive material. In operation, the test station may perform a testing procedure on an RF module where the measurement probes generate testing data indicative of testing parameters. The test station may perform a tuning procedure on the RF module where a tuning tip or the laser modifies the RF module based on the testing parameters. The testing and tuning may be performed by a user, semi-autonomously, or autonomously.

Abstract: A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.

Abstract: A display device includes a display panel including a display area and a non-display area adjacent to the display area, and a driving circuit disposed on the non-display area. The driving circuit includes a plurality of bumps disposed in a plurality of rows, and a first alignment mark bump disposed at an end of at least one of the plurality of rows.

Abstract: An electronic panel includes a base substrate having a first area, a second area adjacent to the first area, and a third area adjacent to the second area, a plurality of pixels in the second area, a plurality of pixel signal lines in the third area and connected to the pixels, a crack detecting pattern spaced apart from the pixels and in the first area, a first line spaced apart from the pixel signal lines, in the third area, and connected to a portion of the crack detecting pattern, and a second line spaced apart from the pixel signal lines, in the third area, connected to another portion of the crack detecting pattern, and spaced apart from the first line. The crack detecting pattern has a line-symmetrical shape with respect to a symmetry axis passing through a center of the first area.

Abstract: Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.

Abstract: The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M?1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the asymmetric ring oscillators are different.

Abstract: A semiconductor device includes a plurality of first micro-bumps suitable for transferring normal signals; a plurality of a second micro-bumps suitable for transferring test signals; and a test circuit including a plurality of scan cells respectively corresponding to the first and second micro-bumps. The test circuit is suitable for applying signals stored in the respective scan cells to the first and second micro-bumps, feeding back the applied signals from the first and second micro-bumps to the respective scan cells, and sequentially outputting the signals stored in the scan cells to a test output pad.

Abstract: Sensor devices and corresponding methods are provided. When a signal path output (COMP OUT) indicates no threshold crossings, diagnosis is performed with a timing based on a clock. In case threshold crossings are indicated, diagnosis is performed with a timing based on threshold crossings.

Abstract: A display device according to various embodiments comprises: a pixel layer comprising a plurality of pixels and having one or more parts of an area of an outer line, on which the plurality of pixels are disposed, depressively formed; and a wiring layer disposed along the depressively-formed one or more parts of the outer line, and comprising detection wiring for detecting cracks on an area adjacent to the pixel layer, wherein the wiring layer can be disposed below the pixel layer. Other various embodiments are possible.

Abstract: The present disclosure relates to a technique for determining a fault of a data line disposed in a display panel using a data driving device. The data driving device may determine a fault of a data line by supplying a data voltage corresponding to a greyscale value to a data line and checking whether another data line is influenced by the data voltage.

Abstract: A semiconductor device may include: first to n-th through-electrodes; first to n-th through-electrode driving circuits suitable for charging the first to n-th through-electrodes to a first voltage level, or discharging the first to n-th through-electrodes to a second voltage level; and first to n-th error detection circuits, each suitable for storing the first voltage level or the second voltage level of a corresponding through-electrode of the first to n-th through-electrodes as a down-detection signal and an up-detection signal, and outputting a corresponding error detection signal of first to n-th error detection signals by sequentially masking the down-detection signal and the up-detection signal.

Abstract: The invention relates to an electric circuit arrangement (20) for the functional testing of a monitoring device (4) for a power supply system (2), the electric circuit arrangement (20) having a test resistance (Rf1, Rf2) which is switched between an active conductor (L1, L2) of the power supply system (2) and ground (PE) and has a settable actual resistance value (Rx). In this context, a bidirectional cascade (12) consisting of field-effect transistors as test resistances (Rf1, Rf2) and an analog control (10) for the continuous-value setting of the actual resistance value (Rx) to a predefined target resistance value (R0) are provided.

Abstract: An automatic test device is disclosed. The automatic test device is includes connection ports, a processor, and a transmission integrated interface. The connection ports is configured to couple to a device under test. The processor is coupled to the connection ports and is configured to transmit a test instruction through the connection ports to the device under test. The device under test is in a test mode after receiving the test instruction, and the first processor is configured to receive a test signal transmitted through the connection ports from the device under test when the device under test is in the test mode. The transmission integrated interface is coupled between the connection ports and the processor, and is configured to transmit at least one of the test instructions to the connection ports or the processor. An automatic test system is also disclosed herein.

Abstract: A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die and coupled to each other through a plurality of through-electrodes and a reference through-electrode, wherein the base die includes a first test circuit suitable for transferring a test oscillating signal to at least one target through-electrode among the through-electrodes, and outputting a test output signal by comparing a test base signal generated based on the test oscillating signal, with a test core signal transferred through the reference through-electrode, during a test operation; and wherein each of the core dies includes a second test circuit suitable for generating the test core signal corresponding to the test oscillating signal transferred through the target through-electrode, and transferring the test core signal to the reference through-electrode, during the test operation.

Abstract: A signal generating device for generation of measurement signals for an electrical system includes a housing which features an electrically conducting material, an energy reservoir arranged in the housing, a data interface arranged at the housing and designed to receive signal data, a coupling interface arranged at the housing and coupled to the electrical system, and a signal generator arranged in the housing. The signal generator is coupled to the electrical energy reservoir, to the data interface and to the coupling interface. The signal generator is designed, based on the signal data, to generate the measurement signals and to output them via the coupling interface. A corresponding measuring device is also included.

Abstract: A testing method and apparatus is disclosed for testing an integrated circuit device (100) which has a dedicated ground bias pad (121) connected across a high voltage electrostatic discharge clamp circuit (123) to a well-driving ground pad (122) by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (103), where the first and second voltage create a stressing voltage across a buried insulator layer (102, 105) in the integrated circuit device so that a screening test can be conducted to screen for a defect (106) in the buried insulator layer by measuring a leakage current.

Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.

Abstract: A method and device for monitoring a multi-die power module in a half-bridge switch configuration are provided. The method and device are designed to set dies in a non conductive state, select one die which is blocking a voltage, inject a current in a gate of the selected die in order to charge an input parasitic capacitance of the selected die, monitor a voltage that is representative of a voltage on the gate of the selected die, and memorize the value of the monitored voltage when the value of the monitored voltage is stabilized.

Abstract: Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.

Abstract: Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may be configured to support different phases of a yield learning ramp up process. The YLV may further include a yield learning controller configured to control circuit block testing, and bypasses configured to partially or fully replicate the behavior of improperly functioning or untested circuit blocks. Some embodiments may include techniques for software implementation of the YLV, such as by invoking a computer to receive data representative of a design of the YLV, and based on the data representative of the design of the integrated circuit, causing the computer to generate data representative of YLV.

Abstract: A control system may include a processor that may receive a first dataset associated with a type of load device coupled to a relay device. The processor may then receive a second dataset associated with one or more operations of the load device over a period of time. The processor may also determine a switching profile to control moving an armature of the relay device between a first position and a second position based on the first dataset and the second dataset, such that the switching profile comprises a firing angle for moving the armature with respect to an electrical waveform. The processor may then control a current provided to a relay coil of the relay device based on the switching profile.

Abstract: A video bus (8) that the plug-in cards (7), which are inserted into the individual slots (13), acquire and/or evaluate information, which refers to and/or describes the assigned slot (13) and/or cores (12) already assigned by other plug-in cards (25) or cores (16) which are still free.

Abstract: A method for detecting an abnormal die includes providing a wafer, determining the surrounding dies in accordance with a position of a target die on the wafer, calculating a difference between a value of an electrical characteristic of each of the surrounding dies and a value of an electrical characteristic of the target die to obtain the electrical characteristic deviations, ranking the absolute values of the electrical characteristic deviations to generate a ranking result, and determining the characteristic-related dies from the surrounding dies in accordance with the ranking result, determining a target-related area in accordance with the position of the target die, determining the target-related die from the characteristic-related dies in accordance with the target-related area and determining whether the target die is qualified in accordance with the target-related die.

Abstract: An apparatus comprising: a functional circuit comprising one or more circuit components configured to perform a function based on one or more first input signals; at least one failure-prediction circuit for use in predicting failure of the functional circuit, the failure-prediction circuit comprising a replica of the functional circuit in terms of constituent circuit components; wherein the failure-prediction circuit is configured to be more susceptible to failure than said functional circuit, wherein the apparatus is configured to provide a prediction of failure of the functional circuit based on a determination of failure of the failure-prediction circuit.