Abstract: According to a first aspect of the present invention, there is provided a method, a computer system and a computer program product. The method, computer system and computer program product including measuring an initial state of a set of SRAM bits on the wafer, identifying a first set of signature SRAM bits on the wafer, of the set of SRAM bits on the wafer, where the first set of SRAM bits comprise a consistent initial state greater than a first threshold percentage of times, measuring physically dimensions of features of the first set of SRAM bits on the wafer; and identifying a set of signature SRAM bits of the first set of SRAM bits on the wafer, wherein the set of signature SRAM bits comprise physical dimensions of features which correlate to the initial state of each correlated SRAM bit.

Abstract: A method for testing at least one single chip in a wafer probing system, at least comprising: providing an adapter plate having an interface surface for contacting a vacuum chuck of the wafer probing system, the adapter plate being configured to accommodate the at least one single chip in a cutout with a chip rear surface being flush with the interface surface; loading the adapter plate with the at least one single chip into the wafer probing system; determining an exact position of the at least one single chip in the adapter plate in the search area; and testing the at least one single chip with test routines stored in a controller of the wafer probing system. A device and an adapter plate for testing at least one single chip in a wafer probing system.

Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.

Abstract: The invention relates to a marking device (02) for marking circuit boards (04) tested by means of a test device (01, 08), wherein the marking device (02) can be fixed to the test device (01, 08) in a defined target position, and wherein the marking device (02) has a marking member (06) which can engage the surface (05) of a circuit board (04), and wherein the marking member (06) can be driven by a drive mechanism (16) in order to apply a marking to the surface (05) of the circuit board (04) by an operating movement of the marking member (06) depending on the test result. The marking device (02) includes a fixation module (10) and a quick change module (11), wherein the marking device (02) can be fixed to the test device (01, 08) in the defined target position by means of the fixation module (10), and wherein the quick change module (11) includes the marking member (06) and the drive mechanism (16), and wherein the quick change module (11) can be replaced without removing the fixation module (10).

Abstract: A test system of embodiments electrically connects one or more first semiconductor chips formed on a first wafer and one or more second semiconductor chips formed on a second wafer to perform tests on the one or more first and second semiconductor chips. The test system includes a test device that supplies a test signal to each of the one or more first semiconductor chips, a first probe device including a first probe to be connected to a first internal pad of each of the one or more first semiconductor chips and a first communication circuit configured to transmit and receive a signal, and a second probe device including a second probe to be connected to a second internal pad of each of the one or more second semiconductor chips and a second communication circuit configured to transmit and receive the signal to and from the first communication circuit.

Abstract: The present application discloses a testing device of array substrates and a testing method. The testing device of array substrates includes: a machine and testing interfaces, the testing interfaces being disposed on the machine; and testers disposed above the machine. There are at least two sets of testers, and the testers synchronously operate according to a preset scheme.

Abstract: An assembly sheet includes a plurality of suspension boards and a frame member that integrally supports the suspension boards. On a surface of the frame member, a plurality of identification marks for identifying respective positions of the suspension boards in automatic optical inspection are provided corresponding to the suspension boards.

Abstract: A method of testing a semiconductor device using the test equipment includes loading an undivided printed circuit board (PCB) including unit PCBs in a test equipment. A semiconductor device is mounted in each of the unit PCBs. Product information of the undivided PCB loaded in the test equipment is confirmed. The undivided PCB whose product information has been confirmed is electrically connected to one of a plurality of main testers of the test equipment. Each of the main testers includes a main test interface directly connected to a cloud server in which firmwares for various kinds of tests are stored. The product information of the undivided PCB is transmitted to the main tester electrically connected to the undivided PCB. The main tester to which the product information has been transmitted performs a main test of the undivided PCB using the product information. The undivided PCB on which the main test has been performed by the main tester is unloaded from the test equipment.

Abstract: A method and system increase processed specimen yield in the laser processing of target material that includes multiple specimens formed on a common substrate. Preferred embodiments implement a feature that enables storage in the laser processing system a list of defective specimens that have somehow been subject to error during laser processing. Once the common substrate has been completely processed, the system alerts an operator to the number of improperly processed specimens and gives the operator an opportunity to run a software routine, which in a preferred embodiment uses a laser to scribe a mark on the top surface of each improperly processed specimen.

Abstract: An apparatus and method for inspecting whether marking of a target chip in a wafer has been performed normally are provided. The apparatus includes a voltage application detector which detects application of a voltage to an external circuit, an image pickup unit which captures an image, and a controller which controls the image pickup unit to capture an image at at least one predetermined point when the application of the voltage is detected by the voltage application detector and determines whether the marking of the target chip has been performed normally based on the captured image. Accordingly, extra time is not required to inspect whether the marking of the target chip in the wafer has been performed normally and the inspection is performed without using a prober operation program.

Abstract: Methods, apparatus, and products for visually marking computing components within a computing system are disclosed that include: detecting that a particular computing component has failed, wherein the particular computing component has a physical surface that may be altered with the application of some physical stimulus; and applying a requisite physical stimulus to the physical surface such that the appearance of the physical service is altered, thereby visually identifying that the component has failed.

Abstract: A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit board from the integrated circuit package; performing a dye mapping to analyze bonds between the integrated circuit package and the circuit board; and performing an analysis of the integrated circuit package.