Abstract: A backup voltage and frequency support method for a 100%-renewable energy sending-end grid, including: (S1) selecting a plurality of support nodes in the 100%-renewable energy sending-end grid; (S2) mounting a backup voltage and frequency support device at each support node; and (S3) dynamically adjusting an active power output of a renewable energy station of the 100%-renewable energy sending-end grid according to a frequency of a grid-connection point.

Abstract: A storage unit is used for storing a plurality of interface units. A disposition system then automatically manages interface units. A carrier is provided for accommodating an interface unit. The interface unit is configured for testing semiconductor elements in corresponding test devices. The storage unit is designed for storing a plurality of interface units, the storage unit having a plurality of compartments, each for accommodating one carrier, and each such carrier being designed to accommodate one interface unit. The storage unit comprises at least one alignment element for positionally accurate coupling of a handling device.

Abstract: A device management apparatus 31 communicates with a plurality of devices to be managed. When an imaging apparatus in which abnormality occurs is detected, or in a case where any imaging apparatus is specified by a user from the imaging apparatuses in which the abnormality occurs, the device management apparatus 31 communicates with the imaging apparatus located within a specific range based on a position of the detected imaging apparatus in which the abnormality occurs or the imaging apparatus in which the abnormality occurs specified by the user, and performs the device specification display using a display unit of the imaging apparatus located within the specific range. By referring to the device specification display, the user may easily specify a desired device, for example, the device in which the abnormality occurs from a plurality of devices.

Abstract: A method of testing objects and an apparatus for performing the same, the method including loading the objects into a testing unit through a loading unit; testing the objects in the testing unit and determining whether the objects are normal objects or abnormal objects; unloading the tested objects from the testing unit to an unloading unit; directly reversely loading the abnormal objects from the unloading unit into the testing unit when the objects are determined to be abnormal objects; and re-testing the abnormal objects in the testing unit.

Abstract: This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of wafers.

Abstract: A light-guiding cover structure includes a top cover unit and a light-guiding unit. The top cover unit has a plurality of receiving spaces formed therein. The light-guiding unit includes a plurality of light-guiding groups, wherein each light-guiding group includes a plurality of optical fiber cables received in the corresponding receiving space, and each optical fiber cable has two opposite ends exposed from the bottom surface of the top cover unit and respectively facing at least one light-emitting device and at least one light-sensing device that have been disposed under the top cover unit. Therefore, the optical fiber cables received in the corresponding receiving space, thus when the light-guiding cover structure is applied to the LED package chip classification system, the aspect of the LED package chip classification system can be enhanced.

Abstract: System and method using low voltage current measurements to measure voltage network currents in an integrated circuit (IC). In one aspect, a low voltage current leakage test is applied voltage networks for the IC or microchip via one or more IC chip connectors. One or multiple specifications are developed based on chip's circuit delay wherein a chip is aborted or sorted into a lesser reliability sort depending whether the chip fails specification. Alternately, a low voltage current leakage test begins an integrated circuit test flow. Then there is run a high voltage stress, and a second low voltage current leakage test is thereafter added. Then, there is compared the second low voltage test to the first low V test, and if the measured current is less on second test, this is indicative of a defect present which may result in either a scrap or downgrade reliability of chip.

Abstract: Disclosed is a method for automatically sorting LEDs (light emitting diode) according to electrostatic resistance and a system using the same. The system includes a transport carrier for laying LEDs and passing LEDs through an electrostatic discharging zone, a lightening evaluating zone, and a sorting zone in sequence. An electrostatic discharging device discharges an electrostatic power to the LED in the electrostatic discharging zone. Furthermore, a lighting device inputs a lightening power to the LED in the lightening evaluating zone. Moreover, an evaluating device in the evaluating zone generates an evaluating signal to a sorting device in the sorting zone according to the lighting condition of the LED for allowing the sorting device to sort LEDs according to electrostatic resistance. Thereby the reliability both for the failure rate and the detection rate can be raised.

Abstract: An LED package chip classification system includes a rotation unit for transporting a plurality of LED package chips, a chip test unit, and a chip classification unit. The rotation unit includes a rotary turntable, a plurality of receiving portions formed on the rotary turntable, and a plurality of suction-exhaust dual-purpose openings respectively disposed in the receiving portions. Each LED package chip has a positive electrode pad and a negative electrode pad disposed on the bottom side thereof. The chip test unit includes a chip test module adjacent to the rotation unit for testing each LED package chip. The chip classification unit includes a plurality of chip classification modules adjacent to the rotation unit for classifying the LED package chips. Therefore, the LED package chips can be classified by matching the rotation unit, the chip test unit, and the chip classification unit.

Abstract: A packaged chip detection and classification device includes a rotation unit for transporting a plurality of packaged chips, a packaged chip detection unit, and a packaged chip classification unit. The rotation unit includes a rotary turntable, a plurality of receiving portions formed on the rotary turntable, and a plurality of suction-exhaust openings respectively formed in the receiving portions. Each receiving portion is used to selectively receive at least one of the packaged chips. The packaged chip detection unit includes a packaged chip detection module adjacent to the rotation unit for detecting each packaged chip. The packaged chip classification unit includes a packaged chip classification module adjacent to the rotation unit for classifying the packaged chips. Therefore, the packaged chip detection and classification device can be used to detect and classify no-lead packaged chips by matching the rotation unit, the packaged chip detection unit, and the packaged chip classification unit.

Abstract: A test handler is provided, which comprises a test tray, at least one opening unit, and a position changing apparatus. The test tray aligns a plurality of inserts on its side. Each insert loads at least one semiconductor device thereon. The opening unit opens inserts at one part of the one side of the test tray. The position changing apparatus moves at least one opening unit in such a way that the at least one opening units can be located at another part of the one side of the test tray, such that the at least one opening units can open inserts at said another part of the one side of the test tray. The present invention can reduce the number of replaced parts according to change in the semiconductor device size, production cost, and part replacement time.

Abstract: A testing device includes a laser source, a current testing device, and a processor. The processor includes a user interface, a control unit, a calculation unit, and a data generation unit. The user interface receives user inputs to determine control parameters. The control unit controls the laser source to emit a laser beam on a photoelectric conversion die according to the control parameters. The laser beam has an optical output power value P. The control unit also controls the current testing device to measure a current value I output by the photoelectric conversion die after the laser beam irradiating on the photoelectric conversion die. The calculation unit calculates a photoelectric conversion efficiency F according to the formula: F=P/I. The data generation unit processes the photoelectric conversion efficiency F which indicates the electro-optical property of the photoelectric conversion die.

Abstract: A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.

Abstract: A method for screening electrolytic capacitors places a capacitor in series with a resistor, applying a test voltage and following the charge curve for the capacitor. A high voltage drop across the capacitor indicates high reliability and a low voltage drop is used to reject the piece. The leakage current is not adversely affected during the test.

Abstract: A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.

Abstract: The present disclosure provides a semiconductor test system. The semiconductor test system includes a wafer stage to hold a wafer having a plurality of light emitting devices (LEDs); a probe test card operable to test each test field of the wafer; and a light detector integrated with the probe test card to collect light from a LED of the wafer.

Abstract: This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of wafers.

Abstract: An improved method and apparatus for testing and sorting electro-optic devices by both electrical and optical properties at high speed is disclosed. Electro-optic devices, in particular light emitting diodes, are singulated by a singulation device and transferred to a linear track where they are tested for electrical and optical properties. The devices are then sorted into a large number of different bins depending upon the tested properties.

Abstract: An equipment and method to classify semiconductor packages diced on a substrate into defective and non-defective semiconductor packages includes a loading preparation table to receive a plurality of semiconductor packages to be inspected, a first inspection unit to inspect and classify the semiconductor packages received at the loading preparation table into normal semiconductor packages and defective semiconductor packages, a temporary loading table to temporarily receive at least a portion of the normal semiconductor packages, a first loading picker to transfer the defective semiconductor packages from the loading preparation table to a defective package loading tray and to transfer the normal semiconductor packages from the temporary loading table to the loading preparation table, and a second loading picker to transfer the normal semiconductor packages from the loading preparation table to a normal package loading tray.

Abstract: A method and apparatus are provided for implementing optimized speed sorting of microprocessors at wafer test. A combination of speed-predicting metrics are measured early in the manufacturing process and are applied to a unique algorithm to properly sort parts into appropriate speed bins. The method significantly improves the accuracy of predicting the chip speed over conventional speed-predicting methods.

Abstract: A chip test method is disclosed and includes: loading chips on a chip tray and fastening a cover plate on the chip tray; loading the chip tray with the cover plate in a chip test device; aligning a probe card of the chip test device with a test unit of the chip tray; testing chips in the chip tray; sorting the passed chips from the failed chips.