Abstract: A clock data recovery circuit is disclosed. The clock data recovery circuit includes a bit stream data rate divider and a digital phase-locked loop including a linear phase detector. The bit stream data rate divider is configured to divide a frequency of a serial data stream by a designated division factor to generate a divided serial data stream. The linear phase detector is configured to compare phases of the divided serial data stream and a feedback signal within the digital phase-locked loop and output an UP signal associated with phase lagging and a DOWN signal associated with phase leading of the feedback signal versus the divided serial data stream. The digital phase-locked loop is configured to output a clock signal having a phase based on a digital difference between a digitized-UP signal derived from the UP signal and a digitized-DOWN signal derived from the DOWN signal.

Abstract: A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit.

Abstract: A phase locked loop (PLL) includes a first charge pump coupled to a filter. The first charge pump may feed the filter a first current. A second charge pump is coupled to the filter. The second charge pump may feed the filter a second current. A first gate is coupled to an input of the second charge pump. The first gate selectively gates the second current.

Abstract: A resonance contactless power supply device can include: (i) a converter configured to convert an input power signal to an adjustable DC voltage; (ii) an inverter configured to receive the adjustable DC voltage, and to generate an AC voltage with a leakage inductance resonance frequency; (iii) a first resonance circuit having a transmitting coil, and being configured to receive the AC voltage from the inverter; (iv) a second resonance circuit comprising a receiving coil that is contactlessly coupled to the transmitting coil, where the second resonance circuit is configured to receive electric energy from the transmitting coil; and (v) a control circuit configured to control the adjustable DC voltage according to a phase difference between the AC voltage and an AC current output by the inverter, such that the phase difference is maintained as a predetermined angle.

Abstract: A wireless sensor reader is provided to interface with a wireless sensor. The wireless sensor reader transmits a narrowband, fixed frequency excitation pulse to cause the wireless sensor to generate a ring signal. The ring signal corresponds to the value of the physical parameter being sensed. The wireless sensor reader receives and amplifies the ring signal and sends the signal to a phase-locked loop. A voltage-controlled oscillator in the phase-locked loop locks onto the ring signal frequency and generates a count signal at a frequency related to the ring signal frequency. The voltage-controlled oscillator is placed into a hold mode where the control voltage is maintained constant to allow the count signal frequency to be determined. The low power, simple circuitry required to generate the excitation pulse allows the reader to be a small, battery operated unit. Alternative methods of frequency determination are also disclosed.

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Abstract: A degradation detection circuit may include a degradation unit including multiple delay elements driven by a high voltage for degradation. The high voltage for degradation value may be higher than an operation voltage. The degradation unit may be configured to provide a first delayed signal after passing a test signal through the degradation unit, wherein the test signal retains a pulse for a preset time. The degradation detection circuit may include a reference unit including a plurality of delay elements driven by the operation voltage, and configured to provide a second delayed signal after passing the test signal through the reference unit, a delay setting unit configured to provide a third delayed signal by selectively adding delay elements with respect to the second delayed signal, and a delay checking logic configured to detect a delay of the test signal by comparing the first delayed signal and the third delayed signal.

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Abstract: The invention provides a tunable coherent optical receiver and a related method wherein the receiver uses low-frequency trace-tone modulation of optical WDM channels at transmission as channel IDs in order to detect which optical channels are present in the received optical WDM signal. The receiver than discriminates between the thereby detected optical channels by tuning a local oscillator to one of the received optical channels as determined based on the presence of the low-frequency tones in the received optical signal.

Abstract: Disclosed is an apparatus and method for detecting failure of a switching device in an inverter, the method including detecting a maximum value and a minimum value of a phase current inputted into a motor from synchronous angle information of the motor through a switching device in a predetermined leg of the inverter unit, and detecting failure of the switching device of the leg through an asymmetry ratio of the phase current.

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Abstract: Various aspects of the present invention relate to techniques of measuring delays between edges of signals of a circuit. Alternating signals, synchronous to a first clock, are supplied to a plurality of nodes of the circuit. First samples of a plurality of signals associated with the alternating signals are captured using a first capture clock, of which sampling instants are synchronous to a second clock. Second samples of the first samples are then captured using a second capture clock, of which sampling instants are also synchronous to the second clock. The captured second samples are conveyed via a shift register to a plurality of modulo counters. The measured signal delay includes a timing skew associated with the first clock and a timing skew of the first capture clock but not a timing skew of the second capture clock.

Abstract: A transceiver circuit for self-test of jitter tolerance is disclosed. The transceiver circuit includes a transmitter circuit having an output coupled to an output terminal of the transceiver and a receiver circuit having in input coupled to an input terminal of the transceiver. The transceiver also includes a loopback path configured to provide a signal transmitted by the transmitter circuit to the input of the receiver circuit. The transceiver also includes a test control circuit that causes jitter to be introduced in the signal transmitted by the transmitter circuit when the test control circuit is operating in a self-test mode, but not when the test control circuit is operating in a non-test mode.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: A small signal feedback loop or feed-forward loop having gain provides substantially unconditional instability in a phase locked loop when a reference phase signal is lost. The small signal feedback or feed-forward also modifies phase locked loop bandwidth when the reference phase signal is lost to increase rapidity of response to loss of reference phase signal while maintaining insensitivity to reference voltage amplitude change while the reference phase signal is present. The performance thus achieved is particularly suitable for rapid condition detection response and control of a grid connected power converter under islanding conditions.

Abstract: An element measurement circuit is provided, comprising a oscillator for generating a first oscillation clock and second oscillation clock, a frequency divider for dividing the first oscillation clock to generate a third oscillation clock and for dividing the second oscillation clock to generate a fourth oscillation clock, a frequency detector for detecting the third oscillation clock to generate a first count value and for detecting the fourth oscillation clock to generate a second count value, and a controller for generating a first oscillation period according to the first count value, for generating a second oscillation period according to the second count value, and for generating a measurement value according to the first oscillation period and the second oscillation period.

Abstract: A small signal feedback loop or feed-forward loop having gain provides substantially unconditional instability in a phase locked loop when a reference phase signal is lost. The small signal feedback or feed-forward also modifies phase locked loop bandwidth when the reference phase signal is lost to increase rapidity of response to loss of reference phase signal while maintaining insensitivity to reference voltage amplitude change while the reference phase signal is present. The performance thus achieved is particularly suitable for rapid condition detection response and control of a grid connected power converter under islanding conditions.

Abstract: A dF/dT trigger system and method includes instantaneously triggering on a frequency deviation of a data signal, which can be associated with an SSC signal. After receiving a signal at an input terminal of a test and measurement instrument, the signal is low-pass filtered and transmitted to trigger circuitry. When a frequency deviation rate in the filtered signal exceeds or crosses one or more thresholds, a trigger event is produced. Also disclosed is a test and measurement instrument including an input terminal to receive the signal, input circuitry to receive and process the signal, and dF/dT trigger circuitry configured to receive the signal and produce a trigger event when a frequency deviation in the signal exceeds or crosses one or more thresholds.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.

Abstract: Provided is a measurement apparatus that measures a signal under measurement, comprising a first oscillation circuit that receives one pulse of the signal under measurement and begins oscillating according to the pulse of the signal under measurement to output a first oscillated signal; a second oscillation circuit that receives one pulse of a reference signal and begins oscillating according to the pulse of the reference signal to output a second oscillated signal having a period that is different from a period of the first oscillated signal; and a first sampling section that samples the first oscillated signal according to a pulse of the second oscillated signal. The first oscillation circuit and the second oscillation circuit each include a control section that selects one pulse; a delay section that delays the pulse; and a loop line that feeds the pulse back to an input terminal of the delay section.

Abstract: A phase comparator (4) for detecting a phase difference between a first signal and a second signal, a first oscillating circuit (1) for supplying the phase comparator with a reference signal as the first signal, and a DDS (8) as a second oscillating circuit for outputting a signal according to an output of the above-mentioned phase comparator are provided. As for a filter-thickness measuring device using the PLL circuit as a frequency measurement circuit, a crystal oscillator (11) which is made of quartz etc. and connected to the first oscillating circuit is accommodated in a vacuum chamber (C). It is arranged that the frequency measurement circuit which constitutes the PLL circuit measures a film thickness of the film forming material based on a change of a natural frequency of a piezoelectric crystal, the change being caused by the film forming material deposited on the piezoelectric element in the vacuum chamber.

Abstract: A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured.

Abstract: A front end of a vector network analyzer (VNA) on an integrated circuit includes a clock generator and two ports. The VNA couples to a device under test (DUT) using the two ports. Each port may include a plurality of receivers and a VSWR bridge, and can be configured as either an input or an output. The clock generator can generate a stimulus signal, an in-phase I clock signal, and a quadrature-phase Q clock signal. The output port provides the stimulus signal to the DUT and measures both reference and reflected power from the DUT, such as by utilizing two receivers by using direct conversion and the I and Q clock signals. The input port measures transmitted power through the DUT using a second VSWR bridge and one of its receivers by using direct conversion along with the I and Q clock signals. The VNA IC can provide S-parameter measurements to a processing unit for further processing and/or analysis to compute the DUT S-parameters.

Abstract: A method may include performing a logical exclusive OR and a logical inverse exclusive or on an input reference signal and an output signal to generate an XOR signal and an XNOR signal, respectively. The method may also include generating a switch control signal indicative of whether a first phase of the input reference signal leads or lags a second phase of the output signal. The method may additionally include: (i) transmitting the XOR signal to an output of a switch if the first phase leads the second phase; and (ii) transmitting the XNOR signal to the output of the switch if the first phase lags the second phase. The method may further include generating a phase detector output signal indicative of a phase difference between the second phase based on a signal present on the output of the switch.

Abstract: Accelerometers have a number of wide-ranging uses, and it is desirable to both increase their accuracy while decreasing size. Here, millimeter or sub-millimeter wavelength accelerometers are provided which has the advantage of having the high accuracy of an optical accelerometer, while being compact. Additionally, because millimeter or sub-millimeter wavelength signals are employed, cumbersome and awkward on-chip optical devices and bulky optical mediums can be avoided.

Abstract: A method of determining a rotational state of a three-phase alternating voltage supply which is connected to a converter and rotating in an uncontrolled manner, wherein the converter is connected to an intermediate voltage circuit and comprises phase-specific upper and lower controllable switches, which are connected in series between the intermediate voltage circuit, free-wheeling diodes connected in parallel with each of the controllable switches, and resistive circuits connected in parallel with the lower controllable switches.

Abstract: Accelerometers have a number of wide-ranging uses, and it is desirable to both increase their accuracy while decreasing size. Here, millimeter or sub-millimeter wavelength accelerometers are provided which has the advantage of having the high accuracy of an optical accelerometer, while being compact. Additionally, because millimeter or sub-millimeter wavelength signals are employed, cumbersome and awkward on-chip optical devices and bulky optical mediums can be avoided.

Abstract: A power measurement device for sampling current or voltage signals of a power system to produce a 1-bit delta-sigma bitstream. The power measurement device includes a frequency locked loop for determining the power system frequency directly from the 1-bit delta-sigma bitstream. The frequency locked loop includes a 1-bit rotate CORDIC that is configured to produce difference signals having a multi-bit word for each bit of the 1-bit delta-sigma bitstream, and a phase error calculator that determines the difference between the phase of the power system frequency and a phase ramp generated from a frequency measurement value in a frequency register. The phase error calculator feeds back a phase correction signal to the frequency register to lock the frequency measurement value to the power system frequency.

Abstract: The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency or set of frequencies and a predetermined amplitude. The energizing signal is coupled to the sensor via magnetic coupling and induces a current in the sensor which oscillates at the resonant frequency of the sensor. The system receives the ring down response of the sensor via magnetic coupling and determines the resonant frequency of the sensor, which is used to calculate the measured physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal.

Abstract: Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

Abstract: A method and apparatus for determining AC voltage waveform anomalies. The apparatus comprises a threshold generator for generating at least one time-variant threshold based on information regarding an AC voltage waveform. The apparatus further comprises a threshold detector for comparing a sample of the AC voltage waveform to the at least one time-variant threshold to identify an AC voltage waveform anomaly.

Abstract: A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit.

Abstract: A method for tracking a variable resonance condition in a plasma coil during creation of plasma from a gas flowing in a plasma torch adjacent to the plasma coil comprises: providing a radio-frequency (RF) power source comprising a power amplifier that generates a radio-frequency power signal with an adjustable operating frequency; providing a high-voltage ignition charge from said RF power source to the gas in plasma torch so as to create an electrical discharge through said gas so as to create a test sample comprising a partial plasma state within said plasma torch; and applying an RF power signal from said plasma coil to said test sample in said plasma torch, wherein said adjustable operating frequency of said power amplifier tracks said variable resonance condition of said plasma coil such that said test sample in the plasma torch achieves a full plasma state.

Abstract: In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment.

Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: A system and method are disclosed for implementing a power source including a power amplifier that generates a radio-frequency power signal with an adjustable operating frequency. The power amplifier also generates a reference phase signal that is derived from the radio-frequency power signal. An impedance match provides the radio-frequency power signal to a plasma coil that has a variable resonance condition. A phase probe is positioned adjacent to the plasma coil to generate a coil phase signal corresponding to the adjustable operating frequency. A phase-locked loop then generates an RF drive signal that is based upon a phase relationship between the reference phase signal and the coil phase signal. The phase-locked loop provides the RF drive signal to the power amplifier to control the adjustable operating frequency, so that the adjustable operating frequency then tracks the variable resonance condition.

Abstract: The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency or set of frequencies and a predetermined amplitude. The energizing signal is coupled to the sensor via magnetic coupling and induces a current in the sensor which oscillates at the resonant frequency of the sensor. The system receives the ring down response of the sensor via magnetic coupling and determines the resonant frequency of the sensor, which is used to calculate the measured physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal.

Abstract: Delay-locked loops, signal locking methods and devices incorporating delay-locked loops are described. A delay-locked loop includes a forward loop path, a feedback loop path, and a phase detector. A test clock signal is temporarily switched to traverse the forward loop path and the feedback loop path. The phase detector is coupled to both the forward and feedback loop path circuits and is configured to periodically adjust responsive to a calculated loop delay of the test clock signal. The phase detector is thereafter able to stabilize at an improved rate.

Abstract: According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip.

Abstract: A clock test apparatus for a semiconductor integrated circuit includes a delay unit configured to delay an internal clock signal. A comparison unit compares the phase of an output signal of the delay unit with the phase of a reference clock signal. A phase discrimination unit receives a test mode signal, the reference clock signal, and an output signal of the comparison unit, thereby outputting a discrimination signal.

Abstract: The present invention determines the resonant frequency of a wireless sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency. The system receives the ring down response of the sensor and determines the resonant frequency of the sensor, which is used to calculate a physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal. The system identifies false locks by detecting an unwanted beat frequency in the coupled signal, as well as determining whether the coupled signal exhibits pulsatile characteristics that correspond to a periodic physiological characteristic, such as blood pressure.

Abstract: The present invention relates to an integrated electronic device for digital signal processing, which includes a reference clock input for receiving a reference clock, a phase locked loop (PLL), a phase interpolator (PI) coupled to the phase locked loop (PLL) for shifting a phase of an output clock signal of the PLL in a stepwise manner so as to generate a shifted output clock signal (PHI_out), a logic stage for determining the state of the reference clock signal (REF_CLK) multiple times during an edge of the shifted output clock for each phase shift, a storing means for storing information whether or not the determined state of the reference clock signal (REF_CLK) is stable for a phase of the shifted output clock signal (PHI_out), and an interface configured to read out the stored information for determining the jitter of the shifted output clock signal (PHI_OUT).

Abstract: An integrated circuit, a phase locked loop, a voltage tune probe and a method of screening an integrated circuit employing a phase locked loop thereof. In one embodiment, the integrated circuit includes: (1) an input/output port configured to provide an external interface lead for the integrated circuit, (2) a phase locked loop having a voltage tune line coupled to a voltage controlled oscillator and (3) a voltage tune probe having a first switch coupled to a second switch and a capacitor coupled therebetween. The first switch is coupled to the voltage tune line and the second switch is coupled to the input/output port. The switches provide a bidirectional connection between the external interface lead and the voltage tune line.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Abstract: Noise detection is performed by using the output of the phase comparator that the PLL comprises. The phase comparator outputs a signal that is based on the phase difference between the output of the voltage controlled oscillator and the reference signal. The phase difference reflects the effect of noise on the PLL and, in addition to the characteristics of the noise itself, such as the wave height value of the noise and the frequency component thereof, reflects the tolerance of the PLL to noise, whereby the level of risk that the system can actually be caused to malfunction can be judged.

Abstract: The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency or set of frequencies and a predetermined amplitude. The energizing signal is coupled to the sensor via magnetic coupling and induces a current in the sensor which oscillates at the resonant frequency of the sensor. The system receives the ring down response of the sensor via magnetic coupling and determines the resonant frequency of the sensor, which is used to calculate the measured physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal.

Abstract: The present invention determines the resonant frequency of a wireless sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency. The system receives the ring down response of the sensor and determines the resonant frequency of the sensor, which is used to calculate a physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal. The system identifies false locks by detecting an unwanted beat frequency in the coupled signal, as well as determining whether the coupled signal exhibits pulsatile characteristics that correspond to a periodic physiological characteristic, such as blood pressure.

Abstract: A system and method are disclosed for implementing a power source including a power amplifier that generates a radio-frequency power signal with an adjustable operating frequency. The power amplifier also generates a reference phase signal that is derived from the radio-frequency power signal. An impedance match provides the radio-frequency power signal to a plasma coil that has a variable resonance condition. A phase probe is positioned adjacent to the plasma coil to generate a coil phase signal corresponding to the adjustable operating frequency. A phase-locked loop then generates an RF drive signal that is based upon a phase relationship between the reference phase signal and the coil phase signal. The phase-locked loop provides the RF drive signal to the power amplifier to control the adjustable operating frequency, so that the adjustable operating frequency then tracks the variable resonance condition.

Abstract: There is provided an electric circuit that outputs a timing signal and a recovered clock.