Abstract: A method in a communication circuit recovers a clock signal. A voltage controlled oscillator is initialized by supplying a predetermined.number of pulses to a charge pump coupled to the voltage controlled oscillator so as to initialize the voltage controlled oscillator to near an operating frequency upon power up of . the clock recovery circuit.

Abstract: On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (P×N+A) 22 wherein each of P, N and A is an integer, A is variable and A<N, a phase comparator 23, and a charge pump 24. A low pass filter 25 having been confirmed to have standard characteristics is externally added to the semiconductor device 20 to construct a PLL circuit to be tested. The frequency divider 22 is of a pulse swallow type and has a control input for setting the integer A at ones in the vicinity of a value in normal use by user. The control input is connected to external terminals D0 and D1 of the semiconductor device 20 for simplifying a test. The semiconductor device 20 is judged whether it is acceptable or not in quality by checking whether or not the PLL circuit enters into a locked state within a given period in each cases of A=A1 and A=A2, where A1<A0<A2 and A0 is a value in normal use by user.

Abstract: A frequency detection circuit is disclosed that employs a phase lock loop circuit in operative cooperation with a microprocessor. The microprocessor provides a control signal to an oscillator of the phase lock loop circuit so as to control its free-running frequency. The microprocessor has prestored quantities that represents predetermined parameters for measuring the frequency components contained in a tone burst transmitted from a sonobuoy. The microprocessor provides an output signal if the measured parameters correspond to predetermined and desired parameters. The microprocessor has predetermined parameters for measuring the length of the tone burst. The microprocessor provides a serial output signal transmitting the frequency and tone burst length measurements.

Abstract: An on-chip built-in self test apparatus for a phase locked loop module that resides on an integrated circuit, receives a reference clock signal and provides an output clock signal. The apparatus generally comprises a finite state machine and testing circuitry. The finite state machine may be for (i) receiving the reference clock signal and for (ii) producing testing signals for the phase locked loop module. The testing circuitry may be coupled to the finite state machine for (i) receiving the output clock signal, (ii) determining whether the characteristics of the output clock signal meet a predetermined criteria for open and close loop phase locked loop module operation, and (iii) outputting a test signal that indicates proper phase locked loop module operation if the characteristics of the output clock signal meet the predetermined criteria.

Abstract: A frequency detection circuit is disclosed that employs a phase lock loop circuit in operative cooperation with a microprocessor. The microprocessor provides a control signal to an oscillator of the phase lock loop circuit so as to control its free-running frequency. The microprocessor has prestored quantities that represents predetermined parameters for measuring the frequency components contained in a tone burst transmitted from a sonobuoy. The microprocessor provides an output signal if the measured parameters correspond to predetermined and desired parameters. The microprocessor has predetermined parameters for measuring the length of the tone burst. The microprocessor provides a serial output signal transmitting the frequency and tone burst length measurements.

Abstract: A servo controller for correcting a read position of a head when reading data recorded on a recording medium. In accordance with the amplitude ratio of data signals read from each segment of a servo section defined on a recording medium, the servo controller generates an AGC signal corresponding to the next segment before reading the next segment. The data signal read from a phase detection segment of the servo section is amplified to an amplitude greater than the predetermined determination range. The amplified data signal is converted to a two-value digital signal in accordance with the determination range. The phase used during servo control is calculated in accordance with the digital signal.

Abstract: A phase-locked loop (PLL) is tested based on a divide-and-conquer strategy. First, digital components in the PLL are isolated from analog components and tested. Next, the digital components are connected to the analog components and the PLL is exercised by causing it to undergo a series of frequency transitions.

Abstract: A network analyzer using time sequenced measurements has a pair of switches for isolating respective mixers from a local oscillator source to ease problems caused by direct leakage from the signal source. The signal source is set to a desired measurement frequency and a local oscillator is set to a desired frequency so that, when mixed, a desired IF frequency is achieved. The signal source output is applied to a return loss bridge, to which also is coupled a device under test, and to a reference channel mixer. A return loss signal from the return loss bridge is applied to a test channel mixer. The LO output is applied in a time sequence via an LO switch first to the reference channel mixer and then to the test channel mixer. An output switch couples the respective mixers to a processor in the same time sequence to provide sequential measurements of magnitude and phase from which reflection coefficients are derived for the device under test.

Abstract: A method for automatically calibrating a phase locked loop (PLL) system includes estimating a frequency value of an input signal applied to the system. Based on the estimated frequency value, a driving signal is generated for a plurality of internal switches in the PLL system. A PLL system may also implement this automatic calibration method.

Abstract: In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential non-linearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is disclosed that enables the measurement device to be synthesized from an RTL description. The present invention is based on a single-stage VDL structure, which is used to mimic the behavior of a complete VDL. Furthermore, as test time is an important consideration during a production test, a method and system is provided that reduces test time at the expense of additional hardware.

Abstract: A phase detection circuit for a phase-locked loop clock recovery system is described which detects the phase difference between an incoming data signal and a clock. The phase detection circuit is configured to generate two phase detection signals, the difference of which is indicative of the phase error between the incoming data and the clock. The phase detection circuit provides improved performance at high frequencies as well as increased flexibility in design and fabrication. The phase detection circuit in one embodiment comprises four type-D flip-flops and two exclusive-OR (XOR) gates. An incoming data signal is fed to one D flip-flop which is enabled off of a rising or positive edge of the clock which in turn feeds its output to a second D flip-flop enabled off of the same clock edge. The same incoming data is also fed to a third D flip-flop which is enabled off of a falling or negative clock edge of the same clock signal.

Abstract: The analog phase frequency detecting apparatus includes the devices described below. The first frequency sensitive device is used to amplify a first input signal with a gain function, which changes responding to the frequency of the reference input signal. The transfer characteristic curve of the first frequency sensitive device includes a monotonous decrease (or increase) curve. The second frequency sensitive device is utilized to amplify an oscillating signal with the varying gain function responding to the frequency of the oscillating signal. The first and the second DC component extracting device is used to extract the direct current component of the first and the second amplified input signal. The comparing device is used to generate a frequency locking signal, in addition, the phase detecting device generates a phase locking signal when the phase of the reference input signal is equal to that of the oscillating signal.

Abstract: A high-resolution apparatus and method provide direct digital measurement of electrical properties such as resistance, capacitance or inductance. An excitation signal derived from a high-frequency source is applied to a network containing an unknown device to produce a network output signal with an amplitude that corresponds to the electrical property to be measured. Amplitude variations in the network output signal are converted to corresponding phase variations in a third signal by adding the network output signal to a reference signal that is phase shifted by 90-degrees with respect to the excitation. The third signal is then applied to a phaselocked loop that employs the above-mentioned high-frequency source in combination with a pulse delete circuit to produce an output that multiplies phase information contained in the third signal by orders of magnitude.

Abstract: In at least one implementation, a method is provided for testing a communication circuit having a clock recovery circuit. The method comprising initializing a voltage controlled oscillator to near an expected operating frequency upon power up of the clock recovery circuit by supplying a signal from an external tester.

Abstract: Integrated circuit devices and methods of operating same include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrated circuit device may include a DLL control circuit that generates a control signal that is responsive to a test mode signal. An oscillator circuit may generate a clock signal that is responsive to the test mode signal. This clock signal may be a high frequency clock signal, such as that used to drive a DLL circuit during a normal operation mode. A DLL circuit, which is responsive to the clock signal, may be configured to operate in either a test mode or a normal operation mode based on the control signal. By generating the clock signal at a high frequency, the DLL circuit may be evaluated during burn-in testing, for example, under conditions that are comparable to conditions during normal operation.

Abstract: A method for synchronizing a plurality of synchronizable oscillators is disclosed. The method includes monitoring a respective output signal of each synchronizable oscillator, each output signal having a respective frequency, generating a synchronization signal based on the output signal having the highest frequency of all of the output signals, and providing the synchronization signal to all of the synchronizable oscillators.

Abstract: A phase difference to duty-cycle circuit converts a phase shifted signal and a reference signal into a single signal having a duty cycle that is a function of the phase difference between the two signals. The single signal may be further converted to a single direct current (DC) value before being transmitted to external measurement circuitry. The external measurement circuitry, by simply measuring the magnitude of the DC signal, can determine the phase difference between the phase shifted signal and the reference signal. In an alternate embodiment, the phase shift in the target bit of a bit pattern is determined based on measurements of the DC voltage value of the shifted target bit pattern, the DC voltage value of first bit pattern comprising a non-shifted bit pattern representing a zero phase shift of the target bit, and a DC voltage value of a bit pattern comprising a non-shifted bit pattern representing a 100% phase shift of the target bit.

Abstract: A fast-locking phase detector includes a first input that receives a first signal, a second input that receives a second signal, and a comparison circuit that generates an output current in proportion to a phase difference between the first signal and the second signal. An operating point circuit selectively maintains a first operating point of the phase detector when a phase of the first signal leads a phase of the second signal, and maintains a second operating point of the phase detector when the phase of the first signal lags the phase of the second signal. The first and second operating points are different from one another. Each of the first and second operating points causes the output current to vary substantially linearly for a predetermined range of both positive and negative phase differences between the first signal and the second signal.

Abstract: A method of estimating the loop phase error in a negative feedback amplifier is disclosed which comprises applying a test signal to the input of the amplifier, modulating the phase of the feedback signal to be summed to the test signal input to the amplifier, measuring the amplitude of the forward signal of the amplifier at two harmonics of the frequency of the phase modulation, and estimating the loop phase error on the basis of said two amplitude measurements. Apparatus for carrying out such a method is also disclosed.

Abstract: A node (20) of a communications network extracts a reference signal from a transport network for use as a reference signal for the node. The node comprises a frequency locked loop (22) which filters the reference signal to the node, as well as a calibration system (24) which determines a tuning sensitivity factor (a) for the frequency locked loop. The calibration system performs a calibration procedure which includes the calibration steps of (1) obtaining a first error measurement (f1) when a first tuning data value is applied to the frequency locked loop; (2) obtaining a second error measurement (f2) when a second tuning data value is applied to the frequency locked loop; and, (3) using the first tuning data value, the second tuning data value, the first error measurement, and the second error measurement to determine the tuning sensitivity factor for the frequency locked loop.

Abstract: A phase meter precisely measures the phase of two signals with very different frequencies by using a sampler, permuter and a matched filter. The phase meter includes a sampler that samples the fast clock with the slow clock; a permuter that permutes the samples based on the frequencies of the fast and slow clocks; and a matched filter that sums sequences of the samples and generates maximum and minimum phase positions. The maximum and minimum phase positions indicate transition times in the fast clock. The filter can take the average of the minimum and maximum values to determine the phase of the fast clock at the middle point of a cycle. The phase meter can also be used with an interval counter to precisely adjust the transition count used by the interval counter to detect a number of cycles in the interval, and to account for partial cycles that fall within the interval.

Abstract: A phase detector with a linear gain characteristic includes two exclusive-OR gates with inputs connected to an input signal and an inverted input signal and a reference signal in a phase locked loop. The outputs of the exclusive-OR gates are connected to a plurality of switches. The switches are connected to a plurality of resistors and the resistors are connected together to form an output signal. Switches and resistors are selected in complementary pairs by a gain select function to provide a linear gain characteristic for the output signal.

Abstract: A phase frequency detector in a clock multiply unit of a serial transmitter detects differences in phase and frequency between a reference clock and an internal clock generated by the clock multiply unit. The phase frequency detector includes a reset circuit which increases the sensitivity and reliability of the phase frequency detector, thereby allowing the phase frequency detector to operate at high speeds. The phase frequency detector produces a pair of output signals which have rising edges corresponding to rising edges of the reference clock and the internal clock respectively. The reset circuit activates a reset signal to reset the phase frequency detector when the output signals are both at logic high and continues to activate the reset signal until both of the output signals reach logic low.

Abstract: An exemplary embodiment of the invention is a method for evaluating jitter of a phase locked loop circuit generating a phase locked loop output signal. The method includes generating a test initiate signal and generating a trigger signal in response to the test initiate signal. The trigger signal is synchronized with the phase locked loop output signal. A disturbance signal is generated to induce jitter in the phase locked loop output signal. The jitter in the phase locked loop output signal is then evaluated.

Abstract: A high-resolution apparatus and method provide direct digital measurement of electrical properties such as resistance, capacitance or inductance. An excitation signal derived from a high-frequency source is applied to a network containing an unknown device to produce a network output signal with an amplitude that corresponds to the electrical property to be measured. Amplitude variations in the network output signal are converted to corresponding phase variations in a third signal by adding the network output signal to a reference signal that is phase shifted by 90-degrees with respect to the excitation. The third signal is then applied to a phaselocked loop that employs the above-mentioned high-frequency source in combination with a pulse delete circuit to produce an output that multiplies phase information contained in the third signal by orders of magnitude.

Abstract: The invention provides a structure, method and means for receiving a reference frequency and a variable frequency, differentiating the frequencies, and generating a logic pulse in response to a first frequency leading a second frequency, the frequencies having a small phase difference. In an aspect, the invention maintains a signal when the reference frequency and the variable frequency transition. In another aspect, the invention provides additional timing balance to prevent early generation of the logic pulses. In another aspect, the logic pulses drive a charge pump used in one of a phase-locked loop and a delay-locked loop.

Abstract: An apparatus and method for determining, in real time, the key parameters of a three phase system electrical generator's output. A pair of reference vectors in quadrature (orthogonal) is phase-locked to a selected input open delta line to line voltage vector. Preferably, the cosine reference vector is locked 45° out of phase from the selected input vector whereby a best projection of the input vector onto the quadrature pair is provided and increases accuracy in subsequent magnitude and phase calculations. The phase-locked reference vectors provide a basis for computing the magnitude and phase angle for the remaining open delta line to line voltage vectors and three line to neutral current vectors.

Abstract: In one embodiment, a high-resolution measurement apparatus and method determine the position and motion of an object such as a human hand relative to a sensor array. Capacitance transferred to the array by the object within a sensor field produces minute phase changes in a fixed-frequency reference signal applied to the several elements of the array. The phase changes are measured by first heterodyning the phase-shifted reference signal with a second reference signal to obtain a low frequency intermediate signal, and then employing a phaselocked loop to multiply the phase information in the intermediate signal by orders of magnitude, thereby permitting the use of conventional methods to measure the resulting greatly magnified phase changes. Other embodiments provide direct digital measurement of unknown electrical properties, such as capacitance, inductance, and resistance.

Abstract: A clock synchronizing method is provided. The clock synchronizing method comprises the step of detecting a phase difference of a synchronous clock from a reference clock, and the step of varying a phase of the synchronous clock in one direction when the phase difference is not within a predetermined range, and varying the phase of the synchronous clock in one of the one direction and the other direction according to the phase difference when the phase difference is within the predetermined range.

Abstract: A timing signal generation circuit comprising: a negative feedback loop comprising; a variable delay circuit for outputting a timing signal delayed against an input clock signal by a delay amount designated by a delay code; a phase difference detector for detecting a phase difference between the timing signal and the input clock signal to output a detection signal; and a loop filter for smoothing a waveform of the detection signal to generate a voltage signal and feed the voltage signal back to the variable delay circuit: and a cancel unit for generating a reverse detection signal based on the delay code to cancel the phase difference caused by a change in delay amount. By the arrangement, a delay amount can be changed with high resolution in operation, while maintaining the phase lock state.

Abstract: A high frequency component is constructed such that the characteristics of a high frequency circuit that cannot be measured only by an outwardly extending terminal electrode are easily measured at the final-product stage. In the high frequency component, a substrate has an electrode pattern provided including a signal measuring electrode pad. Additionally, chip components are mounted on the substrate. A metal cover has a hole provided near the signal measuring electrode pad. Through the hole, a probe of a measuring apparatus is inserted from the outside to abut with the electrode pad. With the arrangement, a voltage signal obtained at a predetermined point of the high frequency circuit is measured.

Abstract: A frequency measurement test circuit includes a frequency divider, and a detection circuit. The frequency divider frequency-divides an input to be measured. The detection circuit outputs a signal of level set on the basis of a relationship in magnitude between the frequency of the signal frequency-divided by the frequency divider and that of a reference clock signal.

Abstract: A phase difference to duty-cycle circuit converts a phase shifted signal and a reference signal into a single signal having a duty cycle that is a function of the phase difference between the two signals. The single signal may be further converted to a single direct current (DC) value before being transmitted to external measurement circuitry. The external measurement circuitry, by simply measuring the magnitude of the DC signal, can determine the phase difference between the phase shifted signal and the reference signal. In an alternate embodiment, the phase shift in the target bit of a bit pattern is determined based on measurements of the DC voltage value of the shifted target bit pattern, the DC voltage value of first bit pattern comprising a non-shifted bit pattern representing a zero phase shift of the target bit, and a DC voltage value of a bit pattern comprising a non-shifted bit pattern representing a 100% phase shift of the target bit.

Abstract: A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.