Abstract: The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency or set of frequencies and a predetermined amplitude. The energizing signal is coupled to the sensor via magnetic coupling and induces a current in the sensor which oscillates at the resonant frequency of the sensor. The system receives the ring down response of the sensor via magnetic coupling and determines the resonant frequency of the sensor, which is used to calculate the measured physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal.

Abstract: A method for measuring the damping factor of an Nth-order phase-locked loop, wherein N>1, and a system, apparatus, and program that operate in accordance with the method. The method includes applying a modulation source at an input to the phase-locked loop. The method also includes measuring the output response to various levels of frequency modulation, measuring the ?3 dB cutoff frequency of the phase-locked loop, and measuring the peak frequency of the phase-locked loop. The method further includes calculating the damping factor of the phase-locked loop as a function of the ?3 dB cutoff frequency and the peak frequency.

Abstract: An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator.

Abstract: A circuit and method for monitoring a frequency divider. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.

Abstract: A method for reducing phase lock time and jittering and a phase lock loop (PLL) using the same adapted for PLL including a charge pump (CP) which includes a pull-up and a pull-down networks used for controlling output voltage of the CP. The output voltage is used for controlling frequency and phase of an output signal of the PLL. The method includes: receiving a reference and a feedback signals; setting the driving capabilities of the pull-up and the pull-down networks to a first driving capability when the phase difference between the reference and the feedback signals is greater than a predetermined value; setting the driving capabilities of the pull-up and the pull-down networks to a second driving capability when the phase difference between the reference and the feedback signals is smaller than the predetermined value, wherein the first driving capability is greater than the second driving capability.

Abstract: According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip.

Abstract: A method of determining a rotational state of a three-phase alternating voltage supply which is connected to a converter and rotating in an uncontrolled manner, wherein the converter is connected to an intermediate voltage circuit and comprises phase-specific upper and lower controllable switches, which are connected in series between the intermediate voltage circuit, free-wheeling diodes connected in parallel with each of the controllable switches, and resistive circuits connected in parallel with the lower controllable switches.

Abstract: A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.

Abstract: A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement to obtain a measured delay. The forward path delays the reference signal based on the measured delay to generate an internal signal. The feedback path includes a calibrating unit for generating the pulse based on a plurality of feedback signals generated from the reference signal. The delay lock circuit further includes a monitoring unit for monitoring the measurement. Based on the monitoring, the monitoring unit enables the calibrating unit to conditionally adjust the width of the pulse.

Abstract: The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency or set of frequencies and a predetermined amplitude. The energizing signal is coupled to the sensor via magnetic coupling and induces a current in the sensor which oscillates at the resonant frequency of the sensor. The system receives the ring down response of the sensor via magnetic coupling and determines the resonant frequency of the sensor, which is used to calculate the measured physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal.

Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: Methods and structure for improved high-speed TDF testing using an on-chip PLL and associated logic to generate high speed launch and capture pulses. A reference clock may be applied to a PLL circuit within the integrated circuit under test to generate a higher frequency PLL Clock. Gating Logic features and aspects within the integrated circuit may apply the PLL Clock signal to a TDF Clock signal when so directed by a TDF Enable signal from an external test system. The PLL Clock is applied to the TDF Clock signal path for precisely two clock pulses for use as a launch and capture pulse sequence for TDF testing at higher speeds than the external automated test system may achieve.

Abstract: A noise-resistive, burst-mode receiving apparatus including a voltage control signal generator for multiplying a frequency of a system clock signal and generating a voltage control signal having a level that corresponds to the multiplied frequency; a reset signal generator for delaying an irregular input signal in the unit of a packet, in response to the voltage control signal, performing an exclusive OR operation on the delayed and input signals, and outputting the result as a reset signal; a clock signal generator for generating a signal having a level that is changed at the middle point of each bit included in the packet as a recovered clock signal in response to the reset signal and the voltage control signal and outputting the recovered clock signal; and an output buffer for buffering the input signal and outputting the buffered signal as recovered data in response to the recovered clock signal.

Abstract: The present invention provides a capacitive sensing apparatus having utility in object detection security applications whereby the object detection field generated by the apparatus is made steerable. The apparatus includes a power source having a ground connection in communication with at least one sensing circuit operative to detect an object moving within the sensing field. At least one conductive element is provided in communication with electrical ground. To steer the direction of the sensing field, the relative position and distance between the conductive element and the sensing circuit is adjusted such that a desired sensing field pattern is obtained.

Abstract: A system and method are provided for adjusting the phase output of a Hogge phase detector. The method comprises: using a Hogge phase detector, generating a reference signal; using the Hogge phase detector, generating a phase and reference signals; accepting an adjust signal; modifying the amplitude of the phase signal in response to the adjust signal; integrating the amplitude modified phase signal; using the integrated signal as a phase adjusted signal; integrating the reference signal; using the integrated reference signal and phase adjusted signal to generate a voltage controlled oscillator (VCO) signal; at the Hogge phase detector, accepting the VCO signal as the clock signal. Some aspects of the method further comprise: using the VCO signal to sample data at a settled first phase of the clock; changing the adjust signal; and, using the VCO signal to sample data at a settled second phase of the clock.

Abstract: A method and device for generating a clock signal accurately synchronized with a wobble signal including jitter even if there are manufacturing differences between voltage controlled oscillators. The clock signal generation device includes a voltage controlled oscillator for generating a clock signal corresponding to each of a plurality of oscillation characteristics. The clock signal generation device applies a test voltage to a voltage controlled oscillator with a voltage control device and sequentially identifies a plurality of oscillation characteristics set for the voltage controlled oscillator. The clock signal generation device selects one of the identified oscillation characteristics that has a frequency range with a generally middle part in which the frequency of a wobble signal is located and has a smaller gain.

Abstract: The present invention provides a system and method for monitoring a short clock cycle on a semiconductor chip. The system includes a phase-locked loop (PLL) for receiving a reference clock as input and for outputting a PLL clock out. The system includes a delay-locked loop (DLL) for receiving the PLL clock out as input and for outputting a DLL phase offset clock. The DLL is locked to a frequency of the PLL clock out. The system may include an edge comparator for receiving the PLL clock out and the DLL phase offset clock as input. The edge comparator is suitable for monitoring each edge of the PLL clock out and each edge of the DLL phase offset clock, and for reporting a short clock cycle when an edge of the PLL clock out comes before an edge of the DLL phase offset clock.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: A method, system and program product to measure performance of a device dedicated to a phase locked loop (PLL). A resistor-inductor-capacitor (RLC) model is produced to simulate the PLL. The RLC model and the device to be measured are mapped together into a test circuit and the characteristics of the test circuit is analyzed to determine whether the device, if attached to the PLL represented by the RLC model, can meet the required standard of performance. This invention can be used to measure the performance of all kinds of devices attached to all kinds of PLLs.

Abstract: A test circuit within an existing design to enable the test circuit to test directly within the circuit. This invention provides a way to test and measure the leakage of the PLL loop filter capacitor leakage during test with a simple digital tester using existing pins. The test PLL circuit has circuit a plurality of capacitors and responsive amplifiers circuits for measuring leakage including a first capacitor set having multiple transistors coupled in series and with a reference resistor circuit coupled to a first amplifier and a second capacitor set having multiple transistors coupled in series and said reference resistor circuit coupled to a second amplifier to measure the leaking across the respective capacitors coupled to said first and second amplifiers and to provide an output of the leakage for measurement with the output of said first and second amplifiers.

Abstract: A method and an apparatus for testing a phase-locked loop (PLL) are provided. A fixed-level reference clock signal and a test feedback clock signal are applied to a phase-frequency detector (PFD) of the PLL to measure a minimum output frequency of a voltage-controlled oscillator (VCO) of the PLL. A test reference clock signal and a fixed-level feedback clock signal are applied to the PFD to measure a maximum output frequency of the VCO. The lock and capture range of the PLL is determined based on the maximum and minimum frequencies of the VCO.

Abstract: An instantaneous voltage dip detection device is provided with: all-pass filter (2) for phase shifting a supply voltage waveform (11) by 90°; a comparator 7 that outputs a signal when the supply voltage waveform (11) is smaller than a threshold (12) in regions of ?/4 to 3?/4, 5?/4 to 7?/4; a comparator (8) that outputs a signal when a phase shift voltage waveform (13) is smaller than a threshold (14) in regions of 0 to ?/4, 3?/4 to 5?/4, 7?/4 to 2?; an OR circuit (9) to which signals from the comparators (7), (8) are inputted; and a signal generator (10) for generating a voltage dip detection signal in response to an output from the OR circuit (9).

Abstract: A digital test module (5) is provided for testing a phase locked loop circuit. The module (5) includes phase detection circuitry (10) for performing phase measurements of the phase locked loop circuit and analog test circuitry (20) for testing at least one analog element of the phase locked loop circuit. Frequency measurement circuitry (30) is provided for performing frequency measurements of the phase locked loop circuit, as is circuitry (40) for performing calibration and jitter measurements. In this way cycle-to-cycle and phase jitter measurements may be made. A calibration mechanism is provided allowing a process evaluation to be made and which allows the jitter data to be provided in a few seconds. The fully digital design facilitates easy manufacture and ready retargeting of the module to diverse applications and processes.

Abstract: A test circuit receives a reference signal having a reference frequency and generates a synchronizer input signal having a synchronizer input frequency for inputting into a synchronizer circuit. A frequency generator is configured to offset the synchronizer input frequency at selectable frequencies from a nominal frequency value. An offset measurement circuit is configured to compare the frequency offset for the synchronizer input frequency with the frequency offset of a synchronizer output signal.

Abstract: A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: A test circuit for connecting a high-impedance node to an external test point when a test signal is enabled. The test circuit comprises: a first transmission gate switch for coupling the high impedance node to a first internal node of the test circuit when the test signal is enabled, the first transmission gate switch comprising a first N-channel transistor having a drain coupled to the high impedance node, a gate coupled to a Logic 1 when the test signal is enabled, and a source coupled to the first internal node. The test circuit also comprises a second transmission gate switch capable of coupling the first internal node to the external test point when the test signal is enabled and a biasing circuit for generating a negative Vgs bias on the first N-channel transistor when the test signal is disabled to thereby reduce leakage current in the first N-channel transistor.

Abstract: On a semiconductor device 20, fabricated are a VCO 10A, an frequency divider by integer R 21, a frequency divider by integer (P×N+A) 22 wherein each of P, N and A is an integer, A is variable and A<N, a phase comparator 23, and a charge pump 24. A low pass filter 25 having been confirmed to have standard characteristics is externally added to the semiconductor device 20 to construct a PLL circuit to be tested. The frequency divider 22 is of a pulse swallow type and has a control input for setting the integer A at ones in the vicinity of a value in normal use by user. The control input is connected to external terminals D0 and D1 of the semiconductor device 20 for simplifying a test. The semiconductor device 20 is judged whether it is acceptable or not in quality by checking whether or not the PLL circuit enters into a locked state within a given period in each cases of A=A1 and A=A2, where A1<A0<A2 and A0 is a value in normal use by user.

Abstract: A device and method for measuring the jitters of phase locked loop signals. A phase lead or phase lag relationship between an input signal and an output signal of a phase locked loop is found. According to the phase relationship and using multiplexers, a first phase difference signal and a second phase difference signal are re-routed to a subtraction unit and produces a jitter-level output signal. The jitter-level output signal represents the absolute value of the difference of pulse width between the first phase difference signal and the second phase difference signal.

Abstract: There is a desire to provide a testing method and apparatus that can be successfully integrated into a PLL and PLL-like circuits (e.g. frequency synthesizers, delay lock loops, etc.). It is desirable that the PLL or PLL-like circuit integrated with testing apparatus does not suffer from performance degradations during nominal (mission mode) operation. Furthermore, it is desirable that the PLL and the testing apparatus share the same interface. In order to produce a PLL having integrated testing apparatus, without having the PLL suffer severe performance degradations during nominal operation nor having the combination of the PLL and testing apparatus be unnecessarily large, a modified PLL integrated with testing apparatus is provided.

Abstract: The invention provides a method and circuit for measuring on-chip, cycle-to-cycle, jitter. Copies of a circuit comprising a programmable delay line, a programmable phase comparator, and two counters are placed at different locations on an IC near a clock signal. The programmable delay line creates a clock signal that is delayed by one clock cycle. This delayed clock signal is compared in time to the original clock signal by the programmable phase comparator. If the difference in time between the delayed clock signal and the clock signal is greater than the dead time, the first counter is triggered. If the difference in time is negative and the absolute value is greater than the dead time, the second counter is triggered. A statistical distribution, based on the values of the counters, is created. This distribution is used to predict on-chip, cycle-to-cycle jitter.

Abstract: A method and an apparatus for testing a phase-locked loop (PLL) are provided. A fixed-level reference clock signal and a test feedback clock signal are applied to a phase-frequency detector (PFD) of the PLL to measure a minimum output frequency of a voltage-controlled oscillator (VCO) of the PLL. A test reference clock signal and a fixed-level feedback clock signal are applied to the PFD to measure a maximum output frequency of the VCO. The lock and capture range of the PLL is determined based on the maximum and minimum frequencies of the VCO.

Abstract: A delay locked loop implementing design-for-test features to test for, among other, stuck-at-faults is provided. The delay locked loop uses multiplexers as design-for-test devices for controllability purposes and flip-flops as design-for-test devices for observability purposes. Such implementation of design-for-test features within a delay locked loop allows for pre-packaging delay locked loop verification and testing.

Abstract: The invention provides a structure, method and apparatus for receiving a reference frequency and a variable frequency, differentiating the frequencies, and generating a logic pulse in response to a first frequency leading a second frequency, the frequencies having a small phase difference. In an aspect, the invention maintains a signal when the reference frequency and the variable frequency transition. In another aspect, the invention provides additional timing balance to prevent early generation of the logic pulses. In another aspect, the logic pulses drive a charge pump used in one of a phase-locked loop and a delay-locked loop.

Abstract: A circuit for measuring absolute spread in capacitors implemented in planary technology. A charge pump supplying a charge current to an internal capacitor (Cint) is used, the voltage across the internal capacitor (Cint) being coupled through a comparator for comparing the voltage with first and second threshold levels. A bistable multivibrator reverses the direction of the charge current, to charge the internal capacitor (Cint) when the voltage decreases below the second threshold level, and to decharge the internal capacitor (Cint) when the voltage increases above the first threshold level. The charge current is determined by a reference voltage that is provided across an external resistor (Rext), the first and second threshold levels defining a voltage range being proportional to the reference voltage. An output signal of the bistable multivibrator is coupled to frequency measuring means to compare the repetition frequency thereof with a reference frequency.

Abstract: A calibration and adjustment system for post-fabrication control of a delay locked loop charge pump current is provided. The calibration and adjustment system includes an adjustment device that varies an amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the charge pump current may be stored and subsequently read to adjust the delay locked loop.

Abstract: A phase-locked loop with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. In addition, the dual-mode phase/frequency detector includes a digital phase/frequency detector, an analog phase/frequency detector, a charge pump, and a control unit. When the phase-locked loop circuit starts, the control unit causes a detection output signal from the dual-mode phase/frequency detector to correspond to a digital signal from the digital phase/frequency detector. When the phase-locked loop circuit approaches a lock state, the control unit causes the detection output signal to correspond to an analog signal from the analog phase/frequency detector. The phase-locked loop with dual-mode phase/frequency detection has the advantages of providing linear characteristics, fast switching speed, and high sensitivity.

Abstract: In an apparatus and a method for detecting a phase state capable of improving reliability of an air conditioner by preventing an abnormal operation of the air conditioner by detecting a phase state (antiphase and open-phase) of three phase AC power supplied to the air conditioner and displaying the detected phase state, the apparatus includes a phase detector for detecting first, second and third phases of a three phase current; an interrupt detector for detecting a falling edge of a pulse signal corresponded to the third phase of the detected first, second and third phases, recognizing an interrupt occurrence by the third phase when the falling edge is detected and generating a counting signal; a counter for counting a pulse signal corresponded to the first and second phases on the basis of the interrupt occurred-third phase according to the counting signal; an antiphase/open-phase detector for detecting a state as a normal connection state, an antiphase state on the basis of a pulse signal corresponded to t

Abstract: A digital test module (5) is provided for testing a phase locked loop circuit. The module (5) includes phase detection circuitry (10) for performing phase measurements of the phase locked loop circuit and analogue test circuitry (20) for testing at least one analogue element of the phase locked loop circuit. Frequency measurement circuitry (30) is provided for performing frequency measurements of the phase locked loop circuit, as is circuitry (40) for performing calibration and jitter measurements. In this way cycle-to-cycle and phase jitter measurements may be made. A calibration mechanism is provided allowing a process evaluation to be made and which allows the jitter data to be provided in a few seconds. The fully digital design facilitates easy manufacture and ready retargeting of the module to diverse applications and processes.

Abstract: An integrated circuit device having a self-resetting phase-locked loop (PLL) circuit. The PLL circuit generates an output clock signal having a first frequency in a first operating mode and a second frequency in a second operating mode, the second frequency being determined, at least in part, by a reference clock signal. A control circuit within the integrated circuit resets the PLL circuit by selecting the first operating mode for a predetermined time interval, then selecting the second operating mode.

Abstract: An integrated circuit for testing a PLL circuit that includes a phase error generator to receive a signal gained by dividing an oscillated signal from a voltage controlled oscillator and a reference signal so as to detect a phase error signal between the both, an integrating circuit to integrate error signals outputted by the phase error generation circuit, a reference voltage generator to generate a predetermined reference voltage, and a comparator configured to compare an integration result voltage outputted from the integrating circuit with a reference voltage generated by the reference voltage generation circuit, wherein the reference voltage generator and the comparison circuit is configured electrically outside of a loop in the PLL circuit.

Abstract: Measuring timing variations in a periodic signal includes producing trigger signals in an integrated circuit in response an externally-generated periodic signal. First and second oscillation signals are generated in response to the trigger signals. A first count of the number of pulses in the first oscillation signal from occurrence of the first oscillation signal until the oscillation signals are in phase and providing a second count of the number of pulses in the second oscillation signal from occurrence of the second oscillation signal until the oscillation signals are in phase.

Abstract: A calibration and adjustment system for post-fabrication control of a delay locked loop charge pump current is provided. The calibration and adjustment system includes an adjustment device that varies an amount of charge pump current. Such control of the charge pump current in a delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the charge pump current may be stored and subsequently read to adjust the delay locked loop.

Abstract: A Coherent Clock Measurement Unit (50) that measures PLL jitter in a coherent manner includes a master clock circuit (52) which provides a master clock signal at a first clock frequency. A first clock divide circuit (54) couples to receive the master clock signal to provide as reference clock signal at a second clock frequency. The phase lock loop input of a device under test (10) connects to receive the reference clock signal. In addition, a second clock divide circuit (56) couples to receive the master clock signal to generate a re-arm clock signal at a third clock frequency. A test measurement unit (58), that is clocked using the re-arm clock signal, receives the signal transmitted at the phase lock loop output to measure a predetermined interval of the signal at a predetermined time based upon the re-arm clock signal.

Abstract: A phase-locked loop (PLL) is tested based on a divide-and-conquer strategy. First, digital components in the PLL are isolated from analog components and tested. Next, the digital components are connected to the analog components and the PLL is exercised by causing it to undergo a series of frequency transitions.

Abstract: A device and method for measuring the jitters of phase locked loop signals. A phase lead or phase lag relationship between an input signal and an output signal of a phase locked loop is found. According to the phase relationship and using multiplexers, a first phase difference signal and a second phase difference signal are re-routed to a subtraction unit and produces a jitter-level output signal. The jitter-level output signal represents the absolute value of the difference of pulse width between the first phase difference signal and the second phase difference signal.

Abstract: In a phase detection circuit, an incoming data signal is fed to one D flip-flop which is enabled off of a rising or positive edge of the clock which in turn feeds its output to a second D flip-flop enabled off of the same clock edge. The same incoming data is also fed to a third D flip-flop which is enabled off of a falling or negative clock edge of the same clock signal. The output of which is in turn fed into a fourth D flip-flop which is enabled off of the same negative edge. The incoming data is also fed to a first XOR gate, along with the output of the first D flip-flop to generate the error phase detection signal. The outputs of the second and fourth D flip-flops are fed into a second XOR gate to generate the reference phase detection signal.

Abstract: A method is provided for testing a communication circuit. Power is applied to a clock recovery circuit. A precharge bit is provided to the clock recovery circuit after applying power to the clock recovery circuit. A predetermined number of pulses is provided to a charge pump coupled to a voltage controlled oscillator to initialize the voltage controlled oscillator to near an operating frequency.

Abstract: A network analyzer using time sequenced measurements has a pair of switches for isolating respective mixers from a local oscillator source to ease problems caused by direct leakage from the signal source. The signal source is set to a desired measurement frequency and a local oscillator is set to a desired frequency so that, when mixed, a desired IF frequency is achieved. The signal source output is applied to a return loss bridge, to which also is coupled a device under test, and to a reference channel mixer. A return loss signal from the return loss bridge is applied to a test channel mixer. The LO output is applied in a time sequence via an LO switch first to the reference channel mixer and then to the test channel mixer. An output switch couples the respective mixers to a processor in the same time sequence to provide sequential measurements of magnitude and phase from which reflection coefficients are derived for the device under test.

Abstract: A fast-locking phase detector includes a first input that receives a first signal, a second input that receives a second signal, and a comparison circuit that generates an output current in proportion to a phase difference between the first signal and the second signal. An operating point circuit selectively maintains a first operating point of the phase detector when a phase of the first signal leads a phase of the second signal, and maintains a second operating point of the phase detector when the phase of the first signal lags the phase of the second signal. The first and second operating points are different from one another. Each of the first and second operating points causes the output current to vary substantially linearly for a predetermined range of both positive and negative phase differences between the first signal and the second signal.