Abstract: Logic cells in an application-specific integrated circuit (ASIC) emulating standard gate sizing by duplicating elements within a single standard gate where logical high-drive gates are synthesized and converted to parallel elements as a post-process. The drive characteristics of the logical gates are retained during the conversion to the physical gate equivalents in the standard cell architecture. The logic cells in the device may include, for example, at least two two-input multiplexers.

Abstract: A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No. 6,590,800) and Flash technology. The circuit means is based on SCMOS-DTL gate arrays. Software means is based on the C++ procedures with levels of LUT. The SFPGA device supports GHz low power ASIC mixed signal product applications with embedded analog, logic, and memory array units. Several multiplexing schemes are disclosed, which accommodate tasks to vary the Vt and transmission line transmission of selected transistor or IO nets, and therefore their analog and digital device properties. A voltage doubler and supply booster and a Digital-Analog-Digital-Translator (DADT) apparatus are also disclosed in accordance with the present invention.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.

Abstract: An interconnection fabric using switching networks organized in multiple levels of hierarchy to allow flexible interconnections of the switching networks amongst different levels of hierarchy and on the same level of hierarchy. The resulting interconnection fabric can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.

Abstract: A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.

Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

Abstract: One embodiment of the invention provides an integrated circuit having a plurality of output drivers for driving signals from the integrated circuit and having a plurality of supply terminals to apply a supply voltage to the integrated circuit, the plurality of output drivers being supplied by the supply voltage, wherein the plurality of output drivers have a first output driver group having one or a plurality of the output drivers and a second output driver group having one or a plurality of the output drivers, wherein a first supply line segment is provided to supply the output drivers of the first output driver group, and a second supply line segment is provided to supply the output drivers of the second output driver group, wherein the first supply line segment may be supplied with the supply voltage via a first supply terminal and the second supply line segment may be supplied with the supply voltage via a second supply terminal, wherein the first supply line segment is electrically connected to the secon

Abstract: A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a long axis parallel with a direction of the first power line; and electrically connecting the dummy pattern to the first power line, based on placement results of the first power line and the dummy pattern.

Abstract: A semiconductor device includes: a cell region; a terminal region; a lower semiconductor layer; a intermediate semiconductor layer on the lower semiconductor layer including a super junction structure; a terminal upper semiconductor layer on the intermediate semiconductor layer; a terminal contact semiconductor region on a surface portion of the terminal upper semiconductor layer adjacent to the cell region; an insulation layer on the terminal upper semiconductor layer having a first part adjacent to the cell region with a small thickness and a second part adjacent to the first part with a large thickness; and a conductive layer in the cell region and a part of the terminal region, the conductive layer extending from the cell region to the part of the terminal region beyond the first part of the insulation layer.

Abstract: A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.

Abstract: A library cell, a method and/or a system for adding the cell to a circuit is disclosed. The method generally comprises a first step for generating a final layout of the cell having an area of interest in at least one upper layer within a first layer stack used for the circuit, the first layer stack including at most all of a plurality of physical layers available for fabrication. A second step may include placing the final layout in the circuit. A third step may route a network of the circuit through the cell using the at least one upper layer and avoiding the area of interest according to at least one of a plurality of rules.

Abstract: A semiconductor integrated circuit includes a MOS logic operating by first and second voltages; a switching transistor unit disposed between a supply terminal of the first voltage or the second voltage and the MOS logic, and turned on or off in response to a control signal so as to control a supply of the first or second voltage to the MOS logic; and a fuse unit disposed between the supply terminal of the first voltage or the second voltage and the switching transistor unit, for cutting off a supply of the first or second voltage to the switching transistor unit by a selective cut based on a test result. Whereby, a product development or production difficulty or a yield decrease based on a performance drop or leakage current increase in a circuit having a power gate or MTCMOS may be improved. In addition, a product development delay caused by a mask revision required at a transistor level may be improved in a revision of an NMOS or PMOS transistor.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A standard cell, placed between a power rail and a ground rail in an integrated circuit, has active areas with connecting arms that extend beneath the power rail and ground rail. The connecting arms conduct current between the power and ground rails and the source regions of transistors in the active areas. The connecting arms include segments extending from these source regions to points beneath the power and ground rails, and segments running longitudinally beneath the power and ground rails. The connecting arms replace metal wiring that would otherwise be required, enabling the size of the standard cell to be reduced.

Abstract: Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to routing signals to and from the input/output (I/O) pads. The programmable routing structure can include long conductors that transmit signals across the chip quickly without the delay encountered in shorter routing conductors. Signals can be routed to and from the I/O pads through vertical and horizontal dedicated routing conductors that bypass global routing conductors. The dedicated I/O routing structure allows signals to be driven onto the chip and off chip more quickly can be achieved through standard programmable routing structures. The dedicated I/O routing structure can be depopulated to reduce the number of programmable connections between the individual conductors, decreasing die area requirements.

Abstract: Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.

Abstract: Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.

Abstract: A mask-programmable logic device includes a macrocell having an external input/output port for “place-and-route” programming by addition of metallization layers. A programmable “fixed” layer allows the external input/output port to be isolated from the remainder of the macrocell so that it “floats,” allowing signals to be routed through the external input/output port when the macrocell is not in use, to reduce routing blockages. The macrocell also may have at least one internal input/output port, potentially connected to different logic circuits, and a programmable “fixed” layer that can be used to control which internal input/output port is connected to the external input/output port. By thus allowing multiple logic circuits to share a single external input/output port, routing blockages are reduced.

Abstract: A semiconductor design layout having a deep well structure for routing body-bias voltage is generated using standard pattern tiles and custom pattern tiles. These tiles have a tile shape and a tile size that fit an integer number of times into a grid unit of a grid for the semiconductor design layout.

Abstract: Data transmitter circuitry on a programmable logic device (“PLD”) includes a plurality of channels of serializer circuitry, and a plurality of clock multiplier units (“CMUs”), each of which is associated with a respective subplurality of the serializer channels. Each CMU includes multiple reference clock signal sources, multiple phase-locked loop (“PLL”) circuits, and circuitry for allowing any PLL to get its reference input from any of the reference sources. Raw and centrally processed clock signals produced by each CMU are distributed to the serializer channels associated with that CMU and, at least in the case of the centrally processed signals, to the serializer channels associated with another CMU. The signal that controls release of parallel data to each serializer channel can be an output signal of that channel, or it can be an output signal of any CMU from which that channel can get a clock signal.

Abstract: A method, apparatus and machine-readable medium for improving communication between logic elements in an integrated circuit (IC) is provided. This is achieved by using a point-to-point approach for IC placement and routing, to address the increase in complexity in terms of design size and/or Deep Sub-Micron physical effects. The method involves providing a separate conductor member between an output of a logic element and each of one or more logic elements for interconnecting the one or more logic elements with the logic element. The method further involves providing a separate buffer between the output of the logic element and each of the one or more logic elements for interconnecting the one or more logic elements with the logic element. Furthermore, the method involves interconnecting the output of the logic element and the one or more logic elements, using the provided separate conductor member, and the provided separate buffer.

Abstract: A signal processing system is taught to be formed by combining a crossbar array with programming circuitry and signal input circuitry so as to provide a linear transformation from a set of input signals to a set of output signals. Applications of such a system to waveform generation, signal filtering, communications, and pattern recognition are explained. In one embodiment the crossbar array of the signal processing system may be a molecular nanowire crossbar array in which the crossbar interconnects are addressed via dual arrays of scanning probe tips so as to provide an interface between the molecular crossbar electronics and conventional solid state electronics used in the programming and signal processing circuitry.

Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

Abstract: A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.

Abstract: A system and method for distributing signals throughout an integrated circuit (IC). The system comprises a transmitter unit and a plurality of receiver units. The transmitter unit combines a plurality of signals into a serial signal stream and couples the serial signal stream to a conductor for distribution to a plurality of destinations in the IC. There is a receiver unit at each of the plurality of destinations and connected to the conductor. Each receiver unit extracts one of the plurality of signals from the serial signal stream received on the conductor. The transmitter unit comprises a multiplexer circuit and a counter circuit and time multiplexes the plurality of signals to form a serial signal stream, wherein a signal is selected for a time slot based on a count value of the counter circuit. The counter signal is also supplied to each receiver unit, which uses the counter signal to determine when to latch a signal from the serial signal stream.

Abstract: An large scale integrated circuit (LSI) includes an input buffer for adjusting a signal input to an outer input terminal; an input side selector for outputting the signal to a first output side when a normal operation is specified and to a second output side when a test operation is specified; a logic circuit for performing a specific logic process and outputting the signal; a bypass circuit for transferring the signal from the second output side of the input side selector; an output side selector for selecting and outputting the signal from the logic circuit when the normal operation is specified and selecting and outputting the signal transferred through the bypass circuit when the test operation is specified; and an output buffer for amplifying and outputting the signal from the output side selector to an outer output terminal.

Abstract: A semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in the conductive state or the nonconductive state, and a plurality of circuit selection switching elements, wherein said circuit selection switching elements are driven in response to the circuit configuration instruction signal, control signals are output from the circuit selection switching elements. As the connection elements, preferably use is made of magnetoresistance effect elements or resistance control elements which become the conductive state or the nonconductive state in accordance with application of a magnetic field. As the circuit elements, use can be made of magnetoresistance effect elements or resistance control elements.

Abstract: A semiconductor integrated circuit able to reduce a load of a layout design when arranging switches in power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

Abstract: In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and at least one column of routing multiplexers driving interconnect lines that can be used to programmably interconnect the logic blocks. An output terminal of the logic block drives a vertically adjacent subset of the routing multiplexers in the column. Optionally, the tile also includes a second column of routing multiplexers. The logic block output terminal also drives a vertically adjacent subset of the routing multiplexers in the second column, and in some embodiments the two subsets are physically located in horizontal alignment with one another within the tile. The tile can also include a column of input multiplexers for the logic block. The logic block output terminal also drives a vertically adjacent subset of the input multiplexers, and the subsets of routing multiplexers and input multiplexers can be horizontally aligned within the tile.

Abstract: A semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in the conductive state or the nonconductive state, and a plurality of circuit selection switching elements, wherein said circuit selection switching elements are driven in response to the circuit configuration instruction signal, and control signals are output from the circuit selection switching elements. The connection elements may be magnetoresistance effect elements or resistance control elements which become the conductive state or the nonconductive state in accordance with application of a magnetic field. The circuit elements may also be magnetoresistance effect elements or resistance control elements.

Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors in each set of the second plurality of conductors substantially connect, through a second set of switches, to a third plurality of sets of conductors. Each conductor of a set of the third plurality sets of conductors either connects, physically, to one pin in each of a plurality of functional blocks or, through a third set of switches, to a subsequent fourth plurality sets of conductors. The SN is scalable for large sized sets of conductors and can be used hierarchically in, for example, an integrated circuit or in an electronic system.

Abstract: A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, and coupling second ends of the power switches to a power receiver of the logic circuit.

Abstract: A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.

Abstract: A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

Abstract: A layout of a programmable interconnect structure, comprising: an active region; and an even plurality of gate regions dividing the active region into a plurality of active stripes, said active stripes arranged into disjoint first, second and third sets; and a plurality of interconnect wires, each interconnect wire coupled to a contact in an active stripe of the first set; and an input wire coupled to a contact in each of the active stripes of said second set; and an output wire coupled to a contact in each of the active stripes of said third set; and a buffer layout comprising one or more buffer gate regions and one or more buffer active regions, wherein the input wire is further coupled to a buffer gate region and the output wire is further coupled to a buffer active region.

Abstract: Provided are a method and a system for designing an embedded system using a design process for building a general-purpose computer. Specifically, the embedded system design includes adding and removing add-on cards as needed during the development of the embedded system design. The add-on cards are easily obtainable and connect to a circuit board of the embedded system by selecting lines originating from the circuit board. The lines not selected are passed on to other add-on cards connected to previously connected add-on cards. After all the lines from the circuit board are either selected to connect to logic of the add-on cards or remain unselected, information regarding the add-on cards are used to generate a configuration image. The configuration image is transmitted to a programmable processor of the circuit board to enable communication on the selected lines, thus permitting the embedded system to function.

Abstract: Methods and apparatus are provided for harnessing the effects of process variations in a semiconductor device. In one example, implementing an electronic design based on collected performance parameters is provided. In general, a core is segmented into multiple core regions. A performance parameter can be collected from each of the core regions. The performance parameter can be collected with a performance measuring mechanism associated with the core region. The performance parameter can be correlated to the performance requirements of an electronic device portion, and the electronic design portion can be implemented in a core region that has a performance parameter matched to the needs of the electronic design portion. In this way, process variation effects are harnessed by optimizing the implementation of the electronic design in regions of the semiconductor device best suited the needs of each electronic design portion. Therefore, performance/power optimization of the semiconductor device can be realized.

Abstract: Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array. In some embodiments, several direct connections do not include any intervening circuits. On the other hand, in some embodiments, several direct connections have intervening circuits, which differ from the nodes in the array.

Abstract: A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: Some embodiments provide an IC with a configurable node array that has (1) two similar nodes within the interior of the array, and (2) two different connection schemes. The first connection scheme specifies a set of connections between the first node and a set of nodes in the array, while the second connection scheme specifies a second set of connections between the second node and a set of nodes in the array. The two nodes cannot connect to any nodes on the boundary of the array with any connection that is specified in any connection scheme.

Abstract: Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to routing signals to and from the input/output (I/O) pads. The programmable routing structure can include long conductors that transmit signals across the chip quickly without the delay encountered in shorter routing conductors. Signals can be routed to and from the I/O pads through vertical and horizontal dedicated routing conductors that bypass global routing conductors. The dedicated I/O routing structure allows signals to be driven onto the chip and off chip more quickly can be achieved through standard programmable routing structures. The dedicated I/O routing structure can be depopulated to reduce the number of programmable connections between the individual conductors, decreasing die area requirements.

Abstract: A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No. 6,590,800) and Flash technology. The circuit means is based on SCMOS-DTL gate arrays. Software means is based on the C++ procedures with levels of LUT. The SFPGA device supports GHz low power ASIC mixed signal product applications with embedded analog, logic, and memory array units. Several multiplexing schemes are disclosed, which accommodate tasks to vary the Vt and transmission line transmission of selected transistor or IO nets, and therefore their analog and digital device properties. A voltage doubler and supply booster and a Digital-Analog-Digital-Translator (DADT) apparatus are also disclosed in accordance with the present invention.

Abstract: Method and apparatus for configuring the operation of an integrated circuit. An integrated circuit with external programming capabilities is disclosed. A pin current source is provided for interfacing with at least one pin on the integrated circuit to control current flow there through to an external load interfaced to the at least one pin external to the integrated circuit. The external load has at least two discrete values. A voltage detector detects the voltage on the at least one pin and a state detector then compares the voltage on the at least one pin to at least two discrete voltage thresholds. Each of the discrete voltages is associated with a separate value of a control word, and the state detector is operable to determine the value of the control word associated with the detected voltage. The state detector then outputs the determined value of the control word.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes an interconnect circuit having a first set of input terminals and a set of output terminals. The interconnect circuit has several connection schemes for connecting the first input set to the output set. The IC also has a second set of input terminals for carrying a set of input signals, where at least several of the second set of input terminals overlap at least a plurality of the first set of input terminals. The IC further has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set. The interconnect circuit receives a control signal and based on this control signal connects the first input terminal set to the output set by using a particular one of the connection schemes.

Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE?Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Abstract: A mask configurable semiconductor device, comprising: a first module layer having a plurality of circuit blocks including at least one programmable logic block; and a second module layer deposited substantially above the first module layer, including a read only memory (ROM) configuration circuit to program said logic block to a user specification.

Abstract: A differential signal transmission cable structure for transmitting differential signals having GHz frequency band in the present invention is provided with a differential signal transmission pair cable 30 connecting a driver circuit 23a and a receiver circuit 23b, for transmitting differential signals having GHz frequency band, and a power supply ground transmission pair cable 31 connecting ground and a first power supply 26a connected to the driver circuit and ground and a second power supply 26b connected to the receiver circuit. Further characteristic impedance of the differential signal transmission pair cable is matched to that of the driver circuit and the receiver circuit, thereby enabling TEM waves of differential signals having GHz frequency band transmission mode to be maintained when the differential signals are transmitted.

Abstract: The present invention relates to a semicustom ASIC, in which a plurality of standard cell rows are arranged. The standard cell and basic cells used in a gate array are mixedly mounted on the same chip. Respective cell rows are composed of a plurality of standard cells with an empty space. The basic cells used in the gate array are arranged as dummy cells. They are disposed in wiring channel regions between the plurality of standard cells or empty spaces between the standard cells in a same standard cell row. Only the latter may be used if the channelless type standard cells are employed. A changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern. Since the circuit can be modified without change of gate polysilicon regions and source/drain regions underlying the metal wiring layers, design and manufacture can be effected in a short period of time.