Complementary Fet's Patents (Class 326/103)
  • Patent number: 10326437
    Abstract: A circuit device includes: a transmitting circuit that performs transmission of a signal by current-driving signal lines in a transmission period; a receiving circuit that receives a signal that a transmitting circuit of a communication partner has transmitted by current-driving the signal lines, in a reception period that is different from the transmission period; and terminating resistor circuits that can be connected to the signal lines, and whose resistance value in the transmission period is set to a value that is smaller than a resistance value in the reception period.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: June 18, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kota Muto, Toshimichi Yamada
  • Patent number: 10224911
    Abstract: An integrated circuit (IC) device includes a first input/output (I/O) buffer circuit. The first input/output buffer circuit includes first and second groups of stacked transistors. The first group of stacked transistors transfer signals formatted in accordance with only one signal protocol from the group of signal protocols. The second group of stacked transistors transfers the signals formatted in accordance with more than one signal protocols. In addition, integrated circuit device also includes a second input/output buffer circuit. The second input/output buffer circuit includes third and fourth groups of stacked transistors. The third group of stacked transistors transfers the signals formatted in accordance to the first signal transmission protocol from the group of signal transmission protocols. The fourth group of stacked transistors transfers the signals formatted in accordance to the plurality of signal transmission protocols from the group of signal transmission protocols.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 5, 2019
    Assignee: Altera Corporation
    Inventors: Tat Hin Tan, Choong Kit Wong, Ker Yon Lau, Hsiao Wei Su, Hoong Chin Ng
  • Patent number: 9966871
    Abstract: A rectifier including an autonomous type synchronous-rectification MOSFET is provided, which prevents chattering and through-current caused by a malfunction when a noise is applied. The rectifier includes: a rectification MOSFET for performing synchronous rectification; a determination circuit configured to input a voltage between a pair of main terminals of the rectification MOSFET, and to determine whether the rectification MOSFET is in on or off state on the basis of the inputted voltage; and a gate drive circuit configured such that a gate of the rectification MOSFET is turned on and off by a comparison signal from the determination circuit, and such that a time required to boost a gate voltage when the rectification MOSFET is turned on is longer than a time required to lower the gate voltage when the rectification MOSFET is turned off.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 8, 2018
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Tetsuya Ishimaru, Kohhei Onda, Junichi Sakano, Mutsuhiro Mori
  • Patent number: 9800156
    Abstract: Provided are an amplifier circuit capable of improving phase characteristics, and a voltage regulator including the amplifier circuit. The amplifier circuit is configured to amplify an input voltage and to output the input voltage, and includes a current source, a first transistor having a gate to which the input voltage is applied, and a second transistor having a gate to which a voltage synchronous with the input voltage is applied, and a source connected to a capacitor.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 24, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Masakazu Sugiura
  • Patent number: 9607569
    Abstract: To provide a small driver IC, in a pass transistor logic circuit that converts k-bit digital signals into analog signals, transistors supplied with a first-bit signal are arranged in a line in the channel width direction. The channel width of transistors supplied with second to kth-bit signals is made larger than (e.g., preferably larger than two times and smaller than eight times) that of the transistors supplied with the first-bit signal. The transistors are preferably arranged such that transistors of the same conductivity type are located adjacent to each other wherever possible.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: March 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Keita Sato
  • Patent number: 9564188
    Abstract: An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
  • Patent number: 9337834
    Abstract: A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 10, 2016
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Xi Chen, Gang-Yi Hu, Xue-Liang Xu, Xing-Fa Huang, Liang Li, Xiao-Feng Shen, Ming-Yuan Xu, Lei Zhang, Yan Wang, Rong-Ke Ye, You-Hua Wang, Xu Huang, Jiao-Xue Li
  • Patent number: 9306570
    Abstract: At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: April 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Satyanarayana Sahu, Joshua Lance Puckett, Ohsang Kwon, William James Goodall, III, Benjamin John Bowers
  • Patent number: 9280630
    Abstract: Circuitry including a logic circuitry portion and a delay circuitry portion, with the circuitry having the following features: (i) the logic circuitry is designed to receive a set of input signals including a first input signal and a second input signal; and (ii) the delay circuitry portion includes a transistor connected so that the first input signal gates the second input signal. In some embodiments, the first and second input signals are chosen because it is expected that the second input signal will arrive at the circuitry before the first input signal so that the gating of the second signal by the first signal will cause the logic circuitry portion to receive the first and second signals at substantially the same time. Also, circuitry where a first output signal from a logic circuitry portion is gated by a second output signal.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Daniel Lewis, Rahul M. Rao, Adarsh Subramanya
  • Patent number: 9236312
    Abstract: Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing. The oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash). The oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hong Yu, Hyucksoo Yang, Richard J. Carter
  • Patent number: 8975952
    Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 10, 2015
    Assignee: Honeywell International Inc.
    Inventors: Paul S. Fechner, Weston Roper, James D. Seefeldt
  • Publication number: 20150061727
    Abstract: At least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (DSP), programmable logic array (PLA), application specific integrated circuit (ASIC), etc., for controlling operation of the at least one analog signal compatible CMOS switch for switching analog signals, e.g., audio, video, serial communications, etc. The at least one analog signal compatible CMOS switch may have first and second states, e.g., single throw “on” or “off”, or double throw common to a or b, controlled by a single digital control signal of either a logic “0” or a logic “1”.
    Type: Application
    Filed: November 10, 2014
    Publication date: March 5, 2015
    Inventor: James K. Russell
  • Publication number: 20140375356
    Abstract: A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may be minimized. In one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 25, 2014
    Inventor: A. Martin Mallinson
  • Patent number: 8779799
    Abstract: A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiya Takewaki
  • Publication number: 20140132306
    Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Paul S. Fechner, Weston Roper, James D. Seefeldt
  • Patent number: 8638123
    Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 8618838
    Abstract: An integrated circuit includes a first plurality of transistors and a second plurality of transistors coupled together to form a standard cell that performs a logic function. Each of the first plurality of transistors is more critical to a speed of operation of the standard cell than any of the transistors of the second plurality of transistors. Each of the first plurality of transistors has a gate length longer than a gate length of any of the transistors of the second plurality of transistors.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 31, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Savithri Sundareswaran
  • Patent number: 8593178
    Abstract: A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: November 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Abe, Hironori Nagasawa
  • Patent number: 8525552
    Abstract: A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: September 3, 2013
    Assignee: Panasonic Corporation
    Inventors: Takashi Ando, Keiichi Kusumoto, Kenji Shimazaki, Kazuyuki Nakanishi, Tetsurou Toubou
  • Patent number: 8508256
    Abstract: A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: August 13, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuto Yakubo, Shuhei Nagatsuka
  • Patent number: 8508276
    Abstract: The latch circuit includes a transistor whose channel region is formed with an oxide semiconductor (OS). Data is held in a node that is electrically connected to an output terminal and one of a source and a drain of the transistor and brought into a floating state when the transistor is turned off. Note that the oxide semiconductor has a band gap wider than silicon and an intrinsic carrier density lower than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: August 13, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takehisa Hatano
  • Patent number: 8461875
    Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 11, 2013
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Lawrence T. Clark
  • Patent number: 8446175
    Abstract: An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: May 21, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Thomas John Aton
  • Patent number: 8446176
    Abstract: An integrated circuit ECO base cell module is formed with PMOS and NMOS gate electrode structures and power supply lines that are electrically separated from one another up to the second metal (M2) layer in a fixed circuit structure that may be reconfigured with one or more conductor elements formed above the M2 layer to form a predetermined circuit function.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 21, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jianan Yang, Darrin L. Hutchinson, Stephen G. Jamison
  • Patent number: 8443306
    Abstract: A multi-operation mode application specific integrated circuit (ASIC) implemented in fully-depleted silicon-on-insulator (FDSOI) includes an ASIC implemented in FDSOI having a plurality of operating modes, plurality of power rails, and a power supply that provides voltages for the first and second rails corresponding to the plurality of operating modes. The power rails include at least one VDD rail, at least one Vss rail, a first rail for biasing a NGP region of PMOS transistor devices in the ASIC, and a second rail for biasing a PGP region of NMOS transistor devices in the ASIC.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: May 14, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sang Hoo Dhong, Jiann-Tyng Tzeng, Kushare Mangesh Babaji, Ramakrishnan Krishnan, Lee-Chung Lu, Ta-Pen Guo
  • Patent number: 8390330
    Abstract: A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: March 5, 2013
    Assignee: STMicroelectronics S.R.L.
    Inventors: Luca Ciccarelli, Roberto Canegallo, Claudio Mucci, Massimiliano Innocenti, Valentina Nardone
  • Patent number: 8390331
    Abstract: Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: March 5, 2013
    Assignee: NXP B.V.
    Inventors: Hendricus Joseph Maria Veendrick, Leonardus Hendricus Maria Sevat
  • Patent number: 8383472
    Abstract: Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: February 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Huaxiang Yin, I-hun Song, Chang-jung Kim, Sang-wook Kim, Sun-il Kim
  • Patent number: 8384439
    Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: February 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-chul Park, I-hun Song, Young-soo Park, Kee-won Kwon, Chang-jung Kim, Kyoung-kook Kim, Sung-ho Park, Sung-hoon Lee, Sang-wook Kim, Sun-il Kim
  • Publication number: 20130043906
    Abstract: A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal.
    Type: Application
    Filed: March 19, 2012
    Publication date: February 21, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki ABE, Hironori Nagasawa
  • Patent number: 8373440
    Abstract: A three dimensional multilayer circuit includes a via array made up of a set of first vias and a set of second vias and an area distributed CMOS layer configured to selectively address said first vias and said second vias. At least two crossbar arrays overlay the area distributed CMOS layer. These crossbar arrays include a plurality of intersecting crossbar segments and programmable crosspoint devices which are interposed between the intersecting crossbar segments. The vias are connected to the crossbar segments such that each programmable crosspoint devices can be uniquely accessed using a first via and a second via.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: February 12, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dmitri Borisovich Strukov, R. Stanley Williams
  • Patent number: 8373443
    Abstract: An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: February 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Kengo Akimoto, Masashi Tsubuku
  • Patent number: 8357955
    Abstract: Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (?2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N?M?2) times the basic cell length which is appropriate to the single complementary transistor pair.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: January 22, 2013
    Assignee: Sony Corporation
    Inventor: Yoshinori Tanaka
  • Patent number: 8330494
    Abstract: A semiconductor device includes a first transistor included in a latch circuit, a second transistor that is included in the latch circuit and is formed in a well in which the first transistor is formed, the second transistor having a conduction type identical to that of the first transistor, and a well contact that is provided between the first transistor and the second transistor and connects a power supply to the well.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: December 11, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Taiki Uemura
  • Publication number: 20120293210
    Abstract: A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 22, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuto YAKUBO, Shuhei NAGATSUKA
  • Publication number: 20120293209
    Abstract: A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 22, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshiya TAKEWAKI
  • Publication number: 20120287712
    Abstract: A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for supplying a first operation voltage or a second operation voltage smaller than the first operation voltage; a P-type low-threshold transistor Tp for receiving the first or the second operation voltage from the power supply portion; and a N-type transistor Tn connected between the transistor Tp and a base potential. The transistors Tp, Tn construct a logic circuit. The power supply portion supplies the first operation voltage to the source of the transistor Tp in the enable state, and supplies the second operation voltage in a standby state. The second operation voltage is set so that voltage amplitude between gate and source of each transistor Tp, Tn is larger than the threshold value of the transistors Tp, Tn.
    Type: Application
    Filed: November 23, 2011
    Publication date: November 15, 2012
    Applicant: WINBOND ELECTRONICS CORP.
    Inventor: Hiroki Murakami
  • Patent number: 8294492
    Abstract: An ultra-low-power transconductance device is provided, (FIG. 1b, FIG. 1c), comprising a series connection of a transistor of a first channel type (A) and a transistor of a second channel type (B), the first channel type having a different polarity than the second channel type. The transistors each have a source, a drain and a gate. The source of the transistor of the first channel type (A) is coupled with the source of the transistor of the second channel type (B) and the drain of the transistor of the first channel type (A) is coupled with the gate of the transistor of the second channel type (B).
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: October 23, 2012
    Assignee: Universite Catholique de Louvain
    Inventors: David Bol, Denis Flandre, Jean-Didier Legat
  • Publication number: 20120235706
    Abstract: A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 20, 2012
    Inventor: Richard F.C. Kao
  • Patent number: 8253443
    Abstract: An interconnection architecture for multilayer circuits includes metal-insulator transition channels interposed between address leads and each bar in the multilayer circuit. An extrinsic variable transducer selectively transitions the metal-insulator channels between insulating and conducting states to selectively connect and disconnect the bars and the address leads. A method for accessing a programmable crosspoint device within a multilayer crossbar circuit is also provided.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: August 28, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Warren Robinett
  • Publication number: 20120194219
    Abstract: A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal.
    Type: Application
    Filed: April 5, 2012
    Publication date: August 2, 2012
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Alexander FISH, Arkadiy Morgenshtein
  • Patent number: 8222676
    Abstract: A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: July 17, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Publication number: 20120126853
    Abstract: A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal.
    Type: Application
    Filed: February 2, 2012
    Publication date: May 24, 2012
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Arkadiy MORGENSHTEIN, Alexander Fish, Israel A. Wagner
  • Publication number: 20120074985
    Abstract: In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 29, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hajime KIMURA
  • Patent number: 8125248
    Abstract: There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: February 28, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Publication number: 20120001655
    Abstract: A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.
    Type: Application
    Filed: April 28, 2011
    Publication date: January 5, 2012
    Applicant: STMicroelectronics S.r.I.
    Inventors: Luca CICCARELLI, Roberto Canegallo, Claudio Mucci, Massimiliano Innocenti, Valentina Nardone
  • Patent number: 8076957
    Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Masanori Isoda
  • Patent number: 8030970
    Abstract: The invention relates to a device for forming an electric circuit comprising logic means (30) generating and using small signals of intermediate levels between the device supply levels and means for detecting signals leaving the small signal range.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: October 4, 2011
    Assignee: Etat Francais, repr{acute over ())}{acute over (})}senté par le Secretariat General de la Defense Nationale
    Inventor: Loïc Duflot
  • Patent number: 7982504
    Abstract: An interconnection architecture for multilayer circuits includes an array of vias and a CMOS layer configured to selectively access the array of vias according to an address. The interconnection architecture also includes a crossbar stack which includes layers of intersecting wire segments with programmable crosspoint devices interposed between intersecting wire segments. The vias are connected to the wire segments such that each programmable crosspoint device is uniquely addressed and every address within a contiguous address space accesses a programmable crosspoint device.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 19, 2011
    Assignee: Hewlett Packard Development Company, L.P.
    Inventor: Warren Robinett
  • Patent number: RE45988
    Abstract: Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (?2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N?M?2) times the basic cell length which is appropriate to the single complementary transistor pair.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: April 26, 2016
    Assignee: SONY CORPORATION
    Inventor: Yoshinori Tanaka