Field-effect Transistor Patents (Class 326/102)
  • Patent number: 11276541
    Abstract: The present disclosure is related to a display panel. The display panel may include a plurality of switch units. Each of the plurality of the switch units may include a first electrode; a second electrode; a third electrode; a fourth electrode opposite the first electrode; a piezoelectric material layer between the first electrode and the fourth electrode; a connecting electrode above the fourth electrode and electrically insulated from the fourth electrode; and a driving transistor comprising a driving gate. The driving gate may be the third electrode. An orthogonal projection of the second electrode and an orthogonal projection of the third electrode on a plane of the connecting electrode may overlap the connecting electrode respectively.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 15, 2022
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhonghao Huang, Jun Wang, Yongliang Zhao, Seungmoo Rim, Taeyup Min
  • Patent number: 11094540
    Abstract: A manufacturing method of a crystallized metal oxide layer includes: providing a substrate; forming a first insulation layer on the substrate; forming a first metal oxide layer on the first insulation layer; forming a second metal oxide layer on the first insulation layer; forming a second insulation layer on the first metal oxide layer and the second metal oxide layer; forming a silicon layer on the second insulation layer; performing a first laser process on a portion of the silicon layer covering the first metal oxide layer; and performing a second laser process on a portion of the silicon layer covering the second metal oxide layer. An active device and a manufacturing method thereof are also provided.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 17, 2021
    Assignee: Au Optronics Corporation
    Inventors: Jia-Hong Ye, Ching-Liang Huang
  • Patent number: 11011119
    Abstract: The present disclosure relates to an array substrate and a display screen. The array substrate includes a first gate drive unit located in the non-display area and corresponding to pixels in the special-shaped display region, and a second gate driving unit located in the non-display area and corresponding to pixels in the non-special-shaped display region. A width-length ratio of a first output transistor of the first gate driving unit is smaller than a width-length ratio of a second output transistor of the second gate driving unit.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 18, 2021
    Assignee: KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventors: Longfei Fan, Longyan Wang, Zhanjie Ma, Siming Hu, Zhenzhen Han, Hui Zhu
  • Patent number: 10862463
    Abstract: A level shifter includes a power supply rail conversion block, an RS latch and a digital detection block. The power supply rail conversion block comprises a first NLDMOS transistor, a second NLDMOS transistor, a first PLDMOS transistor, a second PLDMOS transistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first inverter. A gate of the first NLDMOS transistor is connected to an input of the first inverter, a drain of the first NLDMOS transistor is connected to a drain of the first PLDMOS transistor; a source of the first NLDMOS transistor and a source of the second NLDMOS are connected to a referenced ground of an LV power supply rail. The digital detection block comprises a second inverter, a third inverter, a first delay chain, a second delay chain, a first NAND gate and a second NAND gate.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: December 8, 2020
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Zekun Zhou, Jianwen Cao, Zhuo Wang, He Tang, Bo Zhang
  • Patent number: 10847511
    Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Patent number: 10769513
    Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Patent number: 10522693
    Abstract: A memory device with excellent writing performance and excellent storing performance is provided. In the memory device, a first layer overlaps with a second layer. The first layer includes a first transistor including an oxide semiconductor as an active layer. The second layer includes a second transistor and a third transistor each including an oxide semiconductor as an active layer. The off-state current of a transistor formed in the first layer is lower than the off-state current of each of a transistor formed in the second layer. The field-effect mobility of the transistor formed in the second layer is higher than the field-effect mobility of the transistor formed in the first layer.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10325827
    Abstract: A base plate, and a plurality of unit structures formed on the base plate are provided. Each of the unit structures including an insulating substrate fixed on the base plate, a metal pattern formed on the insulating substrate, a semiconductor element electrically connected to the metal pattern, and a main electrode having an upper end portion exposed to the outside and a lower end portion connected to a peripheral portion of the metal pattern closest to an outer edge of the base plate.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: June 18, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Hasegawa, Kazuhiro Morishita, Ryo Tsuda, Yukimasa Hayashida, Goro Yasutomi, Ryutaro Date
  • Patent number: 10303633
    Abstract: A method of controlling a mode of a device is provided. The method includes determining a Vbus voltage on a Vbus pin in a USB connector on the device, comparing the Vbus voltage with a threshold, and configuring the device based on the comparison of the Vbus voltage and the threshold.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: May 28, 2019
    Assignee: Micro Motion, Inc.
    Inventors: Paul J Hays, Craig B McAnally, William M Mansfield, Brian T Smith
  • Patent number: 10275560
    Abstract: Embodiments relate to using placement grids corresponding to repeating track patterns of metal layers in a region to place circuit elements. Each placement grid is defined by as a vertical pitch of a repeating track pattern of one metal layer and a horizontal pitch of another repeating track pattern of another metal layer. Each circuit element is assigned with a placement grid so that it can be placed in alignment with the assigned placement grid. By using the placement grids derived from the track patterns, routable placement of circuit elements can be performed automatically or manually with reduced efforts.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 30, 2019
    Assignee: Synopsys, Inc.
    Inventors: Bulent Basaran, Jon Francis Bendicksen, Friedrich Gunter Kurt Sendig
  • Patent number: 10270448
    Abstract: A level shifter circuit is described herein for shifting a signal from a first voltage domain to a second voltage domain. The level shifter circuit includes two current paths between a supply terminal of the first voltage domain and a supply terminal of the second voltage domain. The first and second current paths each include a differential transistor that receives a signal from a pulse generator in a first voltage domain. The pulse generator provides pulses to the differential transistors based on an input signal to be translated to the second voltage domain. The level shifter includes a latch circuit in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths. Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage for biasing the bias transistor. The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 23, 2019
    Assignee: NXP B.V.
    Inventors: Kristof Blutman, Sebastien Antonius Josephus Fabrie, Juan Diego Echeverri Escobar, Ajay Kapoor, Jose de Jesus Pineda de Gyvez, Hamed Fatemi
  • Patent number: 10217861
    Abstract: An nchMOSFET of a level-raising circuit is arranged in a high voltage junction termination region (HVJT), to be integrated with a parasitic diode formed by an n?-type diffusion region and a second p-type separation region. On a high potential side of the HVJT, a first field plate (FP) also acting as a drain electrode of the nchMOSFET and a second FP also acting as a cathode electrode of a parasitic diode are arranged away from each other. On a low potential side the HVJT, a third electrode also acting as a source electrode of the nchMOSFET is arranged in a planar layout surrounding the periphery of a high potential side region. On an interlayer insulating film, an interval between a first portion of the third FP and a fourth portion of the first FP is larger than an interval between the second and the third FPs.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: February 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 10043424
    Abstract: It is an object to provide a specific driving method for reduction in power consumption in displaying a 3D image with field sequential driving.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 10037994
    Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tung Ying Lee, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang
  • Patent number: 10020060
    Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 10, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sungkwon Lee, Venkatraman Prabhakar
  • Patent number: 9997230
    Abstract: Embodiments of the invention relate to a reference voltage pre-processing circuit and method for a reference voltage buffer. The embodiments include a filter to control/reduce the noise and/or interference attached to a reference voltage to be provided to a reference voltage buffer by passing the reference voltage via two transistor in series. Furthermore, the embodiments include an auxiliary voltage circuit which interfaces the filter and the reference voltage buffer to avoid that the reference voltage buffer get an invalid reference voltage.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 12, 2018
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Min-Chung Chou
  • Patent number: 9972365
    Abstract: A non-volatile memory module includes a volatile memory circuit; an interface to a reference voltage source external to the module providing an external reference voltage to the volatile memory circuit by which the volatile memory circuit and external devices may communicate reliably at high speeds; an internal reference voltage generator; and a control circuit adapted to cause the volatile memory circuit to be decoupled from using the external reference voltage and coupled to using a reference voltage from the internal reference voltage generator upon the non-volatile memory module ceasing to draw power from an external power source.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: May 15, 2018
    Assignee: AGIGA TECH INC.
    Inventors: Yingnan Liu, Ying Cai
  • Patent number: 9972389
    Abstract: Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: May 15, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Masashi Fujita
  • Patent number: 9852259
    Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products that provide for area and/or power optimization through post-layout modification of design blocks. Specifically, a layout for an initial IC design is accessed. This initial IC design incorporates multiple instances of the same design block. Each instance includes a primary input connected to top-level logic for receiving a signal and one or more modifiable periphery sections. A timing analysis is performed to close timing and determine arrival times of the signal at the primary inputs of all instances of the design block, respectively, given the layout. The arrival times are then compared to a preselected threshold arrival time and the modifiable periphery section(s) of any specific instance of the design block having an arrival time that is equal to or less than the preselected threshold arrival time is selectively modified in order to generate an area and/or power optimized integrated circuit design.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeanne P. Bickford, Alok Chandra, Anand Kumaraswamy, Sandeep Prajapati, Venkatasreekanth Prudvi
  • Patent number: 9762245
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: September 12, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael Otto, Nigel Chan
  • Patent number: 9720434
    Abstract: An electronic device 2 has circuitry 4 which operates in a first voltage domain 6 supplied with a first voltage level VDD1 and a reference voltage level. A voltage regulator 14 generates the first voltage level VDD1 from a second voltage level VDD2 higher than the first voltage level VDD1. At least one power gate 20, 30 is provided for selectively coupling the circuitry 4 to one of the first voltage level VDD1 or the reference level. The control signal 22 for the power gate 20, 30 is generated in a second voltage domain supplied with a higher voltage level VDD2 or VDD3 derived from the second voltage level VDD2 supplied to the voltage regulator 14. Hence, an existing high voltage source within the device 2 can be reused for applying a boosted voltage to power gates to improve efficiency of power gating.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: August 1, 2017
    Assignee: ARM Limited
    Inventors: James Edward Myers, David Walter Flynn, David William Howard
  • Patent number: 9601139
    Abstract: A magneto-resistive (MR) sensor protection circuit is disclosed, for the protection of an MR sensor. The MR sensor may have a safe operating voltage range, a normal operating voltage range within the safe operating voltage range, and two terminals coupled to a read channel circuit, including a positive terminal and a negative terminal. The MR sensor protection circuit may have positive and negative protection threshold voltage ranges. The MR sensor protection circuit may also have a plurality of N-channel field-effect transistors (NFETs) that are coupled to the positive terminal and to the negative terminal, and configured to, in response to a voltage between the two terminals being within either the positive or the negative protection threshold voltage range, limit the voltage between the terminals by shunting current between the positive terminal and the negative terminal.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ephrem G. Gebreselasie, Icko E. T. Iben, Alain Loiseau, Andreas D. Stricker
  • Patent number: 9584121
    Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: February 28, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Qi Ye, Zhengyu Duan, Steven James Dillen, Animesh Datta
  • Patent number: 9501120
    Abstract: A power supply circuit includes first to third electronic switches, first to sixth resistors, and a first capacitor. The power supply circuit is coupled to a USB interface. A control terminal of the first electronic switch is utilized to receive a control signal. A first terminal of the first electronic switch is coupled to a standby power supply. The standby power supply is also coupled to ground through the first capacitor. The second electronic switch is coupled to the first electronic switch. The third electronic switch is coupled between the second electronic and the USB interface. The disclosure further provides an electronic device having the circuit.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: November 22, 2016
    Assignees: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Yong-Zhao Huang
  • Patent number: 9425381
    Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: August 23, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce G. Elmegreen, Glenn J. Martyna, Dennis M. Newns
  • Patent number: 9252283
    Abstract: A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is TS1 and the thickness of the second region is TG1, TS1?TG1.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 2, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Matsubayashi, Satoshi Shinohara, Wataru Sekine
  • Patent number: 9154135
    Abstract: Spare gate cells for inclusion in an integrated circuit have multiple inputs and outputs and are capable of selectively performing, concurrently, multiple logic functions on signals appearing at the inputs. Selection of required logic functions depends on the connections of at least one of the inputs of the spare cell. One of the outputs is fed back to an input of the spare gate cell to provide certain functionality while other outputs are set to a fixed logical value. The spare gate cell may be configured to perform NOR, OR and inverter operations on inputs simultaneously.
    Type: Grant
    Filed: April 27, 2014
    Date of Patent: October 6, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Reecha Jajodia, Gaurav Goyal
  • Patent number: 9111602
    Abstract: A system and method for accurately distributing a master reference voltage to a plurality of local circuits within a system. A central master reference voltage is distributed to a plurality of local circuits as a difference in the voltage of a pair of conductors oriented substantially spatially parallel. Local reference voltages are generated based on the master reference voltage and a local voltage source.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: August 18, 2015
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventor: Yossi Smeloy
  • Patent number: 9087818
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: July 21, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 9054070
    Abstract: An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: June 9, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Kaya, Yasushi Nakahara
  • Patent number: 9035679
    Abstract: Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: May 19, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Mahbub Rashed, Irene Yuh-Ling Lin, Jongwook Kye
  • Patent number: 9032236
    Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: May 12, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Ryo Hirano
  • Publication number: 20150015306
    Abstract: A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 15, 2015
    Inventors: Anis M. Jarrar, Mark D. Hall, David R. Tipple, Surya Veeraraghavan
  • Patent number: 8860465
    Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: October 14, 2014
    Assignee: Chaologix, Inc.
    Inventors: Brent Arnold Myers, James Gregory Fox
  • Publication number: 20140266304
    Abstract: A shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate without changing the potential of a gate is provided. In a shift register circuit including a logic circuit with a first transistor and a second transistor having the same conductivity type, a first gate electrode of the first transistor is connected to a source electrode or a drain electrode of the first transistor, an input signal is supplied to a second gate electrode of the first transistor, a clock signal is supplied to a gate electrode of the second transistor, and the first gate electrode and the gate electrode are formed from the same layer.
    Type: Application
    Filed: June 2, 2014
    Publication date: September 18, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Patent number: 8810280
    Abstract: Devices, systems, methods, and other embodiments associated with spare gates are described. In one embodiment, a spare gate in an integrated circuit has a disconnected discharge path to minimize or eliminate current leakage.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: August 19, 2014
    Assignee: Oracle International Corporation
    Inventors: Rambabu Pyapali, Yongjun Zhang, Yongning Sheng
  • Patent number: 8791516
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuaki Ohshima
  • Patent number: 8786313
    Abstract: It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: July 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Kawae
  • Publication number: 20140167819
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: February 21, 2014
    Publication date: June 19, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
  • Patent number: 8738940
    Abstract: A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: May 27, 2014
    Assignee: LSI Corporation
    Inventors: Ramnath Venkatraman, Shashidhara S. Bapat, Ruggero Castagnetti
  • Patent number: 8689031
    Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: April 1, 2014
    Inventor: Ryo Hirano
  • Patent number: 8683414
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 8681533
    Abstract: A signal processing circuit using a nonvolatile memory circuit with a novel structure is provided. The nonvolatile memory circuit is formed using a transistor including an oxide semiconductor and a capacitor connected to one of a source electrode and a drain electrode of the transistor. A high-level potential is written to the memory circuit in advance, and this state is kept in the case where data to be saved has a high-level potential, whereas a low-level potential is written to the memory circuit in the case where data to be saved has a low-level potential. Thus, a signal processing circuit with improved writing speed can be provided.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: March 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masashi Fujita
  • Patent number: 8638123
    Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: January 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Publication number: 20140002137
    Abstract: A switch comprising a spin-transistor and a first control wire. The spin-transistor is configured so that when a magnetic field applied to the spin-transistor is less than a threshold value, the transistor is in a conductive state in which electric current flows through the spin-transistor. When the magnetic field applied to the spin-transistor is greater than the threshold value, the spin-transistor is in a resistive state in which the electric current flowing through the spin-transistor is substantially reduced. The first control wire is for receiving a current to affect the magnetic field applied to the spin-transistor.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 2, 2014
    Inventors: Joseph S. Friedman, Gokhan Memik, Bruce W. Wessels
  • Patent number: 8587342
    Abstract: A novel logic circuit in which data is held even after power is turned off is provided. Further, a novel logic circuit whose power consumption can be reduced is provided. In the logic circuit, a comparator comparing two output nodes, a charge holding portion, and an output-node-potential determining portion are electrically connected to each other. Such a structure enables data to be held in the logic circuit even after power is turned off. Further, the total number of transistors in the logic circuit can be reduced. Furthermore, the area of the logic circuit can be reduced by stacking a transistor including an oxide semiconductor and a transistor including silicon.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: November 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuto Yakubo, Shuhei Nagatsuka
  • Publication number: 20130300456
    Abstract: Provided is a semiconductor chip for a programmable logic device which can hold configuration data even when supply of a power supply potential is interrupted and can operate with low power. Further, a semiconductor device using the semiconductor chip is provided. The semiconductor chip can hold configuration data even when supply of a power supply potential is interrupted and can operate with low power. The semiconductor chip includes a transistor and a pad connected to the transistor. The transistor is formed using a material which allows a sufficient reduction in off-state current of the transistor; for example, an oxide semiconductor material that is a wide bandgap semiconductor.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 14, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Erwan Lennon
  • Publication number: 20130293266
    Abstract: A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor.
    Type: Application
    Filed: April 25, 2013
    Publication date: November 7, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Publication number: 20130249597
    Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.
    Type: Application
    Filed: May 6, 2013
    Publication date: September 26, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironobu TAOKA, Yusaku ONO
  • Patent number: 8525552
    Abstract: A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: September 3, 2013
    Assignee: Panasonic Corporation
    Inventors: Takashi Ando, Keiichi Kusumoto, Kenji Shimazaki, Kazuyuki Nakanishi, Tetsurou Toubou