Significant Integrated Structure, Layout, Or Layout Interconnections Patents (Class 326/101)
  • Patent number: 10339245
    Abstract: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: July 2, 2019
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Patent number: 10311818
    Abstract: A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: June 4, 2019
    Assignee: Japan Display Inc.
    Inventors: Takayuki Suzuki, Hiroyuki Abe
  • Patent number: 10306779
    Abstract: A substrate support frame includes a body having an upper surface for supporting a first module substrate and a lower surface for supporting a second module substrate, and including a plurality of extending portions that define a cavity for receiving semiconductor devices mounted on first and second module substrates, a curved portion protruding outwardly from a first one of the extending portions of the body corresponding to a position of a flexible substrate that electrically connects the first and second module substrates to each other, the curved portion having a curved sectional shape protruding toward the flexible substrate, and a fastening hole penetrating through the first one of the extending portions of the body and configured to receive a screw to couple the body to at least one of the first and second module substrates.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu-Sung Kim, Ji-Yong Kim, Chung-Hyun Ryu
  • Patent number: 10305485
    Abstract: An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 28, 2019
    Assignee: NEC CORPORATION
    Inventors: Ayuka Tada, Noboru Sakimura, Makoto Miyamura, Yukihide Tsuji, Ryusuke Nebashi, Xu Bai, Toshitsugu Sakamoto
  • Patent number: 10296699
    Abstract: Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 21, 2019
    Assignee: XILINX, INC.
    Inventors: Hao Yu, Raymond Kong, Jun Liu
  • Patent number: 10283178
    Abstract: A semiconductor device which reduces power consumption. In the semiconductor device, semiconductor chips are stacked over a base chip. The stacked chips include n through-silicon vias as a first group and m through-silicon vias as a second group. In each of the first and second groups, the through-silicon vias are coupled by a shift circular method, in which the 1st to (n?1)th ((m?1)th) through-silicon vias of a lower chip are coupled with the 2nd to n-th (m-th) through-silicon vias of an upper chip respectively and the n-th (m-th) through-silicon via of the lower chip is coupled with the 1st through-silicon via of the upper chip. n and m have only one common divisor. Activation of the stacked semiconductor chips is controlled by combination of a first selection signal transmitted through through-silicon vias of the first group and a second selection signal transmitted through through-silicon vias of the second group.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 7, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroyuki Takahashi
  • Patent number: 10256274
    Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: April 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Kobayashi, Yoshihisa Iwata, Takeshi Sugimoto
  • Patent number: 10250262
    Abstract: An integrated circuit comprising a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality and (ii) includes a configurable switch interconnect network including a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including: (a) at least two of the stages which is configured in a hierarchical network, and (b) a mesh stage, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage and wherein the mesh stage of switch matrices of each logic tile is directly connected to the mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: April 2, 2019
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 10234891
    Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 19, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventors: Sho Kamezawa, Tohru Kanno
  • Patent number: 10211815
    Abstract: An integrated circuit includes a first portion of a stacked ring oscillator coupled between a first supply voltage node and a common node, wherein the first supply voltage node provides a local supply voltage for the first portion and the common node provides a local ground for the first portion. The integrated circuit includes a second portion of the stacked ring oscillator coupled between the common node and a second supply voltage node wherein the common node provides a local supply voltage for the second portion and the second supply voltage node provides a local ground for the second portion. The integrated circuit also includes a voltage divider having a first resistive element coupled between the first supply node and the common node and a second resistive element coupled between the common node and the second supply node.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Earl K. Hunter, Miguel Mendez, Yi Cheng Chang
  • Patent number: 10192859
    Abstract: Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: January 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas J. Aton, Roger Mark Terry, Robert L. Pitts
  • Patent number: 10133692
    Abstract: A system including: a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junho Huh, Horang Jang, Tomas Scherrer, Jaewon Lee
  • Patent number: 10121534
    Abstract: In one embodiment, an integrated circuit includes a pass gate circuit and a memory element circuit. The pass gate circuit receives a user signal that toggles between a high voltage level and a low voltage level. The memory element circuit outputs a control signal to control the pass gate circuit. The control signal may be asserted to be greater than the high voltage level when activating the pass gate circuit or the control signal may be deasserted to be less than the low voltage level when deactivating the pass gate circuit. In addition to that, a method on how to operate the pass gate circuit is also provided.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 6, 2018
    Assignee: Altera Corporation
    Inventor: Andy L. Lee
  • Patent number: 10114914
    Abstract: A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
  • Patent number: 10108188
    Abstract: A data processing device and an aerial vehicle are provided. The device comprises a sensor, a processor, and a clock converter. A data signal output pin of the sensor is connected with a data signal input pin of the processor. The sensor comprises at least two clock output pins, each of which is connected with one of two input pins of the clock convert. An output pin of the clock converter is connected with a clock input pin of the processor. The dock converter is configured to convert clock signals input from various input pins into a single-ended clock signal, and output the single-ended clock signal to the processor through the output pin.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 23, 2018
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Kang Yang, Guyue Zhou, Lei Yu, Xin Gao
  • Patent number: 10090840
    Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Andy L. Lee, Richard G. Smolen, Rusli Kurniawan, Jeffrey T. Watt, Christopher J. Pass, Yue-Song He
  • Patent number: 10068890
    Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: September 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hikaru Tamura, Naoaki Tsutsui, Atsuo Isobe
  • Patent number: 10044355
    Abstract: A reconfigurable circuit comprising: a first level crossbar switch that has first non-volatile resistive switches; a second level crossbar switch that has second non-volatile resistive switches; and a first wire and third non-volatile resistive switches that are used for redundancy, wherein input wires of the second level crossbar switch are connected to output wires of the first level crossbar switch one-to-one, and input wires of the first level crossbar switch and output wires of the second level crossbar switch are connected to the first wire through the third non-volatile resistive switches.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 7, 2018
    Assignee: NEC CORPORATION
    Inventors: Xu Bai, Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Ayuka Tada, Makoto Miyamura
  • Patent number: 9953121
    Abstract: A computer-implemented method includes identifying an in initial register-transfer-level description for an integrated circuit design and adding one or more spare latches to the initial register-transfer-level description to yield a modified register-transfer-level description for the integrated circuit design. The computer-implemented method further includes performing placement and routing for the modified register-transfer-level description to yield a gate-level description for the integrated circuit design. The one or more spare latches exist in said gate-level description. The computer-implemented method further includes converting at least one of the one or more spare latches in the gate-level description into a reconfigurable latch filler cell to yield a modified gate-level description for the integrated circuit design and finalizing the integrated circuit design. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
  • Patent number: 9904748
    Abstract: A layout effect characterization circuit includes a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: February 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
  • Patent number: 9906225
    Abstract: An integrated circuit comprising a field programmable gate array including a plurality of logic tiles physically organized in at least one row and at least one column and wherein each logic tile (i) is electrically coupled and physically adjacent to at least one other logic tile of the plurality of logic tiles and (ii) includes (a) logic circuitry, (b) memory, and (c) a configurable switch interconnect network which is electrically coupled to the memory, wherein the configurable switch interconnect network includes a plurality of switches electrically interconnected and organized into a plurality of switch matrices and wherein the plurality of switch matrices are arranged in a plurality of stages. In one embodiment, each logic tile of the plurality of logic tiles is capable of communicating, during operation, with at least one other logic tile of the plurality of logic tiles.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: February 27, 2018
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 9859358
    Abstract: An on-die-capacitor structure includes a first capacitor and a second capacitor. The first capacitor may have first and second terminals. The first and second terminals are directly connected to first and second power supply rail structures, respectively. The first power supply rail structure is different from the second power supply rail structure. The second capacitor may have third and fourth terminals. The second capacitor is connected in series between the second power supply rail structure and a third power supply rail structure. The third power supply rail structure is different from the first and second power supply rail structures. The third and fourth terminals are directly connected to the second and third power supply rail structures, respectively. The first capacitor may have a first capacitance and the second capacitor structure may have a second capacitance that is greater than the first capacitance.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: January 2, 2018
    Assignee: Altera Corporation
    Inventors: Kyung Suk Oh, Charu Sardana, Yanzhong Xu, Guang Chen
  • Patent number: 9792399
    Abstract: An integrated circuit hierarchical design tool apparatus comprises a processor arranged to support a block coupling reconfiguration unit. The block coupling reconfiguration unit is capable of receiving block layout data comprising block placement, terminal location data and intra-block connectivity data. The block coupling reconfiguration unit is arranged to identify from the block layout data a block placement level block having a terminal respectively coupled to a plurality of other block placement level blocks by a plurality of nets, and to provide the block with an additional terminal capable of providing the same function as the terminal. The block coupling reconfiguration unit is also arranged to replace a net of the plurality of nets that is coupled to the terminal with a replacement net coupled to the additional terminal.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: October 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Asher Berkovitz, Inbar Ben-Porat, Yossy Neeman
  • Patent number: 9769077
    Abstract: The present disclosure is directed to Quality of Service (QoS) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a Network on Chip (NoC) for an endpoint agent. The QoS policy and handshake protocols may involve the use of credits for buffer allocation which are sent to agents in the NoC to compel the acceptance of data and the allocation of an appropriate buffer. Messages sent to the agent may also have a priority associated with the message, wherein higher priority messages have automatic bandwidth allocation and lower priority messages are processed using a handshake protocol.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: September 19, 2017
    Assignee: NetSpeed Systems
    Inventor: Sailesh Kumar
  • Patent number: 9768775
    Abstract: A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 19, 2017
    Assignee: PLSense Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Patent number: 9760112
    Abstract: A semiconductor chip comprising: an internal clock circuit for generating an internal clock signal; a first phase shift device for shifting the phase of an external clock signal and outputting a phase shifting clock signal; a multiplexer, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad, for outputting the first clock signal; and a controllable pad. The controllable pad is controlled to selectively act as an input pad for receiving the external signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: September 12, 2017
    Assignee: MEDIATEK INC.
    Inventors: Ming-Luen Liou, Rong-Liang Chiou
  • Patent number: 9755506
    Abstract: An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Robert K. Montoye, Jae-sun Seo, Albert M. Young
  • Patent number: 9738987
    Abstract: An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lian Guo, Shu-Jen Han, Xuesong Li
  • Patent number: 9740813
    Abstract: An aspect includes forming a layout effect characterization circuit by incorporating a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain in an integrated circuit layout. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
  • Patent number: 9729148
    Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: August 8, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hikaru Tamura, Naoaki Tsutsui, Atsuo Isobe
  • Patent number: 9660626
    Abstract: An integrated circuit includes a clock tree network that distributes a clock signal to a plurality of clocked components of the integrated circuit. The clock tree network includes clock lines, each of which includes a clock tree delay element that provides a modified clock signal that is provided to an individual one the clocked components. Among the plurality of clocked components, one or more of the clocked components provides a data signal to another one or more of the clocked components. The one or more clocked components are configured having a transmission duration for the data signal that is longer relative to a transmission duration of the modified clock signal of the receiving clocked component.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 23, 2017
    Assignee: Medtronic, Inc.
    Inventors: Kevin K. Walsh, Melvin P. Roberts
  • Patent number: 9659129
    Abstract: An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 9582026
    Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: February 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youn-Sik Choi, Jin-Ook Song, Ho-Yeon Jeon, Jae-Gon Lee
  • Patent number: 9535127
    Abstract: An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: January 3, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9478609
    Abstract: An integrated circuit comprises a first cell having first cell height and a first line routed at a first line height and having a first line width. The integrated circuit also comprises a second cell having a second cell height different from the first cell height and a second line routed at a second line height and a second line width different from the first line width. The integrated circuit further comprises a third cell. The third cell has a third line having a first end and a second end. The first end has a first end width. The second end has a second end width. The first end width is equal to the first line width. The second end width is equal to the second line width. The first end is coupled with the first line. The second end is coupled with the second line.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: October 25, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Wei Chiang, Li-Chun Tien, Ming-Jin Huang, Pin-Dai Sue
  • Patent number: 9473415
    Abstract: The present disclosure is directed to Quality of Service (QoS) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a Network on Chip (NoC) for an endpoint agent. The QoS policy and handshake protocols may involve the use of credits for buffer allocation which are sent to agents in the NoC to compel the acceptance of data and the allocation of an appropriate buffer. Messages sent to the agent may also have a priority associated with the message, wherein higher priority messages have automatic bandwidth allocation and lower priority messages are processed using a handshake protocol.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: October 18, 2016
    Assignee: NETSPEED SYSTEMS
    Inventor: Sailesh Kumar
  • Patent number: 9467149
    Abstract: A distribution network for distributing clock and reset signals across an address macro has circuit blocks having dividers and counters, drivers connected in a balanced tree, and drivers connected in an unbalanced tree. The dividers and counters are synchronized relative to a clock signal. The drivers connected in the balanced tree distribute the clock signal synchronously to the circuit blocks. The drivers connected in the unbalanced tree distribute a reset signal to the circuit blocks. The clock signal is distributed via the balanced tree as a function of the reset signal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 11, 2016
    Assignee: SOCTRONICS, INC.
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao
  • Patent number: 9438218
    Abstract: Integrated circuits of large size produced by photorepetition of several mutually identical partial patterns are provided, more precisely to the compensation of propagation delays of signals (notably of clock signals) from one partial circuit to the following whereas the signals concerned must reach the various partial circuits simultaneously for proper operation of the whole. The compensation circuit provided in each partial circuit comprises a main transmission line for a master clock signal and a compensation line with multiple outputs, as well as a multiplexer for selecting one of the outputs, the output selected being different in the various partial circuits. The multiplexer provides a local clock signal in each partial circuit and these clock signals are synchronous despite the propagation delays.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: September 6, 2016
    Assignee: PYXALIS
    Inventor: Grégoire Chenebaux
  • Patent number: 9413566
    Abstract: A signal transmission circuit includes a transceiver, an impedance adjustment circuit, a first control circuit and a second control circuit. The impedance adjustment circuit realizes a low impedance state and a normal state of the transmission line. The first control circuit controls the impedance adjustment circuit to realize the low impedance state for a fixed period that is shorter than a width of one bit, when a change of a signal level on the transmission line is detected. The second control circuit controls the impedance adjustment circuit according to a transmission data transmitted from the transceiver, when detecting that a communication frame wins an arbitration by comparing the transmission data and the received data, to realize the low impedance state in an entire period where the signal level on the transmission line is recessive until transmission of the communication frame ends.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: August 9, 2016
    Assignees: DENSO CORPORATION, NIPPON SOKEN, INC.
    Inventors: Hiroyuki Mori, Keiji Shigeoka, Yoshifumi Kaku, Shogo Akasaki
  • Patent number: 9374092
    Abstract: An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 21, 2016
    Assignee: HYNIX SEMICONDUCTOR INC.
    Inventor: Bong Hwa Jeong
  • Patent number: 9270002
    Abstract: An interface for connecting a differential signal circuit having a differential signal output and a reference potential terminal to an input of a single ended signal circuit and a reference potential terminal. The interface includes a differential transmission line having a pair of electromagnetically coupled microwave transmission lines having first ends connected to the differential signal output and second ends, one of the second ends being connected to the single ended circuit input and the other one of the second ends being coupled to the reference potential terminals of the differential signal circuit and the single ended signal circuit.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: February 23, 2016
    Assignee: Raytheon Company
    Inventors: Valery S. Kaper, Anthony Kopa
  • Patent number: 9251860
    Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: February 2, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Aaron S. Yip, Mark A. Helm, Ramin Ghodsi
  • Patent number: 9202820
    Abstract: Improved 14 nm cells, as depicted in FIGS. 1-53, realize reduced pattern complexity, high yield, high performance, and improved compactness (one poly-stripe smaller than existing designs for the disclosed cells). The invention relates to ICs made using these cells (or topologically equivalent variants thereof), as well as processes for makings such ICs using said cells (or their variants).
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 1, 2015
    Assignee: PDF Solutions, Inc
    Inventor: Jonathan R. Haigh
  • Patent number: 9196316
    Abstract: A multi-die memory package may have separate chip enable inputs for the respective memory dice. Individual chip enable inputs may be separated by other chip connections such as power and ground. The memory dice may include multiple chip enable inputs to allow easy wire bonding of the individual chip enable inputs to a die without requiring any jumpers within the package. Circuitry may be included so that undriven chip enable inputs are masked and driven chip enable inputs may be propagated to the memory die to enable memory accesses while a single chip enable input is only connected to the capacitance of a single bonding pad.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: November 24, 2015
    Assignee: Intel Corporation
    Inventor: Daniel Chu
  • Patent number: 9142556
    Abstract: A dummy gate cell includes an nMOS transistor and a pMOS transistor, wherein a drain electrode of the nMOS transistor is not connected to a drain electrode of the pMOS transistor and the dummy gate cell is disposed in an unused area not occupied by a basic cell in a cell-based IC.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: September 22, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Yoshiharu Kito
  • Patent number: 9058459
    Abstract: An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a plurality of regions; determining a utilization for each of the regions; for each region, selecting from among a plurality of switch cell organizations for the region in response to the corresponding utilization; and for each region, modifying the layout to include switch cells for the region according to the selected switch cell organization.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: June 16, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Harish Dangat, Young Koog, Sarita Baswant, Prasanth Koduri
  • Patent number: 9024662
    Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: May 5, 2015
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Patent number: 9007095
    Abstract: An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 14, 2015
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8996906
    Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: March 31, 2015
    Assignee: Tabula, Inc.
    Inventors: Kent R. Townley, Christopher D. Ebeling, Hamish Fallside, Prasun K. Raha
  • Patent number: 8988109
    Abstract: High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 24, 2015
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young