Significant Integrated Structure, Layout, Or Layout Interconnections Patents (Class 326/101)
  • Patent number: 10811461
    Abstract: Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey
  • Patent number: 10804889
    Abstract: The disclosure relates to a skew control circuit for controlling the skew between at least three clock signals, the clock signals being forwarded to different clock domains associated with the respective clock signals. The skew control circuit comprises multiple programmable delay elements arranged within a signal flow before the respective clock domain, a skew detector arrangement operable for detecting skews between at least two pairs of the clock signals, and a control circuit operable for adjusting delays caused by the programmable delay elements. The control circuit is operable for carrying out a de-skewing operation. The de-skewing operation comprises determining an order of occurrence of edges of the signals, selecting one of the programmable delay elements based on the determined order, and adjusting the delay caused by the selected programmable delay element.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael V. Koch, Andreas H. A. Arp, Matthias Ringe, Fatih Cilek
  • Patent number: 10796728
    Abstract: Apparatuses for providing a clock signal for a plurality of circuits of a semiconductor device within delays in a certain range are described. An example apparatus includes a signal wire including a first portion and a second portion, having one ends coupled to each other at a signal input and the other ends coupled to each other that extend in parallel. The second portion has a higher impedance than the first portion from the first end to the second end. Output buffers closer to the signal input are coupled to the second portion and output buffers farther to the signal input are coupled to the first portion.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Takamitsu Onda
  • Patent number: 10784868
    Abstract: A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 22, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 10784184
    Abstract: A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soojung Rho, Chisung Oh, Kyomin Sohn, Yong-Ki Kim, Jong-Ho Moon, SeungHan Woo, Jaeyoun Youn
  • Patent number: 10769342
    Abstract: A method of generating an integrated circuit layout diagram includes arranging first cells having a first cell height in a first row and arranging second cells having a second cell height less than the first cell height in a second row abutting the first row. The first row and the second row extend along a first direction and are laid out relative to a routing grid including first routing tracks along the first direction and second routing tracks along a second direction perpendicular to the first direction. First cell pins are placed within each first cell extending along second routing tracks. Second cell pins are placed over selected via placement points in each second cell. At least one second cell pin extends along a corresponding second routing track across a boundary of a corresponding second cell and into a corresponding first cell abutting the corresponding second cell.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kam-Tou Sio, Jiann-Tyng Tzeng
  • Patent number: 10747933
    Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 18, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Chetan Bisht, Harry Scrivener, III
  • Patent number: 10739949
    Abstract: A port expansion device is connected to a user interface terminal in an aircraft. The user interface terminal displays a first selection page designed to make it possible to select a peripheral system from among a first set of peripheral systems connected to the user interface terminal, so as to transfer graphical interface control to the selected peripheral system. A second set of peripheral systems are connected to the user interface terminal via control circuitry of the port expansion device, which emulates peripheral system behaviour. The control circuitry exports a name representative of a menu navigation action on the user interface terminal, and emulates a second selection page in the style of the first selection page generated by the user interface terminal, making it possible to select a peripheral system from among the second set of peripheral systems. The port expansion is thus performed transparently.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 11, 2020
    Assignee: AIRBUS OPERATIONS (SAS)
    Inventor: Pau Lattore Costa
  • Patent number: 10727820
    Abstract: A clock detector includes a first detector circuit, a second detector circuit, and a toggle detector circuit. The first detector circuit is for activating a first detect signal in response to detecting that a clock signal that toggles between first and second logic states when present is stuck in the first logic state, and keeping the first detect signal inactive otherwise. The second detector circuit is for providing a second detect signal in response to detecting that the clock signal is stuck in the second logic state, and keeping the second detect signal inactive otherwise. The toggle detector circuit is for activating a toggle detect signal in response to both the first detect signal and the second detect signal being inactive, and keeping the toggle detect signal inactive in response to an activation of either the first detect signal or the second detect signal.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 28, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hariprasad Tt, Satish Sankaralingam, Dinakar Venkata Sarraju
  • Patent number: 10614231
    Abstract: A system and method for a enhancing security for a high security embedded system. The system on chip device including at least one central processing unit (CPU) component, input and output component blocks, an independent hard or soft core dedicated to the input and output blocks, and a built-in, on die interposer, wherein the interposer consists of a field programmable gate array (FPGA) fabric, the FPGA fabric surrounding the components of the system on chip. The method for includes separating system components using a FPGA fabric, redirecting or changing the appearance of system components unknown to other system components, separating system code from security and recovery code, and providing proactive security problem detection and resolutions.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 7, 2020
    Assignee: Riverside Research Institute
    Inventors: David Dozer, Adam Kouse
  • Patent number: 10615290
    Abstract: A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10608167
    Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Sasikanth Manipatruni, Anurag Chaudhry, Ian A. Young
  • Patent number: 10599594
    Abstract: The present invention relates to a method of processing data in a computer system, the method comprising the steps of: 1) allocating at least one processing node (100); 2) receiving data at a data source node (200, 400); 3) transferring the data to the or each processing node (100) through a serial data connection; 4) processing the data at the or each processing node (100); and 5) transferring the processed data from the or each processing node (100) to a data sink node (300, 400) through the serial data connection, wherein the at least one processing node (100), the data source node (200, 400) and the data sink (300, 400) each comprise no more than one Field Programmable Gate Array (101) or Application Specific Integrated Circuit.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 24, 2020
    Assignee: Nanotronix Inc.
    Inventors: Evangelos Angelakos, Konstantinos Masselos
  • Patent number: 10573598
    Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: February 25, 2020
    Assignee: XILINX, INC.
    Inventors: Austin H. Lesea, Sundararajarao Mohan, Stephen M. Trimberger
  • Patent number: 10566329
    Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Patent number: 10553171
    Abstract: A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit, along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: February 4, 2020
    Assignee: Japan Display Inc.
    Inventors: Takayuki Suzuki, Hiroyuki Abe
  • Patent number: 10541686
    Abstract: A circuit for routing data in an integrated circuit device is described. The circuit comprises an input/output port; an interface circuit coupled to the input/output port and configured to receive data, the interface circuit comprising a selection circuit enabling the selection of the data and a predetermined value; and a control circuit coupled to control the selection circuit; wherein the control circuit holds the input/output port at the predetermined value during a partial reconfiguration of the integrated circuit device in response to a control signal. A method of configuring a circuit for routing data in an integrated circuit device is also described.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 21, 2020
    Assignee: Xilinx, Inc.
    Inventors: David P. Schultz, David Robinson, Kusuma Bathala, Wenyi Song
  • Patent number: 10521267
    Abstract: A method of a priority trainer of a many core processing system comprising a plurality of cores is disclosed.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 31, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Patrik Åberg, Magnus Templing
  • Patent number: 10515171
    Abstract: According to one embodiment, a circuit description generation apparatus includes: a reduction candidate extraction unit that generates a waveform of an input signal based on a verification vector, and extracts a candidate for reducing the number of stages of shift registers, based on a minimum value of the number of cycles that last until a change in a value of a signal represented by the waveform; and a reduction circuit generation unit that generates circuit information describing a circuit in which the reduction has been made, and verifies whether or not there is equivalence in output between a circuit before the reduction and a circuit after the reduction.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: December 24, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Yuichiro Miyaoka
  • Patent number: 10339245
    Abstract: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: July 2, 2019
    Assignee: CALLAHAN CELLULAR L.L.C.
    Inventor: Raminda Udaya Madurawe
  • Patent number: 10311818
    Abstract: A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: June 4, 2019
    Assignee: Japan Display Inc.
    Inventors: Takayuki Suzuki, Hiroyuki Abe
  • Patent number: 10306779
    Abstract: A substrate support frame includes a body having an upper surface for supporting a first module substrate and a lower surface for supporting a second module substrate, and including a plurality of extending portions that define a cavity for receiving semiconductor devices mounted on first and second module substrates, a curved portion protruding outwardly from a first one of the extending portions of the body corresponding to a position of a flexible substrate that electrically connects the first and second module substrates to each other, the curved portion having a curved sectional shape protruding toward the flexible substrate, and a fastening hole penetrating through the first one of the extending portions of the body and configured to receive a screw to couple the body to at least one of the first and second module substrates.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu-Sung Kim, Ji-Yong Kim, Chung-Hyun Ryu
  • Patent number: 10305485
    Abstract: An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 28, 2019
    Assignee: NEC CORPORATION
    Inventors: Ayuka Tada, Noboru Sakimura, Makoto Miyamura, Yukihide Tsuji, Ryusuke Nebashi, Xu Bai, Toshitsugu Sakamoto
  • Patent number: 10296699
    Abstract: Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 21, 2019
    Assignee: XILINX, INC.
    Inventors: Hao Yu, Raymond Kong, Jun Liu
  • Patent number: 10283178
    Abstract: A semiconductor device which reduces power consumption. In the semiconductor device, semiconductor chips are stacked over a base chip. The stacked chips include n through-silicon vias as a first group and m through-silicon vias as a second group. In each of the first and second groups, the through-silicon vias are coupled by a shift circular method, in which the 1st to (n?1)th ((m?1)th) through-silicon vias of a lower chip are coupled with the 2nd to n-th (m-th) through-silicon vias of an upper chip respectively and the n-th (m-th) through-silicon via of the lower chip is coupled with the 1st through-silicon via of the upper chip. n and m have only one common divisor. Activation of the stacked semiconductor chips is controlled by combination of a first selection signal transmitted through through-silicon vias of the first group and a second selection signal transmitted through through-silicon vias of the second group.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 7, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroyuki Takahashi
  • Patent number: 10256274
    Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: April 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Kobayashi, Yoshihisa Iwata, Takeshi Sugimoto
  • Patent number: 10250262
    Abstract: An integrated circuit comprising a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality and (ii) includes a configurable switch interconnect network including a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including: (a) at least two of the stages which is configured in a hierarchical network, and (b) a mesh stage, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage and wherein the mesh stage of switch matrices of each logic tile is directly connected to the mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: April 2, 2019
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 10234891
    Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 19, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventors: Sho Kamezawa, Tohru Kanno
  • Patent number: 10211815
    Abstract: An integrated circuit includes a first portion of a stacked ring oscillator coupled between a first supply voltage node and a common node, wherein the first supply voltage node provides a local supply voltage for the first portion and the common node provides a local ground for the first portion. The integrated circuit includes a second portion of the stacked ring oscillator coupled between the common node and a second supply voltage node wherein the common node provides a local supply voltage for the second portion and the second supply voltage node provides a local ground for the second portion. The integrated circuit also includes a voltage divider having a first resistive element coupled between the first supply node and the common node and a second resistive element coupled between the common node and the second supply node.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Earl K. Hunter, Miguel Mendez, Yi Cheng Chang
  • Patent number: 10192859
    Abstract: Integrated circuit (5) includes substrate (10) with surface (20) and structure (30) including base levels (45.i, 45.(i+1)), terminating cells (48, 49), and block (40) of standard cells arranged in rows (42.i, 42.(i+1)), and another type of block (60) outside block (40). Standard cells at at least two edges of block (40) have the following protections: (1) block (60) has strip of separation (41.j) having at least a minimum width from the edges of block (40), and protected by one of the following: (2) terminating cells (48, 49) reduce context effect and some terminating cells (48) are placed at at least one end of rows (42.i, 42.(i+1)) of standard cells within first-named block (40), and (3) the terminating cells (48, 49) reduce context effect and some terminating cells (49) are at one end of a column of standard cells within block (40). Other structures, devices, and processes are also disclosed.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: January 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas J. Aton, Roger Mark Terry, Robert L. Pitts
  • Patent number: 10133692
    Abstract: A system including: a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junho Huh, Horang Jang, Tomas Scherrer, Jaewon Lee
  • Patent number: 10121534
    Abstract: In one embodiment, an integrated circuit includes a pass gate circuit and a memory element circuit. The pass gate circuit receives a user signal that toggles between a high voltage level and a low voltage level. The memory element circuit outputs a control signal to control the pass gate circuit. The control signal may be asserted to be greater than the high voltage level when activating the pass gate circuit or the control signal may be deasserted to be less than the low voltage level when deactivating the pass gate circuit. In addition to that, a method on how to operate the pass gate circuit is also provided.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 6, 2018
    Assignee: Altera Corporation
    Inventor: Andy L. Lee
  • Patent number: 10114914
    Abstract: A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
  • Patent number: 10108188
    Abstract: A data processing device and an aerial vehicle are provided. The device comprises a sensor, a processor, and a clock converter. A data signal output pin of the sensor is connected with a data signal input pin of the processor. The sensor comprises at least two clock output pins, each of which is connected with one of two input pins of the clock convert. An output pin of the clock converter is connected with a clock input pin of the processor. The dock converter is configured to convert clock signals input from various input pins into a single-ended clock signal, and output the single-ended clock signal to the processor through the output pin.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 23, 2018
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Kang Yang, Guyue Zhou, Lei Yu, Xin Gao
  • Patent number: 10090840
    Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Andy L. Lee, Richard G. Smolen, Rusli Kurniawan, Jeffrey T. Watt, Christopher J. Pass, Yue-Song He
  • Patent number: 10068890
    Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: September 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hikaru Tamura, Naoaki Tsutsui, Atsuo Isobe
  • Patent number: 10044355
    Abstract: A reconfigurable circuit comprising: a first level crossbar switch that has first non-volatile resistive switches; a second level crossbar switch that has second non-volatile resistive switches; and a first wire and third non-volatile resistive switches that are used for redundancy, wherein input wires of the second level crossbar switch are connected to output wires of the first level crossbar switch one-to-one, and input wires of the first level crossbar switch and output wires of the second level crossbar switch are connected to the first wire through the third non-volatile resistive switches.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 7, 2018
    Assignee: NEC CORPORATION
    Inventors: Xu Bai, Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Ayuka Tada, Makoto Miyamura
  • Patent number: 9953121
    Abstract: A computer-implemented method includes identifying an in initial register-transfer-level description for an integrated circuit design and adding one or more spare latches to the initial register-transfer-level description to yield a modified register-transfer-level description for the integrated circuit design. The computer-implemented method further includes performing placement and routing for the modified register-transfer-level description to yield a gate-level description for the integrated circuit design. The one or more spare latches exist in said gate-level description. The computer-implemented method further includes converting at least one of the one or more spare latches in the gate-level description into a reconfigurable latch filler cell to yield a modified gate-level description for the integrated circuit design and finalizing the integrated circuit design. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
  • Patent number: 9904748
    Abstract: A layout effect characterization circuit includes a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: February 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
  • Patent number: 9906225
    Abstract: An integrated circuit comprising a field programmable gate array including a plurality of logic tiles physically organized in at least one row and at least one column and wherein each logic tile (i) is electrically coupled and physically adjacent to at least one other logic tile of the plurality of logic tiles and (ii) includes (a) logic circuitry, (b) memory, and (c) a configurable switch interconnect network which is electrically coupled to the memory, wherein the configurable switch interconnect network includes a plurality of switches electrically interconnected and organized into a plurality of switch matrices and wherein the plurality of switch matrices are arranged in a plurality of stages. In one embodiment, each logic tile of the plurality of logic tiles is capable of communicating, during operation, with at least one other logic tile of the plurality of logic tiles.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: February 27, 2018
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 9859358
    Abstract: An on-die-capacitor structure includes a first capacitor and a second capacitor. The first capacitor may have first and second terminals. The first and second terminals are directly connected to first and second power supply rail structures, respectively. The first power supply rail structure is different from the second power supply rail structure. The second capacitor may have third and fourth terminals. The second capacitor is connected in series between the second power supply rail structure and a third power supply rail structure. The third power supply rail structure is different from the first and second power supply rail structures. The third and fourth terminals are directly connected to the second and third power supply rail structures, respectively. The first capacitor may have a first capacitance and the second capacitor structure may have a second capacitance that is greater than the first capacitance.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: January 2, 2018
    Assignee: Altera Corporation
    Inventors: Kyung Suk Oh, Charu Sardana, Yanzhong Xu, Guang Chen
  • Patent number: 9792399
    Abstract: An integrated circuit hierarchical design tool apparatus comprises a processor arranged to support a block coupling reconfiguration unit. The block coupling reconfiguration unit is capable of receiving block layout data comprising block placement, terminal location data and intra-block connectivity data. The block coupling reconfiguration unit is arranged to identify from the block layout data a block placement level block having a terminal respectively coupled to a plurality of other block placement level blocks by a plurality of nets, and to provide the block with an additional terminal capable of providing the same function as the terminal. The block coupling reconfiguration unit is also arranged to replace a net of the plurality of nets that is coupled to the terminal with a replacement net coupled to the additional terminal.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: October 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Asher Berkovitz, Inbar Ben-Porat, Yossy Neeman
  • Patent number: 9769077
    Abstract: The present disclosure is directed to Quality of Service (QoS) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a Network on Chip (NoC) for an endpoint agent. The QoS policy and handshake protocols may involve the use of credits for buffer allocation which are sent to agents in the NoC to compel the acceptance of data and the allocation of an appropriate buffer. Messages sent to the agent may also have a priority associated with the message, wherein higher priority messages have automatic bandwidth allocation and lower priority messages are processed using a handshake protocol.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: September 19, 2017
    Assignee: NetSpeed Systems
    Inventor: Sailesh Kumar
  • Patent number: 9768775
    Abstract: A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 19, 2017
    Assignee: PLSense Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Patent number: 9760112
    Abstract: A semiconductor chip comprising: an internal clock circuit for generating an internal clock signal; a first phase shift device for shifting the phase of an external clock signal and outputting a phase shifting clock signal; a multiplexer, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad, for outputting the first clock signal; and a controllable pad. The controllable pad is controlled to selectively act as an input pad for receiving the external signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: September 12, 2017
    Assignee: MEDIATEK INC.
    Inventors: Ming-Luen Liou, Rong-Liang Chiou
  • Patent number: 9755506
    Abstract: An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Robert K. Montoye, Jae-sun Seo, Albert M. Young
  • Patent number: 9738987
    Abstract: An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lian Guo, Shu-Jen Han, Xuesong Li
  • Patent number: 9740813
    Abstract: An aspect includes forming a layout effect characterization circuit by incorporating a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain in an integrated circuit layout. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Thomas Gentner, Jens Kuenzer, Antje Mueller, Thomas Strach, Otto A. Torreiter
  • Patent number: 9729148
    Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: August 8, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hikaru Tamura, Naoaki Tsutsui, Atsuo Isobe
  • Patent number: 9660626
    Abstract: An integrated circuit includes a clock tree network that distributes a clock signal to a plurality of clocked components of the integrated circuit. The clock tree network includes clock lines, each of which includes a clock tree delay element that provides a modified clock signal that is provided to an individual one the clocked components. Among the plurality of clocked components, one or more of the clocked components provides a data signal to another one or more of the clocked components. The one or more clocked components are configured having a transmission duration for the data signal that is longer relative to a transmission duration of the modified clock signal of the receiving clocked component.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 23, 2017
    Assignee: Medtronic, Inc.
    Inventors: Kevin K. Walsh, Melvin P. Roberts