Abstract: A self-clocked apparatus for eliminating race condition in high speed decoders is provided. In multi-stage decoders, a first stage is generally composed of predecoder blocks while a second stage is generally composed of decoder/driver blocks. Each predecoder block receives several address bits and outputs a high or low level signal depending on the address bit's state. Each decoder/driver block receives the output signal of the corresponding predecoder block, and outputs a signal selecting or not selecting a connected line. The self-clocked apparatus of the invention is cross-connected between adjacent predecoder blocks such that the ith decoder/driver block is controlled by the i+1th predecoder block, and conversely. No external clock signal is used, and no time margins are required. Furthermore, the invention provides a robust electrical design.

Abstract: A memory configuration (10) for outputting information in response to an address (A0-A7), the configuration including an array of memory cells (12) aligned in an array. The configuration further includes a plurality of predecoders (PD0, PD1, PD2), each operable to receive a corresponding portion of the address, and a plurality of decoder sets (DECODER SET 1-8), each having a plurality of wordline enable outputs (WL.sub.0 -WL.sub.255). Each of the plurality of predecoders comprises a plurality of predecoder precharge nodes (e.g., PN.sub.0 -PN.sub.3), a plurality of predecoder conditional series discharge paths (e.g., TA5.sub. 0, TA6.sub. 0, and DT) and a plurality of predecoder inverters (e.g., INV.sub.0 -INV.sub.3). Each of the plurality of decoder sets comprises a plurality of decoder precharge nodes (e.g., PN.sub.0 -PN.sub.31), a plurality of decoder conditional series discharge paths (e.g., TPD2.sub.0/0, TPD1.sub.0/0-7, and TPD0.sub.0/0-31), and a plurality of inverters (INV.sub.0 -INV.sub.31).

Abstract: Since the logic levels on both edge sides (node n1 and node n2) of an NMOS connected to a word line are set to the same level corresponding to the logic level of the chip enable signal, even in a memory having an MOS transistor with a short gate length due to an increase of the storage capacity, a leak voltage can be prevented from taking place in the chip standby state.

Abstract: A local column selection line driving circuit in a multi-bank memory device is shown which includes a first transistor coupled between a bank selection line and a circuit node and wherein a gate of the first transistor is coupled to a power supply voltage such that a non-inverting bank selection signal received on the bank selection line precharges the circuit node to a first voltage level. The local column selection line driving circuit also includes a second transistor coupled between a global column selection line and a local column selection line and having a gate terminal coupled to the circuit node such that a global column selection signal received on the global column selection line boosts the circuit node to a voltage level higher than the first voltage level. The circuit node then drives the global column selection signal onto the local column selection line through the second transistor.

Abstract: The drive circuit of the present invention includes a signal generation circuit which generates a drive signal at a specific timing. A first driver circuit drives one end of a first wire connected to a plurality of controlled circuits in response to the drive signal. A second driver circuit drives one end of a second wire having a smaller drive load than the first wire in response to the drive signal. A high speed driver circuit has its inputs connected to the other end of the second wire and to the other end of the first wire, and has an output terminal that drives the other end of the first wire when the voltage level at the other end of the second wire does not coincide with the voltage level at the other end of the first wire.

Abstract: First and second inverting stages and first and second decoding stages form in combination a decoder circuit, each of NAND gates of the first and second decoding stages and each of inverters of the first and second inverting stages are implemented by bi-MOS circuits, respectively, and the bi-MOS circuit for the NAND gate and the bi-MOS circuit for the inverter are a high-speed large-current consumption type and a low-speed small-current consumption type so that the decoder circuit achieves a high switching speed without sacrifice of power consumption.

Abstract: A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.

Abstract: In order to provide a detector with fewer switching elements for detecting simultaneous occurrence of more than one of logic `1` or logic `0` out of plural inputs, 4 inputs A, B, C and D for example, a detector of the invention detects more than one of logic `1` from NAND logic of outputs of 3 OR-NAND composit gates as follows. ##EQU1## Each OR-NAND composit gate is composed of 4 pMOS transistors for common use and 4 nMOS transistors and a NAND gate of 3 inputs is composed of 3 pMOS transistors and 3 nMOS transistors.Therefore, the detector of 4 inputs of the invention can be composed of 22 MOSFETs insted of 36 MOSFETs needed for a conventional detector of 6 NAND gates of 2 inputs and a NAND gate of 6 inputs.

Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.

Abstract: A combined row decoder and level translator powered by an on-chip high voltage supply results in an efficient layout, area savings and elimination of the global precharge signal resulting in additional area and power savings. In addition, power from the high voltage supply is consumed only by the level translator and wordline driver of the selected decoder resulting in additional power savings.

Abstract: In a logic circuit including a NAND type or a NOR type decoder, a p-MOS type transistor for precharge or an n-MOS type transistor for discharge is connected to a common node. The transistor allows precharge or discharge to be completed in a short period of time by promoting the charging or discharging of stray capacitances. Therefore, the circuit reduces the period of time necessary for the decoder to produce a high level output or a low level output.

Abstract: An address gating circuit for a memory array having redundant word lines. The address gating circuit includes a plurality of address lines comprising paired true and complement address lines for receiving address bits. The true and complement values of the address lines are ORed together then the results are ANDed together to generate an output. The output is used to inhibit selection of one of the address lines until a latest address bit is received.

Abstract: A multiplexer circuit (100) having N data inputs (151, 152, 156) is operable for outputting one of the received N data inputs (151, 152, 156) to its data output (150) in response to receipt of a plurality of control signals (144), which are produced by encoding (143) the selection signals (145) typically implemented for controlling such a multiplexer circuit (100).

Abstract: Method and apparatus for exploiting exclusivity of operation between a plurality of logic gates. The apparatus comprises a circuit having a plurality of logic gates. Each logic gate comprises a unique control input, and shares a data input with each of the plurality of logic gates. Control signals received at the control inputs insure exclusivity of operation between the logic gates. The shared data input is coupled to a shared fet which may serve as a virtual power supply for each of the plurality of logic gates.

Abstract: An improved decoder with a reduced architecture that decodes a plurality of input signals that include a least significant input signal. The decoder comprises at least one pair of adjacent logic gates, each of the at least one pair of logic gates receiving at least one logic input signal that is selected from a group of logic signals that include the input signals to the decoder and the inverse of the input signals to the decoder. The logic input signals received by the at least one pair of adjacent logic gates are common to both adjacent logic gates of the pair, except for those logic signals representing the least significant decoder input signal and the inverse of the least significant decoder signal.

Abstract: A 4.times.1 multiplexer for an electrically configurable device uses novel logic gates to logically combine outputs from two SRAM memory cells to control pass gates between the multiplexer signal inputs and a multiplexer output. Each logic gate has three transistors. A complementary NMOS/PMOS pair of transistors defines a transmission gate. The gate of the NMOS transistor defines a first logic-gate input, while the gate of the PMOS transistor defines a second logic-gate input. Their sources are coupled and cooperatively define a third logic-gate input. Their drains are coupled and cooperatively define the logic-gate output. A third transistor, with its gate tied to the third input, couples the logic-gate output to ground when the transmission gate is OFF. The first and second logic-gate inputs are respectively coupled to complementary outputs of one memory cell, while the third logic gate input is coupled to an output of the other memory cell.

Abstract: A circuit is designed with a decoder circuit (10), responsive to a first input signal (81) having a first voltage range, for producing a first output signal. An output circuit (11), responsive to the first output signal, produces a second output signal (26) having a second voltage range. The second voltage range includes a voltage less than a least voltage of the first voltage range and a voltage greater than a greatest voltage of the first voltage range.

Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.

Abstract: A combined row decoder and level translator powered by an on-chip high voltage supply results in an efficient layout, area savings and elimination of the global precharge signal resulting in additional area and power savings. In addition, power from the high voltage supply is consumed only by the level translator and wordline driver of the selected decoder resulting in additional power savings.

Abstract: A multiplexing arrangement. The multiplexing arrangement comprises a set of data inputs wherein a first multiplexer is coupled to a first subset of the set of data inputs and a second multiplexer is coupled to a second subset of the set of data inputs. Only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time. A logic gate is coupled to the first and second data outputs, and the logic gate synthesizes an output signal for the multiplexing arrangement in response to values output by the first and second multiplexers such that the multiplexing arrangement operates as a single multiplexer. According to one embodiment, the multiplexer that is not selected to pass data has its output biased to a known state.

Abstract: The present invention utilizes a CMOS (complementary metal-oxide-semiconductor) inverter, which includes a PMOS transistor and an NMOS transistor connected in cascade, and back-gate biasing circuits. The back-gate biasing circuit consists of capacitors and loads (active load or passive load). By providing a bias voltage to either one of bulks of the transistors or both of them, the constituted CMOS inverter demonstrates higher operation speed and lower standby current than the conventional one.

Abstract: A semiconductor integrated circuit having a decode circuit for selecting selected and non-selected wordlines and having a driver circuit for driving a potential to the non-selected wordlines which is less than the lowest potential to which any digit lines are driven during the operation of the semiconductor integrated circuit.

Abstract: A multiplexer. The multiplexer comprises a first data input and a second data input coupled to a logic gate via a first data path and a second data path, respectively, wherein a maximum of one of the first and second data paths is enabled to pass data at any given time. The data paths are independent of one another such that devices of the first data path do not load the second data path, and vice versa. The speed of a data path is determined by how many data input signals are routed through the same data path. In this manner, the speed of each data path may be tuned as required to provide the necessary operating speeds.

Abstract: It is an object to provide reduction of power consumption and/or speed-up of a semiconductor memory device. Different subdecode signals are supplied to respective blocks BL.sub.1 -BL.sub.m forming a memory cell array. The subdecode signals are generated in subdecode signal generating circuits SDB1.sub.1 -SDB1.sub.m provided corresponding to the respective blocks BL.sub.1 -BL.sub.m from addresses BS.sub.1 -BS.sub.m for block selection and addresses SDA.sub.1, SDA.sub.2 for subdecode signal provided respectively to the blocks. The subdecode signals are supplied only to subdecode circuits of one block specified by the address for block selection, and the number of subdecode circuits allotted to one subdecode signal generating circuit and the length of signal lines can be reduced.

Abstract: An address generator generates a binary coded address signal consisting of a combination of bit-representative low swing complementary signals. The coded address signal is decoded by an address decoder in a concurrently amplifying manner to obtain a decoded address signal consisting of a combination of symbol-representative full swing signal pairs of logical signals. The decoder comprises a binary tree of sense amplifiers each serving for outputting a logical product of an input enable signal and a corresponding low swing complementary signal, so that a single logical signal has a high level at the output end of the decoder. The high level logical signal is employed to drive a word line for an access to an arbitrary location defined in a given memory or to a desired piece of data stored therein, at an address represented by the decoded address signal.

Abstract: A circuit and method are provided for reducing the DC power consumption of clocked ratioed digital logic circuits. The circuit includes switching circuitry designed to analyze the voltage transitions of a ratioed digital logic circuit and based on such transitions, control the DC current flow through the entire circuit. Through the regulation of DC current flow through a digital logic circuit, the present invention reduces the detrimental effects of hot-electron effects and electromigration concerns which cause digital circuitry to fail. The circuit and method are illustrated by way of a ratioed logic NOR function employing MOSFET technology.

Abstract: A NOR decode circuit which includes a latch composed of a pair of n-channel transistors and a pair of p-channel transistors with the p-channel transistor of one latch portion coupled to a reference circuit transistor via a first pass transistor and the p-channel transistor of the other latch portion coupled to the address select line controlled transistors via a second pass transistor. The pass transistors are also controlled by an enable row (ENROW) signal. The address transistors are larger and conduct more current than the reference transistor. When ENROW is activated, the n-channel transistors of the latch are enabled and current passes through one side of the latch circuit and through a third transistor in parallel with the address transistors if any of the address transistors are turned on. Current also flows through the other side of the latch circuit and through a fourth transistor in parallel with the reference transistor. The second pass transistor conducts a current I.sub.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: The integrated circuit includes a plurality of row decoder-driver circuits, each for raising the voltage of a respective row line. Each of the plurality of row decoder-driver circuits includes an address decoder capable of receiving a plurality of address bits. The plurality of address bits, when decoded, identify one of the plurality of row decoder-drivers to provide an output. Each of the plurality of row decoder-drivers has an input transistor having a gate. The input transistor has a conduction path coupled between a power supply node and the address decoder. A signal generating circuit receives a signal to raise the voltage of a respective row line associated with the identified row decoder-driver circuit. The signal generating circuit provides an output that is coupled to the gate of the input transistor of each of the plurality of row decoder-driver circuits.

Abstract: The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are connected along the common signal line between the input pull down transistors and an output. A feedback element connects an output of the second inverter to an input of the first inverter. The inverters are configured to maintain the input of the first inverter at a first intermediate voltage level of V.sub.cc -2 Vt. Input signals received by the input transistors cause the voltage on the signal line to be pulled from the first intermediate level toward Vss. The first inverter responds by generating an output signal which swings from a low voltage of V.sub.ss towards a second intermediate level of V.sub.cc -0.7 Vt. The second inverter responds by generating an output signal which swings between the high level of V.sub.cc and a low level of V.sub.ss.

Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.

Abstract: An apparatus and method are described for minimizing the time required to perform verify operations in a semiconductor memory having a memory cell capable of being programmed, erased, and repaired, such as a flash EEPROM (electrically erasable programmable read only memory). The apparatus minimizes the time required to verify that the memory cell was correctly programmed, erased, and repaired. The apparatus includes a word a decoder, a driver, and a means for switching voltage levels supplied to the decorder and driver. The driver is comprised of a p-channel transistor having an n-well electrically coupled to a first power line, and a p-substrate. When the memory cell is to be accessed, the driver is activated and drives the word line with a voltage on a second power line. The the second power line is switched from a first voltage level to a second voltage level in order to initiate a verify process while the first power line is maintained at an approximately constant voltage.

Abstract: A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.

Abstract: A word-line driver of a semiconductor memory device having an address buffer for receiving a row address and a word-line decoder for converting an output signal of the address buffer into a word-line decoding signal is disclosed.

Abstract: A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.

Abstract: In a code setting circuit wherein pad terminals are supplied with a voltage pulse to burn out corresponding thin-film resistors, first transistors of first conductivity type are adapted to be turned on in response to a turn-on pulse and second transistors of the first conductivity type are provided. The channel of each second transistor is connected in parallel with the channel of each first transistor between a voltage source and one of circuit nodes at which desired potentials are developed and a digital setting signal is generated corresponding thereto. Inverters are connected between the nodes and the gate terminals of the second transistors to keep the nodes at the desired potentials. Third transistors of second conductivity type are provided to prevent the voltage source from being coupled through the second transistors to the pad terminals. Blocking means are provided respectively corresponding to the third transistors and the pad terminals.

Abstract: A logic circuit arrangement for performing synchronous dual word decoding utilizing a programmable logic array which is formed with a reduced number of transistor counts. This is achieved by organizing the AND plane (64) so as to decode only the seven (7) most significant bits of an 8-bit opcode word. A LSB decoder circuit (153) is used for decoding the least significant bit of the opcode word separately and outside of the AND plane. As a result, the amount I.C. chip space required has been substantially reduced.

Abstract: A dynamic decoder stores decoded signals in latch circuits for producing output signals, and the latch circuits are disabled after storing the decoded signals so that the output signals are free from undesirable level change of the decoded signals due to leakage between the dynamic decoding operations.

Abstract: A fast static logic gate contains a pullup logic network and a pulldown logic network configured to implement a logic function. The pullup logic network is coupled to receive gate inputs, and generates a first voltage level at a first node to represent a first state in accordance with the gate inputs and logic function. The first voltage level is less than the source voltage for the fast static logic gate circuit. A leaker circuit generates a second voltage level at the first node in response to a second state of the logic function. A driver circuit is coupled to a second node for generating an output. The pulldown logic network receives the gate inputs, and generates a second voltage level for the output to represent the second state in accordance to the gate inputs and logic function. The switch circuit couples the first node to the second node when the logic function generates the second state, and couples the source voltage to the second node when the logic function generates the first state.

Abstract: A high speed multiple input NOR gate. In an illustrative embodiment, the invention includes a plurality of pull-down transistors for providing an output signal. A pull-up transistor is coupled to the plurality of pull-down transistors for providing a drive current. A regulator is coupled to the pull-up transistor for regulating the drive current in response to temperature and power supply voltage variation so as to maintain the speed of the output signal during a low-to-high transition of the output signal. In specific implementations, the NOR gate is designed to regulate the output signal so that a high level or a low level thereof is maintained at a predetermined level.

Abstract: A digital logic circuit is provided which eliminates excessive power consumption while providing high speed transitions between logic states. The digital logic circuit includes a pull-down device coupled to an input line. The digital logic circuit further comprises a weak pull-up device and a strong pull-up device coupled to the pull-down device at a node. A means for providing a signal on an output line of the programmable logic device is coupled to the pull-down device and the pull-up devices. The weak pull-up device holds the node high if the pull-down device is in an off state. However, if the pull-down device is in an on state, the strong pull-up device is also turned on, thereby providing a stable intermediate voltage on the node. A feedback path from the output line controls the state of the strong pull-up device.