Abstract: The application provides a field programmable gate array (FPGA) and a communication method. At least one application specific integrated circuit based (ASIC-based) hard core is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.

Abstract: An OR logic operation circuit and a driving method, a shift register unit, a gate drive circuit, and a display device are provided. The OR logic operation circuit includes: a first inverter, a second inverter, a first control circuit, and a second control circuit. The first inverter is configured to invert a first control signal, which is received, to output a second control signal; the second inverter is configured to invert a third control signal received to output a fourth control signal; the first control circuit is configured to perform first control on a first node and the output terminal to achieve an OR operation and output a first level of an output signal at the output terminal; and the second control circuit is configured to perform second control on the first node and the output terminal to output a second level of the output signal at the output terminal.

Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

Abstract: Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via optical couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser.

Abstract: A system on chip (SoC) is connected to multiple off-chip devices, where the off-chip devices share IO pads of the SoC. A pin-mux circuit is used to facilitate the IO pad sharing. The pin-mux circuit can be addressed using just one control register and a decoder, which allows the IO pads to be easily and flexibly assigned. The decoder generates pin-mux control bits based on a configuration word stored in the control register. The pin-mux circuit assigns IO pads of the SoC to the off-chip devices. Device controllers of the SoC provide output bits to corresponding ones of the devices by way of the IO pads, and the devices provide input bits to the device controllers via the IO pads. Chip area is saved by using a register-decoder scheme, and set-up requires writing just the one control register.

Abstract: In an example, a programmable integrated circuit (IC) includes external contacts configured to interface with a substrate and a plurality of configurable logic elements (CLEs) distributed across a programmable fabric. The programmable IC further includes interconnect circuits disposed between the plurality of CLEs and the external contacts. A plurality of the interconnect circuits is disposed in the plurality of CLEs.

Abstract: A security chip including a fusible logic array. An input is configured to receive, from a verification module external to the security chip, a seed value corresponding to one of a predetermined value and a generated value. The fusible logic array is configured to generate a logic result using the received seed value. The fusible logic array includes a logic gate configured to operate, based on a state of a fusible link within the logic gate, as both a first type of logic gate configured to perform a first logic operation and a second type of logic gate configured to perform a second logic operation different from the first logic operation. The fusible logic array is configured to generate the logic result based on the state of the fusible link. An output is configured to provide a key value, representative of the logic result, to the verification module.

Abstract: A circuit has a stacked structure having at least one symmetric FET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.

Abstract: Disclosed herein is a logic circuit that includes a transistor T1 coupled between VPERI and a node n1, a transistor T2 coupled between VPERI and a node n2, a transistor T3 coupled between VSS and a node n3, a transistor T4 coupled between VSS and a node n4, transistors T5 and T7 coupled in series between the nodes n1 and n3, transistors T9 and T11 coupled in series between the nodes n1 and n3, transistors T6 and T8 coupled in series between the nodes n2 and n4, and transistors T10 and T12 coupled in series between the nodes n2 and n4. An output signal Y is output from a connection point of the transistors T5 and T7 and a connection point of the transistors T6 and T8.

Abstract: A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side, and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small.

Abstract: A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.

Abstract: The circuit includes an E-mode transistor with gate-source junction, a D-mode transistor with gate-source junction, a component generating a voltage drop between the source of the D-mode transistor and the drain of the E-mode transistor, and a connection between the drain of the E-mode transistor and the gate of the D-mode transistor. The gate of the E-mode transistor is provided for an input signal, and the drain of the E-mode transistor is provided for an output signal.

Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Abstract: A wire-OR matching circuit with low power consumption can be enabled by inputting an input-enabling signal representing “enabled.” The wire-OR matching circuit generates an output-enabling signal according to a control signal and a periodic pulse signal. When the periodic pulse signal represents “turn on”, if the input-enabling signal represents “enabled” and the control signal represents “not disabled”, the output-enabling signal represents “enabled;” if the input-enabling signal represents “enabled” and the control signal represents “disabled”, the output-enabling signal represents “not enabled.” The wire- or matching circuit can promptly break the connection between the high voltage source and the low voltage source by controlling the pulse width of the periodic pulse signal. In this way, large current is avoided, saving power consumption.

Abstract: An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

Abstract: An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.

Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Abstract: A wire-OR matching circuit with low power consumption can be enabled by inputting an input-enabling signal representing “enabled.” The wire-OR matching circuit generates an output-enabling signal according to a control signal and a periodic pulse signal. When the periodic pulse signal represents “turn on”, if the input-enabling signal represents “enabled” and the control signal represents “not disabled”, the output-enabling signal represents “enabled;” if the input-enabling signal represents “enabled” and the control signal represents “disabled”, the output-enabling signal represents “not enabled.” The wire- or matching circuit can promptly break the connection between the high voltage source and the low voltage source by controlling the pulse width of the periodic pulse signal. In this way, large current is avoided, saving power consumption.

Abstract: The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision.

Abstract: A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.

Abstract: Reconfigurable logic cells based on dual gate MOSFET transistors (DG MOSFETs) including n inputs (A,B), n being greater than or equal to 2 and capable of performing at least four logic functions with which logical signals provided on the n inputs (A,B) may be processed. The cell contains, between the ground and the output (F) of the cell, at least one first branch including n dual gate N-type MOSFET transistors (M1,M2) in series and n?1 branches in parallel with the first branch, each provided with a dual gate N-type MOSFET transistor (M3), each of the logic functions corresponding to a given configuration of the cell. A specific set of control signals (C1,C2) is applied on the rear gates of at least one portion of the transistors (M2,M3), each control signal (C1,C2) being capable of setting the transistor (M2,M3) to a particular operating mode.

Abstract: A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.

Abstract: The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision.

Abstract: A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.

Abstract: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H level. In this case, when none of a plurality of pieces of data is selected using a selection signal, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor of the second dynamic circuit is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.

Abstract: Disclosed is a logic circuit including first and second input terminals, supplied with respective logic signals, and first and second MOS transistors, having sources respectively connected to associated ones of the first and second input terminals and gates cross-connected to the second and first input terminals. The drains of the first and second MOS transistors are connected in common. The logic circuit also includes a MOS transistor, connected between a first power supply and a common node of the drains of the first and second MOS transistors and having a gate supplied with a reset signal so that the MOS transistor is turned on at the time of resetting. The logic circuit further includes an inverter having an input end connected to the common node.

Abstract: An inverter circuit (500) having a drive transistor (102) that operably couples to a voltage bias input (101) (and where that drive transistor controls the inverter circuit output by opening and closing a connection between the output (105) and ground (104)) is further operably coupled to a feedback switch (401). In a preferred approach the feedback switch is itself also operably coupled to the voltage bias input and the output and preferably serves, when the drive transistor is switched “off,” to responsively couple the voltage bias input to the drive transistor in such a way as to cause a gate terminal of the drive transistor to have its polarity relative to a source terminal of the drive transistor reversed and hence permit the inverter circuit to operate across a substantially full potential operating range of the drive transistor.

Abstract: The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision.

Abstract: A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input nodes and the intermediate nodes, and the conduction states of the transistors being controlled by second complementary input signals to output a logical operation result of the first and second input signals to the intermediate nodes; and inverters for inverting the intermediate signals and producing complementary output signals, wherein the NMOS transistors of the logic network are configured as a depletion-type NMOS.

Abstract: A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle.

Abstract: A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, having four data signal inputs, to which two data signals and the logically complementary data signals thereof can be applied, and having six logic selection elements between the data signal inputs. At a data signal output, the logic combination of the two data signals in accordance with the logic function selected by means of the logic selection elements can be provided as output signal.

Abstract: A semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in the conductive state or the nonconductive state, and a plurality of circuit selection switching elements, wherein said circuit selection switching elements are driven in response to the circuit configuration instruction signal, and control signals are output from the circuit selection switching elements. The connection elements may be magnetoresistance effect elements or resistance control elements which become the conductive state or the nonconductive state in accordance with application of a magnetic field. The circuit elements may also be magnetoresistance effect elements or resistance control elements.

Abstract: A logic family consisting of four basic logical circuits performing AND, OR, NAND and NOR functions is disclosed. The AND and OR logic circuits function without a power supply and complementary input signals. The NAND and NOR logic circuits function without complementary input signals. The AND and OR logic circuits are constructed using two MOS (Metal Oxide Semiconductor) transistors, namely, one P-channel MOS transistor and one N-channel MOS transistor. The NAND and NOR logic circuits are constructed using four MOS transistors, namely, two P-channel MOS transistors and two N-channel MOS transistors. The logic circuits may have higher speed, occupy less area and consume less power because power supply is not needed, complementary input signals are not used and fewer transistors are used. The logic circuits may have increased performance relative to CMOS (Complementary MOS) logic circuits, CPL (Complementary Pass Logic) circuits and DPL (Dual Pass Logic) circuits.

Abstract: An architecture for computing includes nanometer scale crossbar switches configured to perform a logical function in response to a sequence of pulses that encode logic values in the nanometer scale crossbar switches as impedances.

Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: A ratioed logic gate includes a contention interrupt circuit. The ratioed logic gate includes a pull up network coupled to a pull down network. Multiple inputs are coupled to turn the pull down and pull up networks on and off. An output is coupled to apply a logical function on the multiple inputs. A contention interrupt circuit is coupled to one of the pull up and the pull down networks to open circuit the one of the pull up and pull down networks when the pull up and pull down networks are in contention.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output.

Abstract: Methods, and arrangements to enhance speed and reduce power consumption in a scanable latch circuit are disclosed. Embodiments include a wired-or circuit to facilitate independent paths for scan data and normal input data through the scanable latch circuit. In particular, to reduce delays related to gates between the input pin for the system clock and a normal input gate, dual, substantially independent paths are implemented: a scan path and a normal input path. Embodiments coordinate transmission of data from a normal input gate and a scan input gate to an output latch, a scan out pin, and/or combinational logic by incorporating buffers that isolate a wired-or node from either the scan input gate, the normal input gate, or both with a high impedance.

Abstract: A time-multiplexed data bus driver circuit includes a plurality of combinatorial circuits, each of the circuits forming a logic combination of a datum value, a datum enable signal and a datum timeslot signal, the plurality of circuits producing a plurality of output signals based thereon, and a wired-OR junction producing a logic OR combination of the plurality of output signals representing a time-multiplexed data stream. Preferably, for each of the combinatorial circuits the enable signal, the timeslot signal and the datum signal (and preferably also a clock signal) are combined in an AND function to produce a gating signal for an active-low datum value, one selected active-low datum value being gated onto the wired-OR junction at a given timeslot when enabled. The common time-multiplexed data channel at the wired-OR junction has a pre-charge circuit for biasing the junction to a positive or ground voltage, thereby representing in an un-driven state a respective logic 1 or 0.

Abstract: The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated.

Abstract: To produce a logic circuit with excellent characteristics including area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function. Respective nodes are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. A pass transistor selector operating as a NAND or NOR logic with any one of its two inputs, excluding the control input, being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value.

Abstract: Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.

Abstract: A pass transistor circuit comprises a plurality of pass transistors connected in parallel. The same input signal is inputted into the sources of these pass transistors. Continuities of these pass transistors are controlled by a plurality of control signals having an exclusive relationship therebetween. A plurality of buffers respectively drive the drive segments including at least the pass transistors and wirings. The drive segments being a plurality of divided ranges each having an equal potential.

Abstract: A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal line, and a sensing device coupled to the reference signal line and the wired OR signal line to receive the wired OR signal and the reference signal respectively and to detect a difference between the two signals. Having a differential pair of lines is advantageous because it maintains noise immunity for small voltage swings on the wired OR signal line, thereby reducing power dissipation in the wired OR circuit. A common current source coupled to each logic block through a common return path allows the low power wired OR circuit to control a discharge rate at which the wired OR line discharges.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A ratioed NOR gate arrangement for low-voltage-swing logic circuit arrangements, the ratioed NOR gate arrangement including at least two input terminals, an output terminal, and two inverter arrangements, in which each of the two inverter arrangements is coupled to the output terminal and to a corresponding one of the at least two input terminals, and each of the two inverter arrangements includes a first switching device coupled in series with a second switching device, a size of the first switching device being different than another size of the second switching device so that a ratio of the size and the another size is different than one.

Abstract: In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

Abstract: An OR circuit allowing one stable output voltage from a plurality of input voltages is disclosed. A first FET is connected between a corresponding input terminal and an output terminal in such a manner that an inherent diode of the FET is connected in a forward direction. A second FET is connected between a corresponding input terminal and the output terminal in the same manner as the first FET. Each of the input voltages is compared with the output voltage. The conduction/non-conduction states of each of the first and second FETs are independently controlled depending on the comparison result.

Abstract: For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output.