Abstract: In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-inut, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass tansistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

Abstract: A system and method of reducing wire-or glitch to improve bus speeds. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver is controlled. The off-going wave is forced to climb gradually such that one propagation delay of the loaded bus later, it is only marginally above a high threshold voltage. The fall time of the wave created by an on-going driver is minimized such that a strong negative going voltage propagates down the bus. This strong negative going voltage drags a composite wave on the bus (i.e. the combination of the waves of the on-going driver and the off-going driver) back below a low threshold voltage approximately one propagation delay after the switching occurs.

Abstract: A system of logic modules providing AND, OR and NOT logical elements most useful in education and entertainment situations where it is important to avoid excessive costs and where speed is not a requirement utilizes electrical continuity and a lack of electrical continuity between pairs of electrical conductors to represent predetermined values of logical variables.

Abstract: A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gate of the transistor T1 is connected to a direct signal input IN whereas the gate of the transistor T2 receives a shifted version of the direct input signal from a source-follower comprising the transistors T3 and T4. The level shifter may also be embodied as a differential cross-coupled sense amplifier with the sources of the drain load transistors being crossed coupled to the differential inputs.

Abstract: For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

Abstract: An apparatus for dynamic termination logic of bi-directional data buses and methods of operating the same result in bi-directional data buses with improved data transfer performance. The bi-directional data bus for wire-or data transfers comprises a first end-driver coupled to a first end of the data bus configured to drive the first end of the data bus with a first signal. The second end-driver coupled to the second end of the data bus is configured to dynamically terminate the first signal from the first end-driver.

Abstract: A wired combinational logic arrangement responsive to N binary signal sources includes N circuits, one for each source. The circuits drive a common output terminal. Each circuit includes first and second devices for pulling the common terminal to first and second different voltages during successive abutting activation periods. The first device supplies a current to the common terminal that is considerably greater than the current supplied to the common terminal by the second device. The arrangement further includes a third device for pulling the common terminal to the second voltage at all times. The third device supplies a current to the common terminal that is either equal to or less than the current supplied by the second device.

Abstract: A gate array architecture adapted for serial multiplexer-based circuits. In one embodiment, the gate array contains base cells having functional but isolated serial multiplexer circuits therein. In another embodiment, a base cell contains a single serial multiplexer circuit divisible into varying-sized (size corresponding to the number of inputs) derivative serial multiplexer circuits. In either embodiment, the serial multiplexer circuits within the base cell may be formed from P- and N-channel transistors of varying size. The transistor sizes are chosen to optimize the efficiency of serial multiplexer-based circuits.

Abstract: A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and not-invert functions. Each circuit is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.

Abstract: A method and apparatus for increasing the speed of a cascaded Content Addressable Memory (CAM) system by pre-charging the system match line of the CAM system are disclosed. The CAM system has (i) a plurality of CAM chips, (ii) a separate match output circuit for each CAM chip, (iii) a separate precharge circuit and pull-down circuit for each match output circuit and (iv) a system match line coupled to all of the match output circuits. Each of the precharge and pull-down circuits has an N-channel MOSFET. To increase the speed of the CAM system, the CAM system precharges the system match line so that the recovery time required for the system match line to change from a logic low to a logic high is minimized. Because each match output circuit has a precharge circuit, adding more CAM chips to the CAM system does not degrade the speed of the CAM system.

Abstract: A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and not-invert functions. Each circuit is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.

Abstract: An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and a p-channel driver transistor (16, 20) which are connected to a signal (I/O) when no wired outputs (y) are desired. If two or more outputs (y) are to be connected to enable a wired logic function, p-channel transistor (16) is disabled. Then, a weak pull-up transistor (18) may be provided. Alternatively, a senseamp may be provided to the connected outputs (y).

Abstract: A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver invertor having an input and an output. The invertor inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.

Abstract: A boating shoe, comprises an upper unit, a midsole and a high traction outsole attached to the bottom of said midsole. The upper unit includes a padded tongue made of a substantially nonabsorbent material and an inner lining having at least two plies. The outer ply adjacent the wearer's foot is made of a hydrophobic material and the inner ply is made of a hydrophilic material with good wicking characteristics. A bottom sock made of a fabric material through which water can flow freely is sewn to the bottom of the upper unit. The midsole is molded from a plastic material and includes forward and rear drainage cavities, each having a plurality of upstanding projections for supporting the wearer's foot. Drainage channels extend from each of the cavities through the midsole to its outer surface so that water flowing into the cavities of the midsole will be drained from the shoe.