Source-coupled Logic (e.g., Current Mode Logic (cml), Differential Current Switch Logic (dcsl), Etc.) Patents (Class 326/115)
  • Patent number: 10224885
    Abstract: In accordance with an embodiment, a method includes receiving a first differential logic signal using a first branch of a circuit that extends from a voltage supply of the circuit as far as an earth terminal of the circuit and has at least one first differential transistor pair, receiving a second differential logic signal using a second branch of the circuit that extends from the voltage supply to the earth terminal and has at least one second differential transistor pair, conducting a current flow between the first branch and the second branch, and outputting an output signal by the second branch.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: March 5, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Johann Peter Forstner, Vadim Issakov, Saverio Trotta
  • Patent number: 10153771
    Abstract: A negative-level shifting circuit includes a first level shifter including an input circuit configured to receive a logic signal having a first voltage level and a load circuit configured to generate a first output signal having a second voltage level based on a voltage generated by the input circuit, and a second level shifter configured to receive the first output signal from the first level shifter and generate a second output signal having a third voltage level. The first level shifter further includes a shielding circuit connected between the input circuit and the load circuit and configured to separate an operating voltage region of the input circuit from an operating voltage region of the load circuit such that the input circuit operates in a positive voltage region and the load circuit operates in a negative voltage region.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Young Ryu, Yong-Hoan Kim, Eun-Jeong Park
  • Patent number: 10135442
    Abstract: A current-mode logic circuit is provided. The current-mode logic circuit includes a transmitter module. The transmitter module includes an output impedance circuit, a switch circuit, and a current source. The output impedance circuit provides an adjustable output resistor. The adjustable output resistor includes floating resistors and/or pull-up resistors. The switch circuit is coupled to the output impedance circuit. The switch circuit receives differential input signals, outputs differential output signals, and controls high-low level switching of the differential input signals and the differential output signals according to the adjustable output resistor. The current source is coupled to the output impedance circuit and the switch circuit. The current source provides currents to the output impedance circuit and the switch circuit.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: November 20, 2018
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Yiming Tang, Bo Hu, Kun Lan
  • Patent number: 10122348
    Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 6, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
  • Patent number: 10033412
    Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 24, 2018
    Assignee: XILINX, INC.
    Inventors: Siok Wei Lim, Kok Lim Chan, Kee Hian Tan, Hongyuan Zhao, Chin Yang Koay, Yohan Frans, Kun-Yung Chang
  • Patent number: 10032487
    Abstract: An apparatus including a Correlated Electron Switch (CES) element and a programing circuit is provided. The programing circuit provides a programing signal to the CES element to program the CES element to an impedance state of multiple impedance states when a number of times the CES element has been programed is less than a threshold.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 24, 2018
    Assignee: ARM Ltd.
    Inventors: Lucian Shifren, Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu
  • Patent number: 9985631
    Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 29, 2018
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Scott E. Thompson, Lawrence T. Clark
  • Patent number: 9948293
    Abstract: An integrated circuit includes first and second transmitter driver circuits. The first transmitter driver circuit includes a first pull-up circuit and a first pull-down circuit that are configured as a first voltage mode driver to drive a first single-ended output signal to a first pad during a voltage mode operation. The second transmitter driver circuit includes a second pull-up circuit and a second pull-down circuit that are configured as a second voltage mode driver to drive a second single-ended output signal to a second pad during the voltage mode operation. The first and second pull-up circuits and the first and second pull-down circuits drive a differential output signal to the first and second pads during a current mode operation when the first and second transmitter driver circuits are configured as a current mode driver.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventor: Ker Yon Lau
  • Patent number: 9853842
    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: December 26, 2017
    Assignee: INPHI CORPORATION
    Inventors: Parmanand Mishra, Steffen Nielsen, Michael S. Harwood
  • Patent number: 9645604
    Abstract: Circuits and techniques for mesochronous processing are provided. A communication method for a mesochronously clocked system may include synchronizing processing of first and second processing units to first and second mesochronous clock signals, respectively. The first and second mesochronous clock signals may have a same frequency and different phases, respectively. The method may further include sending data from the first processing unit to the second processing unit, and enabling or disabling receipt of the data by the second processing unit based, at least in part, on states of the first and second mesochronous clock signals.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 9, 2017
    Assignees: Bitfury Group Limited
    Inventor: Valerii Nebesnyi
  • Patent number: 9595975
    Abstract: A low-latency, high-gain (LLHG) slicer includes an input stage coupled to a differential output port and configured to receive a differential analog input signal, and to track the differential analog input signal during a tracking phase, an output stage coupled to the differential output port and configured to generate digital output bits corresponding to the differential analog input signal during a regeneration phase, and a tunable resistor coupled to the differential output port and configured to provide a first load impedance during the tracking phase and to provide a second load impedance during the regeneration phase, the first load impedance being lower than the second load impedance.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: March 14, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sanquan Song, Amir Amirkhany
  • Patent number: 9564896
    Abstract: A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a control signal. The control module is configured to generate the control signal and to determine a voltage level or a pulse width of the control signal in accordance with a current process corner condition of the voltage control circuits and at least one of first predetermined data and second predetermined data.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui Kao, Chien-Ju Chao, Chin-Shen Lin, Nitesh Katta, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 9537685
    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 3, 2017
    Assignee: INPHI CORPORATION
    Inventors: Parmanand Mishra, Steffen Nielsen, Michael S. Harwood
  • Patent number: 9520196
    Abstract: A voltage switch circuit is connected to a memory cell of a non-volatile memory. When the non-volatile memory is in a program mode and the memory cell is a selected memory cell, two output terminals provide a high voltage. When the non-volatile memory is in the program mode and the memory cell is a non-selected memory cell, the two output terminals provide a medium voltage and a ground voltage. When the non-volatile memory is in an erase mode and the memory cell is the selected memory cell, the two output terminals provide the high voltage and the ground voltage. When the non-volatile memory is in the erase mode and the memory cell is the non-selected memory cell, the two output terminals provide the ground voltage. When the non-volatile memory is in a read mode, the two output terminals provide a read voltage.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 13, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chen-Hao Po
  • Patent number: 9520872
    Abstract: A linear equalizer is configured with load transistors that load a corresponding differential pair of transistors. The linear equalizer is configured to selectively diode connect each load transistor to boost a high frequency gain.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Bupesh Pandita
  • Patent number: 9520708
    Abstract: A protection circuit includes a control circuit coupled to a first power-supply wire applied with a first power-supply voltage. The control circuit generates a control voltage in accordance with the first power-supply voltage and an input voltage. A voltage limitation circuit is coupled between a first node applied with the input voltage and a second power-supply wire applied with a second power-supply voltage. The voltage limitation circuit includes a variable resistance unit having a resistance value that changes according to the control voltage. When the first power-supply voltage is not supplied to the protection circuit and the input voltage is larger than a first voltage, the control circuit generates the control voltage such that the resistance value of the variable resistance unit is smaller than that in a case where the input voltage is equal to or less than the first voltage.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: December 13, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Tunehiko Moriuchi
  • Patent number: 9350335
    Abstract: A combined multiplexer and latch circuit is provided that has only a single gate delay between the input of the overall circuit and the output of the circuit. Two complementary input signal stages each receive a complementary input signal and a multiplexer input. A clocked preset circuit presets a signal at the output of the combined multiplexer and latch circuit with timing based on a first phase of an input clock. A storage circuit stores a value based on the output of the combined multiplexer and latch circuit with timing based on a second phase of the input clock. The circuit has a preset mode during which the output of the combined multiplexer and latch circuit is preset, and has a latch mode during which a value output by the selected complementary signal input stage is output by the circuit and also stored in the storage circuit.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: May 24, 2016
    Assignee: INPHI CORPORATION
    Inventor: Travis William Lovitt
  • Patent number: 9240786
    Abstract: Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HURL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HURL circuit has a differential power at a level that is resistive to DPA attacks.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 19, 2016
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kazuyuki Tanimura, Nikil Dutt
  • Patent number: 9136854
    Abstract: In one embodiment of the invention, a digital to analog convertor (DAC) is disclosed for converting a digital input signal into an analog output signal. The DAC includes a switch controller coupled to a digital input signal; a bias voltage generator coupled to a first terminal of an analog voltage power supply; and a switched current source array coupled to the switch controller and the bias voltage generator. The bias voltage generator generates a bias voltage. The switch controller generates a plurality of digital enable signals. The switched current source array includes a plurality of hybrid switched current cells coupled to the switch controller and the bias voltage generator. The plurality of hybrid switched current cells are coupled together at an analog output terminal to sum unit currents together, if any, and form the analog output signal in response to the digital input signal.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: September 15, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sung-Hwan Hong
  • Patent number: 8994406
    Abstract: A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: March 31, 2015
    Assignee: Nanyang Technological University
    Inventors: Joseph Sylvester Chang, Bah Hwee Gwee, Kwen Siong Chong
  • Patent number: 8975920
    Abstract: A multi-function programmable transceiver is described. The transceiver includes a driver circuit and a receiver circuit, which allows an Application Specific Integrated Circuit (ASIC) device to drive and receive data from other ASIC devices. Both the driver and receiver circuits share a common input/output (I/O) pin. The driver circuit can be programmed to provide one of the several driver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS. Other functional features of the transceiver that can be programmed are driving strengths or output impedance, output power supply voltage, single ended or differential mode of HSTL/SSTL transceivers, and class 1 or class 2 operations for SSTL/HSTL transceivers. The receiver circuit can also be programmed to provide one of the several receiver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: March 10, 2015
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Jai P. Bansal
  • Patent number: 8928355
    Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: January 6, 2015
    Assignee: Broadcom Corporation
    Inventors: Delong Cui, Afshin Momtaz, Jun Cao
  • Patent number: 8901964
    Abstract: A level shifter transfers a first voltage signal to a second voltage signal. The level shifter comprises a comparison circuit, a delay circuit, and a selection circuit. The comparison circuit generates a first signal according to the comparison result between the first voltage signal and the reverse-phase signal of the first voltage signal. The delay circuit generates a second signal according to the first voltage signal. The selection circuit receives the first and the second signals and chooses the higher voltage one from the first signal and the second signal to be the second voltage signal.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Industrial Technology Research Institute
    Inventor: Shien-Chun Luo
  • Patent number: 8890566
    Abstract: Described herein is a low-voltage circuit with an inductor tail and a common mode feedback loop for amplitude and current control. A first transistor pair can receive clock inputs, and a second transistor pair can receive data inputs and output the data to a logic gate. A tail inductor can be coupled to the first transistor pair to suppress high frequency common mode bounce induced by clock transitions in independent common emitter branches. A common mode feedback loop can be provided to maintain a constant average current. The common mode feedback loop and the tail inductor can together function in the same way as a tail current source at low frequencies and high frequencies respectively.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 18, 2014
    Assignee: Semtech Corporation
    Inventor: Daniel Kurcharski
  • Patent number: 8847628
    Abstract: Integrated circuit devices may utilize automatic methods for adjusting the tail currents of current mode logic (CML) cells, which compensate for variations in process corners and thereby enable reliable operation of high performance circuits, such as frequency synthesizers. An integrated circuit may include a current mode logic (CML) circuit responsive to at least one input signal and a variable current source electrically coupled to the CML circuit. This variable current source can be configured to sink (or source) a first current from (or to) the CML circuit in response to a control signal. A control circuit may also be provided, which is configured to generate the control signal in response to a process corner indication signal. This process corner indication signal, which may be generated by a process corner detection circuit, preferably has a magnitude that estimates a relative speed of a process corner associated with the integrated circuit device.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: September 30, 2014
    Assignee: Integrated Device Technology inc.
    Inventors: Minhui Yan, Chien-Chen Chen, Harmeet Bhugra
  • Patent number: 8823421
    Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 2, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: ManoharRaju K.S.V., Hiten Advani
  • Patent number: 8787831
    Abstract: A smart data storage apparatus and data transmitting method for the same are to combine the hard disk with the dual interface memory, and are to use radio frequency identification (RFID) technology or near field communication (NFC) technology. The information of the self-monitoring analysis and reporting technology (SMART) of the hard disk still could be received by the handheld device without the power for the hard disk. Moreover, the external hard disk could be registered with the handheld device quickly.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: July 22, 2014
    Assignee: Jogtek Corp.
    Inventors: Wei-Chun Huang, Tsung-Hsing Hsieh
  • Patent number: 8766668
    Abstract: An integrated circuit chip includes a first single ended type buffer configured to receive a first signal through a first pad, a second single ended type buffer configured to receive a second signal through a second pad, a differential type buffer configured to receive a third signal through the first pad and the second pad, a strobe input unit configured to receive a strobe signal synchronized with the third signal inputted to the first pad and the second pad, and a buffer control unit configured to control activation of the first and second single ended type buffers and the differential type buffer in response to the strobe signal.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 1, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seung-Min Oh
  • Patent number: 8723712
    Abstract: A digital to analog converter including at least one current steering source and a master replica bias network. Each current steering source includes a data current source, two switches, two buffer devices, and two activation current sources. The switches are controlled by a data bit and its inverse for switching the source current between first and second control nodes. The buffer devices buffer the control nodes between corresponding output nodes. The activation current sources ensure that each buffer device remains active regardless of the state of the switches. The master replica bias network includes a replica buffer device coupled to a replica control node and a master buffer amplifier. The master buffer amplifier drives the first, second and replica buffer devices in parallel to maintain the first, second and replica control nodes at a common master control voltage to minimize noise and glitches at the output.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohammad Nizam U. Kabir, Brandt Braswell, Douglas A. Garrity
  • Patent number: 8692576
    Abstract: A level shifting circuit and methodology involving a switching current generator responsive to switching of an input signal for producing a switching current to switch an output signal, and a holding current generator for producing a holding current to hold the logic level of the output signal in accordance with the logic level of the input signal. The holding current is produced independently of the switching current.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: April 8, 2014
    Assignee: Linear Technology Corporation
    Inventor: Jeffrey Lynn Heath
  • Patent number: 8674725
    Abstract: A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 18, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Kurahashi, Tomofumi Hokari, Takashi Muto, Goichi Ono, Hiroki Yamashita
  • Patent number: 8659319
    Abstract: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: February 25, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 8653856
    Abstract: A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: February 18, 2014
    Assignees: Texas Instruments Incorporated, Texas Instruments Deutschland GmbH
    Inventors: Oliver Piepenstock, Andreas Bock, Bhavesh G. Bhakta
  • Patent number: 8643340
    Abstract: An integrated circuit (IC) having an internal power supply voltage step down circuit provides efficiency while requiring a minimum of external terminals. In a first operating mode, a storage capacitor is charged from the power supply return of a group of circuits, while the group of circuits is powered from an input power supply voltage provided to the IC. In a second operating mode, the group of circuits is powered from the storage capacitor. The step-down circuit provides for halving the input power supply voltage, but multiple storage capacitors and additional operating modes can be provided for voltage division by greater factors. A sensing circuit can be employed to sense the voltage across the storage capacitor(s) and in response, select the operating mode, providing hysteretic control of the voltage supplied to the group of circuits.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: February 4, 2014
    Assignee: Cirrus Logic, Inc.
    Inventor: Gautham Devendra Kamath
  • Patent number: 8581628
    Abstract: A transmitter comprises a protection circuit; a first termination resistor having a first end coupled to a first voltage source, and a second end coupled to the protection circuit; a second termination resistor having a first end coupled to the first voltage source, and a second end coupled to the protection circuit, wherein the second end of the first termination resistor and the second end of the second termination resistor form a differential output pair; a current switch coupled to the protection circuit; a current source coupled to the current switch; and a pre-driver circuit coupled to the current switch, for controlling the current switch, making the differential output pair generate an output current. Wherein, the pre-driver circuit receives a second voltage source, and the first voltage source is higher than the second voltage source.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: November 12, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chun-Wen Yeh, Hsian-Feng Liu
  • Publication number: 20130207690
    Abstract: A field effect transistor current mode differential logic circuit comprising load transistors for converting the current output of each differential leg current to voltage output, and means for configuring the bulk of each differential leg's load transistor to be connected to the drain of the load transistor for use the logic circuit in Subthreshold Source Coupled Logic (STSCL) mode, and means for configuring the bulk of each leg load transistor to be connected to a voltage or to source of the same transistor for use in MOS current more logic (MCML) operation.
    Type: Application
    Filed: October 20, 2011
    Publication date: August 15, 2013
    Applicant: Aalto University Foundation
    Inventors: Matthew Turnquist, Lauri Koskinen, Jani Mäkipää, Erkka Laulainen
  • Patent number: 8466712
    Abstract: Embodiments of the present disclosure provide an integrated circuit, comprising a first feed forward equalizing (FFE) circuit configured to operate based on receipt of a first common mode voltage; a second FFE circuit coupled to the first FFE circuit, the second FFE circuit configured to operate based on receipt of a second common mode voltage that is different than the first common mode voltage; and a decision circuit coupled to both the first FFE circuit and the second FFE circuit, the decision circuit configured to selectively provide the first common mode voltage to the first FFE circuit or the second common mode voltage to the second FFE circuit.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: June 18, 2013
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Shimon Avitan, Liav Ben Artsi
  • Patent number: 8436658
    Abstract: A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters and is detected using differential receiver. One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: May 7, 2013
    Assignee: Xilinx, Inc.
    Inventor: William C. Black
  • Patent number: 8378714
    Abstract: A high voltage tolerant transceiver operating at a low voltage is provided, including two input/output pads to receive a receive signal and transmit a transmit signal; a transmitter block to transmit the transmit signal; a receiver block to receive the receive signal and provide an amplified signal; at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad. Also provided is a circuit to isolate the output of a transmitter from high voltages, including a first transistor and a second transistor. Also provided is a substrate isolating circuit, including a first transistor, a second transistor, and a third transistor so that the substrate voltage is isolated from a high voltage in the pads.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: February 19, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Xu Liang, Lei Kai, Bi Han
  • Patent number: 8324939
    Abstract: A differential logic circuit includes: a differential logic unit which receives a plurality of logic signals, performs a logic operation, and outputs a result of the logic operation from a pair of differential signal output terminals thereof; and a current source circuit which supplies current to the differential logic unit and which controls a magnitude of the current. The differential logic circuit further includes: a load circuit connected to the differential signal output terminals; and a load control circuit which is connected to the load circuit and controls a load of the load circuit such that a direct-current output voltage of the pair of differential signal output terminals is constant.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Jianqin Wang
  • Patent number: 8301093
    Abstract: A receiver circuit which can suppress a voltage amplitude appearing on a transmission line. The receiver circuit, coupled to a first and a second transmission lines which transmit information by using currents, includes a first and a second current sources, a first and a second conversion sections which convert currents which flow respectively therein to voltages, a first transistor whose source is coupled to the first current source and to the first transmission line, and whose drain is coupled to the first conversion section, and a second transistor whose source is coupled to the second current source and to the second transmission line, and whose drain is coupled to the second conversion section. The gate and the drain of the first transistor are respectively coupled to the drain and the gate of the second transistor.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: October 30, 2012
    Assignee: Panasonic Corporation
    Inventor: Takefumi Yoshikawa
  • Patent number: 8228093
    Abstract: A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: July 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Tomoko Chiba, Hirokazu Sugimoto, Toru Iwata
  • Patent number: 8220947
    Abstract: A first current source supplies a tail current It to a plurality of differential pairs. A pre-driver outputs gate signals to the gates of transistors of the corresponding differential pair. A pre-driver is configured to switch the state between the enable state and the disable state. In the enable state, the pre-driver outputs the gate signals that correspond to the differential signals. In the disable state, the pre-driver outputs the gate signals having levels which instruct the transistors of the corresponding differential pair to switch off.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: July 17, 2012
    Assignee: Advantest Corporation
    Inventors: Yasuyuki Arai, Shoji Kojima
  • Patent number: 8164361
    Abstract: A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch includes a tracking cell and a locking cell. In a first embodiment, the locking cell includes two complementary logic inverters and two transmission gates. When the locking cell is locked, the two gates are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates. Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second and third embodiment, the tracking cell involves a pair of inverters. The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: April 24, 2012
    Assignee: Qualcomm Incorporated
    Inventors: Babak Soltanian, Jafar Savoj
  • Patent number: 8159270
    Abstract: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals. With the transmitter and power supplies so configured, no one of the three power supplies must source or sink current to or from more than half of the transmitters at any given time, which reduces power supply loading and minimizes switching noise.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: April 17, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 8138793
    Abstract: An integrated circuit includes a CML swing reference voltage generating unit, a CML bias control voltage generating unit and a CML buffering unit. The CML swing reference voltage generating unit determines a level of a CML swing reference voltage in response to a frequency setting code and a CML bias control voltage. The CML bias control voltage generating unit compares the level of the CML swing reference voltage with a level of a CML target reference voltage and determines a level of the CML bias control voltage based on the comparison result. The CML buffering unit generates a CML output signal swinging in a CML region by buffering an input signal and determines a swing level of the CML output signal on the basis of the level of the CML swing reference voltage in response to the frequency setting code and the CML bias control voltage.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 20, 2012
    Assignee: Hynix Semiconductor
    Inventor: Kwan-Dong Kim
  • Patent number: 8098084
    Abstract: A transmission apparatus for differential communication includes a driver bridge circuit and a pair of noise protection circuits. The driver bridge circuit includes four output devices that are independently connected between each of a pair of transmission lines and a power line or a ground line. Each noise protection circuit is provided to a corresponding transmission lines. Each noise protection circuit includes a ground potential detector and an impedance controller. The ground potential detector detects a potential of the corresponding transmission line with respect to the ground line. The impedance controller causes an impedance of the corresponding transmission line with respect to the ground line to become equal to an impedance of the other transmission line with respect to the ground line, when the detected potential becomes outside a predetermined potential range.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: January 17, 2012
    Assignees: Nippon Soken, Inc., Denso Corporation
    Inventors: Youichirou Suzuki, Noboru Maeda, Shigeki Takahashi, Takahisa Koyasu, Kazuyoshi Nagase, Tomohisa Kishigami
  • Patent number: 8072242
    Abstract: Embodiments provide input/output devices having programmable logic that is programmable to operate input/output devices in one of two drive modes. In various embodiments, to operate an input/output device in a first drive mode, logic circuitry is programmable to couple a reference voltage to a gate of a transistor element of an output driver. In various embodiments, to operate an input/output device in a second drive mode, the logic circuitry is programmable to couple a bias voltage to the gate of the transistor element of the output driver. In various embodiments, the logic circuitry may also be programmable to couple one of a plurality of data inputs to the output driver to operate an input/output device in either a single-ended mode or a differential mode.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: December 6, 2011
    Assignee: Meta Systems
    Inventor: Jean Barbier
  • Patent number: 8035420
    Abstract: A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: October 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Yeon Byeon
  • Patent number: RE43160
    Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: February 7, 2012
    Assignee: Broadcom Corporation
    Inventor: Tsung-Hsien Lin