Abstract: A multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure.

Abstract: Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bis voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract: A method and apparatus for performing logic operations using a current mode logic circuit is provided. Further, a method and apparatus for performing high fan-in logic operations is provided. Further, a logic circuit that selectively steers current based upon a plurality of inputs is provided. Further, a method for performing logic operations using current steering is provided.

Abstract: A selectable receiver includes a first receiver module for receiving first input signal type and a second receiver module, different from the first receiver module, for receiving a second input signal type, both receiver modules coupled to the same receiver inputs. An internal common mode voltage for the first signal type or for the second signal type, is provided by respective common mode voltage networks, to the first or to the second receiver module, to facilitate AC coupling with the appropriate DC common mode voltage required by the signal type. If direct coupled, the internal common mode voltage is effectively swamped out by the common mode voltage of the input signal. The first receiver module or the second receiver module, and the associated first common mode voltage or second common mode voltage, are selected in the receiver based on a control signal.

Abstract: A high bandwidth clock buffer, including a steering circuit, significantly increases the maximum frequency at which CMOS technology can be used to perform high-speed logic functions. In particular, the clock buffer includes a steering circuit for enhancing a voltage follower stage. The steering circuit includes steering transistors positioned between voltage follower transistors and constant current sources. The steering circuit switches all or substantially all of the current from both of the constant current sources through whichever of the two voltage follower transistors is being pulled low, thus doubling the amount of current that is available for slewing when the output is being pulled low. At the same time, since the voltage follower transistor that is being pulled high no longer has to source the constant current I0, the effective maximum current that can be supplied to charge up the load capacitance is increased by approximately I0.

Abstract: A receiver circuit in a communication system receives a complementary potential signal having a ground level or a floating level from a transmitter circuit through a pair of transmission lines. The receiver circuit includes first and second switching transistors for supplying a complementary current signal based on the complementary potential signal, a current detection transistor for detecting the current flowing through the switching transistors, and a potential control unit for controlling the gate potentials of the switching transistors based on the detected current for implementing a negative feedback loop. The negative feedback loop compensates the influence by a fluctuation of the potential of the transmitter circuit or the receiver circuit.

Abstract: A capacitor-coupling differential logic circuit handling the output of a differential circuit using coupling capacitors and sense amplifier. The coupling capacitors can couple a control signal to the corresponding internal terminal, i.e., the output terminal of the differential circuit. During evaluation, the differential circuit generates a voltage difference on the internal signal of the internal terminal according to the input signal and the predetermined logic operation. The sense amplifier is used to amplify and output the voltage difference on the internal; signal at the internal terminal.

Abstract: A multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure.

Abstract: An improved sense amplifier ad method for sensing signals in a silicon-on-insulator (SOI) integrated circuit improve the performance of semiconductor memories and other circuits implemented in SOI technology. The bodies of amplifier transistors within the sense amplifier and bodies of input transistors to the sense amplifier are coupled to corresponding input signals, eliminating the history dependance that would result from unconnected bodies, while achieving faster switching times due to a dynamically produced difference in threshold voltage of the input transistors and amplifier transistors. The switching time is improved over circuits using input transistors and amplifier transistors having statically biased bodies.

Abstract: A data sampling system, including a data tracking circuit and a data latching circuit, that reduces the likelihood of metastability that arises through competition of the two circuits, where data sampling occurs in a transition time interval. A combined latching and weakened tracking circuit is provided in which the tracking operation cannot change an output signal from the latching operation after the latch resolves a valid logical state.

Abstract: A programmable linear transconductor circuit is disclosed. The programmable linear transconductor circuit includes a first current source and a second current source, a first group of transistors and a second group of transistors, a first load coupled to the first group of transistors, and a second load coupled to the second group of transistors, and a first group of switches and a second group of switches. Each switch in the first group of switches is selectively connected to a transistor from the first group of transistors to the first current source or the second current source. Similarly, each switch in the second group of switches is selectively connected to a transistor from the second group of transistors to the first current source or the second current source, accordingly.

Abstract: A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

Abstract: A differential signal current-mode logic (CML) circuit is provided which provides an equal delay output. Convention differential logic CML circuits have upper stage and lower stage transistors pairs. Input signals that are provided to the lower stage are necessarily delayed with respect to inputs provided to the upper stage. The present invention provides parallel upper stage sections so that each input signal is translated to the output through the same number of transistors. Thus, the delay associated with each input signal is made equal. Specific examples of exclusive OR, OR, and AND circuits are provided.

Abstract: The output slew rate of a differential transmission line driver (13) can be limited by suitably controlling signal slew rates (52) at the control inputs (neg, pos) of the drive switches (M1-M4) that control current flow through the load impedance (Rload) of the driver.

Abstract: A self-terminating FET digital logic receiver for impedance-matched interconnection to a transmission line having a uniform characteristic impedance. The receiver includes an input terminal, a current mirror formed by first and second FETs, and a load. First and second non-zero current level digital logic signals are received from the transmission line at the input terminal. The first current mirror FET is connected to the input terminal and configured to provide nonlinear current/voltage characteristics between the first and second current levels which approximate the characteristic impedance of the transmission line. Substantially all the current of the digital logic signals is therefore absorbed by the first FET to minimize signal reflections on the transmission line. The second FET is connected to the first FET to provide a mirror current having current levels proportional to the current levels of the digital logic signals.

Abstract: A method and a device for maintaining logic state stored in a storage device are described. For one embodiment, the device precharges at least two complimentary nodes in a storage device during the precharge cycle. During the evaluation cycle, the device receives an input data. After receipt of the input data, device stores at least one logic state at a storage node according to the input data. The device includes at least one conducting path to limit one store per each evaluation stage.

Abstract: A high bandwidth clock buffer, including a steering circuit, significantly increases the maximum frequency at which CMOS technology can be used to perform high-speed logic functions. In particular, the clock buffer includes a steering circuit for enhancing a voltage follower stage. The steering circuit includes steering transistors positioned between voltage follower transistors and constant current sources. The steering circuit switches all or substantially all of the current from both of the constant current sources through whichever of the two voltage follower transistors is being pulled low, thus doubling the amount of current that is available for slewing when the output is being pulled low. At the same time, since the voltage follower transistor that is being pulled high no longer has to source the constant current I0, the effective maximum current that can be supplied to charge up the load capacitance is increased by approximately I0.

Abstract: A differential output buffer includes first and second complementary data inputs, an idle input, and a differential output stage having first and second output stage control inputs and first and second differential data outputs. First and second push-pull circuits charge one of the first and second output stage control inputs toward a logic high voltage and discharge the other of the first and second output stage control inputs toward a logic low voltage based on relative logic states of the first and second data inputs. A logic low voltage supply generator is coupled to the idle input and the logic low voltage supply terminal for setting the logic low voltage as a function of the idle input.

Abstract: An input buffer circuit consumes a small amount of power and operates rapidly. The input buffer circuit includes a differential amplifier, a buffer, and a switched current path connected to the differential amplifier. The differential amplifier receives an input signal and a reference voltage and generates an internal signal from a node in the differential amplifier. The buffer generates an output signal from the internal signal. The switched current path can include a current source and/or a current sink that includes series connected transistors with gates that respectively receive the input and output signals. The switched current path is temporarily activated to provide a current that reduces charging or discharging time of the node in the amplifier. The current thus reduces the delay time between edges in the input signal and corresponding edges in the output signal. Accordingly, the input buffer circuit operates rapidly.

Abstract: A CMOS signal transmission system for sending a large amount of CMOS signals into a separate quiet analog power domain. Transmission system comprises a converter sub-system which provides at least another device stage through which noise in the CMOS signals must flow and be attenuated to provide converted CMOS signals and a multiplexer coupled to the converter wherein the multiplexer receives converted CMOS signals from the converter sub-system and also receives delayed path control signals. The converter comprises a constant current source for providing a high level voltage reference and a constant current, two complimentary pass gates, and two sets of components for providing paths to ground from the constant current source through the two complimentary pass gates.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bias voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: A complementary source coupled logic topology suitable for low voltage differential signaling is disclosed. The topology is referred to as complementary source coupled logic as it contains complementary differential paris and complementary source follows. The complementary differential pair provide low voltage swing, low gain, high bandwidth signaling with rail-to-rail input common-mode range. The complementary source followers combine and buffer the outputs of complementary differential pairs preserving the low voltage swing, low gain and high bandwidth.

Abstract: A differential tri-state circuit in which noise picked up by an output signal can be removed. The differential tri-state circuit is so configured that, by allowing the same currents to flow from a current source to a p-channel MOS FET and an n-channel MOS FET and to other p-channel MOS FET and other n-channel MOS FET, high impedance state exists between output terminals. With the p-channel MOS FET and the n-channel MOS FET being brought into conduction and with other p-channel MOS FET and other n-channel MOS FET being brought out of conduction, by causing terminating resistors RT1 and RT2 to be conducting or by bringing about a state being in reverse to the above, a 0 state or 1 state is outputted between output terminals.

Abstract: An output buffer circuit for differentially driving a symmetrical transmission line. The circuit enable power efficient operation at very high bit rates and keeps the common mode voltage on the transmission line within predetermined narrow limits. Circuitry is used to match the impedances of transmission lines and to control the bias of voltage sources at predetermined levels.

Abstract: The present invention achieves the stated input receiver goals by merging many of the different functions required into a single unit instead of serializing them in the more traditional fashion. The present invention provides a receiver circuit having both a source-follower pair of MOS transistors, and a source-coupled pair of MOS transistors. The connecting node between these two pairs is coupled to a sense amplifier. The simultaneous use of the source-follower pair, the source-coupled pair and the sense-amplifier transistors allows for fast amplification of the low-swing input to full-rail CMOS, when triggered by a CMOS input clock.

Abstract: An apparatus for and method of reducing transistor body effect when detecting and correcting a phase error between clock signals using delay-locked and phase-locked loop circuits. The clock signals are provided to an equal number of circuit elements in cross-coupled XOR circuits. The circuit includes a transconductance circuit having at least two PMOS transistors with their substrates directly connected to their sources.

Abstract: A differential multiplexer has first and second differential input pairs for receiving first and second input signals, a transistor for making active the first differential input pair by using as a control signal a first clock of a pair of differential first and second clocks, another transistor for making active the second differential input pair by using as a control signal the second clock, a first output terminal for outputting the first input signal if the first clock is larger than the second clock and outputting the second input signal if the second clock is larger than the first clock, and a second output terminal for outputting a paired differential signal of the signal output from the first output terminal.

Abstract: An electronic system includes a plurality of electronic circuits each having a signal input and output function, a bus to which the plurality of electronic circuits are connected, first termination resistors connected to ends of the bus, and a termination voltage circuit having a first part generating a first voltage and a second part generating a second voltage. The sum of the first voltage and the second voltage is supplied, as a power supply voltage, to output circuits of the plurality of electronic circuits connected to the bus. The second voltage is supplied to the first termination resistors as a termination voltage.

Abstract: A symmetrical loading and current supply arrangement is described for a differential-type logic means, and symmetrical voltage swings are thereby achieved in the logic output. In a preferred arrangement the output voltages are self-aligned to a CMOS level which facilitate conversion of the differential-type output to CMOS signals.

Abstract: A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1 and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.

Abstract: A common mode logic (CML) circuit having an improved bias circuit and an active MOS load operating exclusively in the triode region to provide improved performance characteristics including a high speed of operation. The bias circuit of the CML circuit comprises a pair of MOS transistors, one of which has an aspect ratio (W.sub.P /L.sub.P) and the other of which has an aspect ratio (W.sub.P /L.sub.P)/n, wherein 1<n<4. This configuration causes a third MOS transistor in the bias circuit to operate exclusively in the triode region. The CML circuit also includes a logic portion, which may be a logic gate or flip-flop, having a plurality of pairs of input MOS transistors for receiving differential input signals. In accordance with the invention, the logic portion has load MOS transistors which operate exclusively in the triode region.

Abstract: A logic circuit contains a first transistor with a logic signal supplied to the base and having its collector connected to an output node. A second transistor has a collector connected to the emitter of the first transistor and an emitter connected to a reference potential, in which the collector current supplied to the first transistor corresponds to the level of the control signal supplied to the base. A p-channel insulated gate field-effect transistor is connected between the power supply and the output node, and a first bias circuit supplies a bias voltage to the gate of the p-channel insulated gate field-effect transistor as the load. An n-channel insulated gate field-effect transistor is connected between the power supply and the output node and parallel to the p-channel insulated gate field-effect transistor as the load, and a second bias circuit supplies a bias voltage to the gate of the n-channel insulated gate field-effect transistor.

Abstract: A semiconductor integrated circuit that measures a current which flows upon deactivation of the circuit in order to test for a damaged transistor therein. The circuit includes an input node for receiving an input voltage, a reference node for receiving a reference voltage, a first source potential node for receiving a first source potential level, a second source potential node for receiving a second source potential level, and a sense circuit connected between the first source potential node and the second source potential node and brought into an operating state during a period in which the first source potential level is supplied. The sense circuit compares the input voltage and the reference voltage and outputs the result of comparison to a sense output node. A buffer circuit is connected between the sense output node and a buffer output node and is adapted to output a voltage corresponding to the voltage appearing at the sense output node to the buffer output node.

Abstract: In a level shifter circuit comprising two P-channel transistors (MP1, MP2), two N-channel transistors (MN1, MN2), two P-channel transistors (MP3, MP4) and two N-channel transistors (MN3, MN4) which are interposed the P-channel transistors (MP1, MP2) and the N-channel transistors (MN1, MN2), four P-channel transistors (MP7, MP8, MP9, MP10) are connected between node (#1, #2) and VCC/GND signal (IN2) in series to fix node potentials of the N-channel transistors (MN3, M4) to VCC/GND. Connected to the nodes (#1, #2), the P-channel transistors (NP9, MP10) have gates connected to GND as countermeasure of a breakdown voltage BVds. Connected to VCC/GND signal (IN2), the P-channel transistors (MP7, MP8) have gates which are directly connected to an input terminal (IN1) and an output terminal of an inverter (INV1), respectively.

Abstract: A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two amplifiers are connected together and each amplifier receives the same differential input signals. The tail-current transistor is self-biased using the current-mirror's gate-bias. This self biasing of each amplifier eliminates the need for an additional voltage reference and allows each amplifier to adjust its biasing over a wide input-voltage range. Thus the common-mode input range is extended using self biasing and complementary amplifiers.

Abstract: A dynamic current mode circuit for low-voltage and high performance VLSI applications, comprising a MOS current mode logic block and dynamic circuitry for precharging the outputs of the MOS current mode logic block, cross-coupled latches for enhancing performance of the MOS current mode logic block during an evaluation phase thereof, and a dynamic current source for enhanced speed and low power consumption.

Abstract: A regenerative amplifier is coupled to a combinational current-steering network to provide a combinational logic and register combination. A differential change in current on the register's input nodes due to current steering is amplified to provide complementary logic values at the output nodes of the register responsive to a clock signal. Various combinational logic functions are implemented by current steering networks. Such a configuration provides the advantages of economy of size, cost and power consumption in the combinational layout because the current steering transistors may be made smaller. Furthermore, such a configuration provides the advantage of decreased set-up time in a registered data path and immunity from external sources of noise via common mode rejection. In one embodiment, a regenerative amplifier includes cross-coupled inverters.

Abstract: A differential current switch logic (DCSL) system is provided which has an evaluation tree including a plurality of input terminals and a pair of complementary output nodes. The DCSL system also has an output network which establishes a pair of state outputs at a predetermined level during a precharge phase and establishes the state outputs at complementary levels in response to the evaluation tree output nodes during an evaluate phase. First and second NMOS transistors are connected in series between the DCVS output state network and the evaluation tree output nodes with their gates coupled to the state outputs to isolate the outputs from the evaluation tree following evaluation.

Abstract: Disclosed herein is a differential CMOS cell that achieves faster switching speeds than conventional CMOS logic by 1) biasing a differential pair of output nodes to a relatively high logic low voltage threshold, and 2) pulling up the differential pair of output nodes to a logic high voltage level. The differential CMOS cell is designed such that the difference between logic low and logic high voltage thresholds is much less than in traditional CMOS circuits (i.e., approximately 0.8 V-1.0 V as compared to 2.6 V). A lower voltage swing allows for fast switching of a differential output signal. In a preferred embodiment, the differential CMOS cell receives a primary differential input signal, and respective first and second secondary differential input signals.

Abstract: A synchronous differential logic system is provided for implementation of pipelined computational structures capable of hyperfrequency operation. An individual logic circuit has a differential cascode switch and a synchronous sense amplifier which operates as a latch. A plurality of differential inputs are connected to the differential cascode switch which produces complementary signals at first and second nodes. The cascode switch is connected to the synchronous sense latch which provides complementary output signals of the logic circuit. The synchronous sense latch comprises an equalization transistor and two cross-coupled inverters, each connected to first and second power supply buses. The equalization transistor is connected to the first and second outputs, of the logic gate and to a global system clock.

Abstract: A current amplifier driver capable of driving both 10 Base-T signalling and 100 Base signalling in a Local Area Network (LAN) includes one constant current source. A voltage controlled switch is contained in each of four vertical segment of an H-bridge circuit. Two voltage signals are applied to the switches to control the direction of current from a constant current source across a load. When one of the voltage signals is high, the other is low and two switches of the four switches turn on. The current amplifier driver sinks the constant current in a first direction, such that a voltage drop across the output nodes is positive. When the other voltage signal is high the switches that were on turn off, and the other two switches turn on to sink the constant current across the load in the opposite direction, such that a voltage drop across the output nodes is negative. When both voltage signals are low, all four switches turn off, and the output voltage is zero.

Abstract: The present invention achieves the stated input receiver goals by merging many of the different functions required into a single unit instead of serializing them in the more traditional fashion. The present invention provides a receiver circuit having both a source-follower pair of MOS transistors, and a source-coupled pair of MOS transistors. The connecting node between these two pairs is coupled to a sense amplifier. The simultaneous use of the source-follower pair, the source-coupled pair and the sense-amplifier transistors allows for fast amplification of the low-swing input to full-rail CMOS, when triggered by a CMOS input clock.

Abstract: The differential MOS current-mode logic structure of the present invention is comprised of a differential MOS transistor pair and a complementary MOS (CMOS) transistor for each of the transistors comprising the differential MOS pair. The gates of the CMOS transistors are coupled to the gates of the differential MOS pair. Since the gates of the differential MOS pair receive a differential signal from the inputs, the voltage between the gate and the source, Vgs, for each of the transistors comprising the MOS differential pair is not fixed. As a result, the gain of the CMOS current-mode logic structure of the present invention is high. In addition, since the gates of the CMOS transistors are coupled to the gates of the differential MOS pair, the current for the CMOS transistors is increased when charging the node capacitance and is decreased when discharging the node capacitance.

Abstract: A high speed logic module is formed to include a differential input formed as a pair of inductive transmission lines and a differential output also formed as a pair of inductive transmission lines. A pair of logic devices are included in the module, with the gate terminals of the devices coupled to separate ones of the input inductive transmission lines. The output terminals of the logic devices are coupled to separate ones of the pair of output inductive transmission lines. The effects of the intrinsic gate-to-drain capacitance C.sub.gd inherent in each logic device is compensated for by including a pair of cross-coupled neutralizing capacitors between the drain and gate terminals of the logic devices. Various logic circuits, such as oscillators, latches, delay lines, etc. can be formed using the differential, neutralized structure of the invention.

Abstract: A differential comparator is provided with an extended input range. In one embodiment, a differential amplifier is provided with a differential input buffer that allows for differential detection even with input voltage signal levels that extend two or more volts beyond the power supply voltage. A first transistor and a first resistor coupled in series are coupled in parallel with a second transistor and a second series resistor. The transistor drain terminals are both coupled to the power supply voltage, and a current source draws current from the common node of the resistors. Input voltages are supplied to the gates of the transistors, and the differential output voltages are provided from the transistor source terminals. A differential amplifier receives the differential output voltages and provides a single output voltage.

Abstract: A loading arrangement for an input stage of a source coupled logic gate comprises a loading element having at least one resistive element and at least one voltage limiting element connected in parallel with one another. There is also disclosed a loading arrangement comprising resistive and voltage limiting elements connected in parallel.

Abstract: This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings.