Abstract: Provided is a scanning-line driving circuit configured with a plurality of unit circuits cascaded in stages and integrally formed with a display panel. The unit circuit includes a first transistor, a resistor, a second transistor, and an output transistor. The first transistor has a first conductive electrode supplied with a first-level voltage and a second conductive electrode connected to a first node. The resistor is connected to the first node at a first terminal. The second transistor has a first conductive electrode supplied with a second-level voltage and a second conductive electrode connected to a second terminal of the resistor. The output transistor has a control electrode connected to the first node and a first conductive electrode connected to an output terminal. The resistor is formed in a semiconductor layer. The unit circuit further includes an upper electrode formed above the resistor.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a power supply voltage and first data. The second semiconductor device generates a control voltage whose level is adjusted in response to the power supply voltage. The second semiconductor device also receives the first data to generate second data having a swing width different from a swing width of the first data. The second data being driven is controlled by the control voltage.

Abstract: A wide bandgap voltage reference circuit generates a temperature stable negative bias reference voltage for use in wide bandgap circuits. The reference circuit uses field effect transistor (FET) based source feedback. It can also be used as source feedback in high power high bandgap device applications, where constant current is required over process and thermal variations.

Abstract: A semiconductor device which is capable of operating at an operation frequency “f”, includes a substrate, a first element unit and a second element unit. The substrate has a thermal diffusion coefficient “D”. The first element unit is formed on the substrate. The first element includes a first active element. The second element unit is adjacent to the first element unit on the substrate. The second element includes a second active element. The second active element acts on a different timing from the first active element. Moreover, a distance of between a first gravity center of the first element unit and a second gravity center of the second element unit is equal to or less than twice of a thermal diffusion length (D/?f)1/2.

Abstract: A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor.

Abstract: A switch circuit is disclosed. The switch circuit may include one or more arrangements of transistors coupled in a cascode configuration. The transistors used to implement the switch circuit may be configured for operation within a first range of voltages. The application in which the switch circuit may be implemented may require conveying signals within a second range of voltages that is greater than the first range of voltages. Thus, the switch circuit may include one or more additional transistors to ensure that a voltage drop between any two terminals of the transistors used in the switch circuit is within the first range of voltages.

Abstract: A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set at 50 ohms which is equal to the characteristics impedance of the external signal transmission path. The matching impedance between a internal signal transmission path (13) and an input-side or output-side IC or intermediate IC is set at 200 ohms which is higher than the 50 ohms. The semiconductor device reduces the current dissipation and can operate at a higher speed.

Abstract: A logic gate is described that has an N-type region, which may be an N-well or N-tub, forming a cathode of one or more Schottky diodes and a collector of an NPN bipolar transistor. Accordingly, the Schottly diodes and transistor do not need to be isolated from one another, resulting in a very compact logic gate. The logic gate forms a portion of a NAND function in one embodiment. One or more Schottky diodes between the collector and base of the bipolar transistor act as a clamp to prevent the transistor from saturating. The clamp diodes can also be used to adjust the output voltage of the gate to ensure downstream transistors can be fully turned off.

Abstract: An improved signaling system and method are provided that uses transconductance signaling rather than voltage or current signaling. A transient voltage applied to a first end of a conductor can produce a varying current placed into a low impedance node at a second end of the conductor. The second end is preferably pinned to a fixed voltage value, and the low impedance second end will allow current upon the second end to freely transition, enabling the conductor to arrive at a steady state condition much sooner than with conventional signaling methods. The present transconductance signaling method avoids large changes in voltage along the greater part of the conductor due to a current sent through this resistive conductor. This greatly improves transient behavior as, for example, evidenced by signal rise and fall times for digital signals produced by this transconductance signaling method.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

Abstract: A buffer circuit having an input and output terminals includes a first Schottky gate transistor connected between a voltage setting node and ground, a load device connected between a power supply and the voltage setting node, a second Schottky gate transistor connected between the output terminal and ground, the gate of the second Schottky gate transistor being connected to the voltage setting node, a third Schottky gate transistor connected between the output terminal and the power supply, the gate of the third Schottky gate transistor being connected to the input terminal, a resistor means connected the gate of the first Schottky gate transistor and input terminal for increasing a voltage level applied to the gate of the third Schottky gate transistor.

Abstract: A circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises a depletion mode MESFET device, coupled between at least one CMOS device and at least one other MESFET device, the depletion mode MESFET device limiting a current through a gate-source junction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of the at least one other MESFET device.

Abstract: A method and apparatus for reducing power consumption by gallium arsenide integrated circuits divides the integrated circuit into higher and lower frequency sections. The high frequency sections require a substantial portion of the system clock period to resolve their longest combinatorial paths. The lower frequency sections require a relatively small portion of the system clock period to resolve their longest combinatorial logic paths. The combinatorial logic paths of each of such lower frequency sections are designed using logic gates which are capable of being decoupled from the chip power supply by way of a power enable input. Edge triggered memory circuits such as flip-flops are also designed using the reduced power logic gates, except for their cross-coupled outputs so that they may retain their state.

Abstract: A semiconductor integrated circuit having a field effect transistor formed on a compound semiconductor is disclosed, that comprises a first power supply, a second power supply for supplying a voltage lower than a voltage that the first power supplies, and at least one virtual power supply that is not connected to the outside and that has a voltage between the voltage of the first power supply and the voltage of the second power supply, wherein the number of the virtual power supplies is designated to a value larger than the quotient of which the voltage between the first power supply and the second power supply is divided by the forward turn-on voltage of a gate electrode of the field effect transistor. In the case that a signal received from a circuit with a low voltage is connected to a circuit between any power supply, the signal is received by a directly coupled logic circuit with a depletion type field effect transistor as a drive circuit.

Abstract: An interface circuit includes an input current limiting circuit for limiting a current of an input signal fed from a preceding circuit, thereby outputting the current-limited signal to a following circuit which is constituted using a MES type transistor. The interface circuit also includes a level shifting circuit supplied with a first higher power supply voltage and a lower power supply voltage, for converting a level of the current-limited signal into a logic level of the following circuit which is supplied with a second higher power supply voltage. The interface circuit further includes a level judging circuit connected between the input current limiting circuit and the level shifting circuit, for judging a logic threshold level of the input signal based on a predetermined level reference voltage. By the constitution, it is possible to adapt the interface circuit for connection to the following circuit constituted using MES type transistors.

Abstract: Voltage translator apparatus to translate TTL or CMOS logic level inputs to 0/-5 V logic levels that is insensitive to temperative and bias supply variation. A unique circuit structure comprises a level shift stage employing transistors configured to level shift a source of operating potential to a controlling potential to be applied to a predriver stage. The controlling potential is a function of the input logic levels. The predriver stage drives an output stage capable of providing complementary 0/-5 V logic outputs. The configuration is such as to afford low power consumption as well as proper operation over wide bias supply and temperature ranges.

Abstract: A fine filling method for dental purposes is characterized in that a powder, a granulate, a solution (suspension) or paste containing hydroxy-apatite with or without an adjuvant is rubbed on the surface of teeth. A fine filler for use in this method is characterized in that a calcification-promoting protein is incorporated in hydroxy-apatite or tetracalcium phosphate.

Abstract: The high impedance state of a tri-state CMOS transistor output circuit is enhanced by serially connecting first and second Schottky diodes with the P-channel transistor and the N-channel transistor whereby in the high impedance state reverse bias of the substrate/source-drain diodes of the two transistors is prevented when the output of the circuit is taken beyond the supply voltage potentials of the output circuit.