Abstract: A boot charge circuit for charging a boot capacitor of a switching power converter with upper and lower switches including pulse circuitry that provides a boot refresh pulse in response to a pulse control signal transitioning to an active state to turn on the lower switch for a duration of the boot refresh pulse, and gate circuitry that prevents activation of the upper switch until after completion of the boot refresh pulse in response to the transitioning of the pulse control signal. The boot refresh pulse has a negligible duration relative to each switching cycle yet sufficient to charge the boot capacitor to enable a driver to turn on the upper switch. A load monitor may be included to disable the pulse circuitry from providing the boot refresh pulse during higher load levels.

Abstract: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Abstract: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Abstract: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Abstract: A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set at 50 ohms which is equal to the characteristics impedance of the external signal transmission path. The matching impedance between a internal signal transmission path (13) and an input-side or output-side IC or intermediate IC is set at 200 ohms which is higher than the 50 ohms. The semiconductor device reduces the current dissipation and can operate at a higher speed.

Abstract: A logic gate is described that has an N-type region, which may be an N-well or N-tub, forming a cathode of one or more Schottky diodes and a collector of an NPN bipolar transistor. Accordingly, the Schottly diodes and transistor do not need to be isolated from one another, resulting in a very compact logic gate. The logic gate forms a portion of a NAND function in one embodiment. One or more Schottky diodes between the collector and base of the bipolar transistor act as a clamp to prevent the transistor from saturating. The clamp diodes can also be used to adjust the output voltage of the gate to ensure downstream transistors can be fully turned off.

Abstract: A two-input logic gate circuit suitable for extremely high-speed operation, which operates on two differential signal pairs expressing respective logic inputs, includes a control signal generating circuit which converts the input differential signal pairs to two sets of differential control signal pairs respectively having first and second level ranges, to be supplied to a current switching section.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

Abstract: To prevent a deadlock in a latch circuit for deciding an input state of an SDA terminal in a system initialization state. An input/output control circuit 5 for always determining a data state in the system initialization state is provided.

Abstract: The basic building block of the invention is an inverter gate consisting of two stages: The first stage is an input logic switching stage consisting of a depletion mode pull-up FET whose gate is the input node and whose source-to-drain channel is connected in series through a level-shifting Schottky diode with the source-to-drain channel of an depletion mode pull-down FET between drain and source voltage rails. The source of the pull-up FET is connected to the diode's anode while the drain of the pull-down FET is connected to the diode's cathode and is the output node of the input logic switching stage. The level-shifting diode isolates the output node from the input node, which allows the input voltage to switch rail-to-rail without causing problems.