Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.

Abstract: In accordance with the disclosure, one or both semiconductor dies in a face-to-face arrangement may include a probe pad layer formed on a face of the die to allow the die to be individually tested prior to assembly of the dies. Thus, faulty dies may be discarded individually so they are not included in a composite semiconductor device, thereby increasing device yields. The probe pad layer also allows dies to be matched so that a composite semiconductor device achieves desired performance, which may further increase device yields. In some embodiments, the probe pads of the probe pad layer formed on the face of the die may be used to individually test the die, and may remain inactive, or inert, during operation of the composite semiconductor device.

Abstract: A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

Abstract: An RF driver circuit may include a wideband output impedance matching and gain circuit, a wideband input impedance matching and gain circuit, and a summer configured to sum the outputs of the wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit. The wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit may collectively provide the gain of the RF driver circuit. The wideband output impedance matching circuit may have a source follower configuration. The wideband input impedance matching circuit may have a common gate configuration. Controllable bias voltages may be used to maintain a constant gain and interface impedances in multiple modes of operation.

Abstract: A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Abstract: A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.

Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

Abstract: The invention relates to an array substrate for a display device and to a method for manufacturing an array substrate comprising a thin-film transistor (“TFT”). An array substrate according to an embodiment of the invention comprises a source electrode, a gate electrode and a drain electrode, wherein the gate electrode is located on a first metal layer, the source electrode and the drain electrode are located on a second metal layer, and in the case that dislocation occurs between the first metal layer and the second metal layer, the area of the overlapping region between the source electrode and the gate electrode keeps constant.

Abstract: A reverse-connection protecting device comprises an interface, a battery control module and an activation module. The interface includes first and second lead-in ends coupled to respective ones of first and second lead-out ends. The second lead-in end is couplable to a negative terminal of a backup battery. The second lead-out end is couplable to each negative terminal of a load and an external power supply. The battery control module is coupled to the first lead-in end of the interface and couplable to a positive terminal of the backup battery. The battery control module is configured to control the charging or discharging of the backup battery. The activation module is coupled to the battery control module, and couplable to the load and the external power supply.

Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.

Abstract: A circuit has a stacked structure having at least one symmetric FET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.

Abstract: A tunable depletion diode is provided. Within this depletion diode, there is a depletion mode transistor that is coupled to the anode terminal at its gate and the cathode terminal at its drain. A diode is coupled between the source of the depletion mode transistor and the anode terminal, and a variable capacitor is coupled between the source of the depletion mode transistor and the anode terminal, where the capacitance of the variable capacitor is controls the reverse recovery time of the tunable depletion diode.

Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

Abstract: A semiconductor device includes two unit circuits and a control unit. A middle point between the unit circuits is coupled with an inductive load. Each unit circuit includes a first switching element and a free wheel diode coupled in inverse-parallel with the first switching element. At least one of the unit circuits further includes a bypass section coupled in parallel with the first switching element and the free wheel diode. The bypass section includes a second switching element and a resistor coupled in series. The controller alternately turns on the first switching elements with a dead time during which both the first switching elements are turned off. The controller controls the second switching element coupled in parallel with one of the first switching elements to be an on-state when the one of the first switching elements transitions from an off-state to an on-state in the dead time.

Abstract: An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.

Abstract: A semiconductor device includes two unit circuits and a control unit. A middle point between the unit circuits is coupled with an inductive load. Each unit circuit includes a first switching element and a free wheel diode coupled in inverse-parallel with the first switching element. At least one of the unit circuits further includes a bypass section coupled in parallel with the first switching element and the free wheel diode. The bypass section includes a second switching element and a resistor coupled in series. The controller alternately turns on the first switching elements with a dead time during which both the first switching elements are turned off. The controller controls the second switching element coupled in parallel with one of the first switching elements to be an on-state when the one of the first switching elements transitions from an off-state to an on-state in the dead time.

Abstract: An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.

Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Abstract: An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer.

Abstract: An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.

Abstract: An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.

Abstract: A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, while second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.

Abstract: The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.

Abstract: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.

Abstract: It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply currents (111, 112). The circuit further comprises a second logic block (B2) coupled to the supply terminal (VDD) via the first resistor means (R1) and via the second resistor means (R2) for receiving respective third and fourth supply currents (122, 121). A first output terminal (Q?) coupled to the first block (B1) and to the first resistor means (R1). A second output terminal (Q+) coupled to the second logic block (B2) and to the second resistor means (R2). A first current source (I0) coupled to at least one of the first output terminal (Q?) and/or second output terminal (Q+) for providing a first supply current (I1) through the first resistor means (R1), which is substantially equal to a second supply current (I2) through the second resistor means (R2).

Abstract: Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.

Abstract: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.

Abstract: An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer.

Abstract: Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

Abstract: The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.

Abstract: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.

Abstract: To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in which a channel layer includes at least one element selected from In, Ga and Zn formed on a same substrate, the inverter being the E/D inverter having plural thin film transistors, is characterized by comprising the steps of: forming a first transistor and a second transistor, the thicknesses of the channel layers of the first and second transistors being mutually different; and executing heat treatment to at least one of the channel layers of the first and second transistors.

Abstract: Provided are an inverter, a method of operating the inverter, and a logic circuit including the inverter. The inverter may include a load transistor and a driving transistor, and at least one of the load transistor and the driving transistor may have a double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter.

Abstract: The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.

Abstract: Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.

Abstract: Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

Abstract: A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input nodes and the intermediate nodes, and the conduction states of the transistors being controlled by second complementary input signals to output a logical operation result of the first and second input signals to the intermediate nodes; and inverters for inverting the intermediate signals and producing complementary output signals, wherein the NMOS transistors of the logic network are configured as a depletion-type NMOS.

Abstract: Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.

Abstract: A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set at 50 ohms which is equal to the characteristics impedance of the external signal transmission path. The matching impedance between a internal signal transmission path (13) and an input-side or output-side IC or intermediate IC is set at 200 ohms which is higher than the 50 ohms. The semiconductor device reduces the current dissipation and can operate at a higher speed.

Abstract: Optimizing fly ash resistivity by controlling concentration of sulfur trioxide (SO3) in flue gas by the use of an algorithm.

Abstract: A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.

Abstract: A semiconductor integrated circuit includes: a logic circuit section including transistors formed on an SOI substrate; and a partially-depletion-type transistor, which is formed on the SOI substrate as a switching transistor for controlling ON/OFF states of the logic circuit section and which has a body contact portion. The partially-depletion-type transistor has a threshold voltage, which is substantially equal to that of the transistors in the logic circuit section when no potential is applied to the body contact portion and which is higher than that of the transistors in the logic circuit section when a potential is applied to the body contact portion.

Abstract: An inverter circuit is disclosed that prevents flow of a large feedthrough current. The inverter circuit includes depletion type MOS transistor combined with a resistor to impose a current limitation when a feedthrough current flows.

Abstract: A method and apparatus provides an efficient ratioed digital logic structure. The digital logic structure includes ratioed pull-up transistors and pull-down transistors such that the circuit noise margin does not substantially affect gain performance of the ratio stage. In one particular embodiment, a ratioed logic structure includes PMOS transistors and NMOS transistors that receive input voltage signals wherein a current path is induced in the NMOS transistors when a voltage input of zero or less is applied. Another feature of the present invention allows modification of gain performance of the ratio stage by arranging different ratios of the PMOS-to-NMOS transistor channel widths.

Abstract: To achieve a differential type logic circuit operating at a high speed and with a low voltage, the circuit is composed of a differential push-pull circuit comprising enhancement type NMOSFETs and depletion type NMOSFETs and a CMOS inverter pair circuit comprising inverters, and a threshold voltage of FETs of the CMOS inverter pair circuit is set to a value same as or greater than a threshold voltage of enhancement type FETs of the differential push-pull circuit and smaller than about ½ of supply voltage.

Abstract: A semiconductor integrated circuit includes: a logic circuit section including transistors formed on an SOI substrate; and a partially-depletion-type transistor, which is formed on the SOI substrate as a switching transistor for controlling ON/OFF states of the logic circuit section and which has a body contact portion. The partially-depletion-type transistor has a threshold voltage, which is substantially equal to that of the transistors in the logic circuit section when no potential is applied to the body contact portion and which is higher than that of the transistors in the logic circuit section when a potential is applied to the body contact portion.

Abstract: A high voltage level shifter includes one or more complementary pairs of transistors connected together in series separate the output terminal from the input terminal so as to prevent junction breakdowns, oxide breakdowns, and punch-through breakdowns.

Abstract: A transistor and a Pch circuit are connected in parallel to a power supply node of a CMOS circuit for receiving a power supply potential therefore. A transistor and an Nch circuit are connected in parallel to a ground node of the CMOS circuit for receiving a ground potential. During operation, the transistors are on, and the CMOS circuit operates fast. During standby, the Nch circuit or the Pch circuit is off in accordance with the state immediately before the standby. The Nch and Pch circuits are formed of transistors having larger threshold voltages than that of transistors of the CMOS circuit, so that a sub-threshold current during standby can be reduced.