Abstract: A light detection element, including a first light detection unit, a second light detection unit, and a driving transistor, is provided. The first light detection unit includes a first transistor and a first light sensing unit. The first transistor and the first light sensing unit are electrically connected. The second light detection unit and the first light detection unit are electrically connected. The second light detection unit includes a second light sensing unit and a second transistor. The second light sensing unit and the second transistor are electrically connected. The driving transistor has a gate terminal. The gate terminal is electrically connected to the first light sensing unit and the second light sensing unit. In a time interval, the first transistor is not turned on and the second transistor is turned on.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

Abstract: A semiconductor device has an off transistor (10) in which a gate electrode (3) and a source region (6) of an N-type MOS transistor are connected to a ground terminal and a drain region (5) is connected to an external signal terminal (100b). In the off transistor (10), the gate electrode (3) is extensively provided over a portion or entirety of the drain region (5) in addition to a channel region. A capacitance (C2) formed between the gate electrode (3) and the drain region (5) may be greater than a capacitance (C1) generated between the gate electrode (3) and a ground potential.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Abstract: A display panel, a stage circuit, and a driving method of the stage circuit are provided. The stage circuit includes cascaded shift register circuits. Each cascaded shift register circuit includes: a first control module, a second control module, and an output module. The first control module receives an input signal and a charging signal, and generates a voltage signal at a second node in response to a first clock signal and a voltage signal at a first node. With an exception of a first stage cascaded shift register circuit, a first transistor of a current stage cascaded shift register circuit has a first end connected to a signal output terminal of a previous stage cascaded shift register circuit, a second end connected to the second node, and a control end connected to the first node.

Abstract: Noise is reduced in a circuit that converts voltage. A voltage conversion circuit includes a conversion transistor, a current source transistor, and a control circuit. In this voltage conversion circuit, the conversion transistor converts a potential of an input signal, the potential being changed from one of two different potentials to the other, by using predetermined current, and outputs the converted signal as an output signal. Furthermore, the current source transistor supplies the predetermined current. Then, in a case where the potential of the input signal is changed to the other potential, the control circuit stops supplying the predetermined current.

Abstract: System on a Chip (SoC) integrated circuits are configured to reduce Static Random-Access Memory (SRAM) power leakage. For example, SoCs configured to reduce SRAM power leakage may form part of an artificial reality system including at least one head mounted display. Power switching logic on the SoC includes a first power gating transistor that supplies a first, higher voltage to an SRAM array when the SRAM array is in an active state, and a third power gating transistor that isolates a second power gating transistor from the first, higher voltage when the SRAM array is in the active state. The second power gating transistor further supplies a second, lower voltage to the SRAM array when the SRAM array is in a deep retention state, such that SRAM power leakage is reduced in the deep retention state.

Abstract: According to an aspect, a display device includes a plurality of sub-pixels. Each of the sub-pixels includes a memory block including a memory configured to store therein sub-pixel data and a sub-pixel electrode coupled to the memory block. The memory includes first and second transistors configured to store therein the sub-pixel data in accordance with an electrical charge of a floating gate, the first and second transistors include respective drains that are coupled to each other, and a coupling point of the drains is coupled to a node. The sub-pixel electrode is coupled to the node, and each of the sub-pixels is configured to display an image based on a potential of the node.

Abstract: An image sensor and pixel circuit therefor includes a photoelectric conversion device; an amplifier including a first input terminal connected to the photoelectric conversion device, and an output terminal; a capacitor disposed between the first input terminal and the output terminal; and a reset switch network disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch network including at least a first reset transistor, a second reset transistor, and a third reset transistor.

Abstract: Reference voltage generation circuits and related methods are disclosed. An example reference voltage generation circuit includes a voltage generating circuit including an enhancement mode (E-mode) gallium nitride (GaN) transistor, the voltage generating circuit to, in response to a first clock signal having a first phase, generate a first voltage associated with the E-mode GaN transistor, and, in response to a second clock signal having a second phase different from the first phase, generate a second voltage associated with the E-mode GaN transistor, and a switching capacitor circuit coupled to the voltage generating circuit, the switching capacitor circuit to generate a reference voltage based on a difference between the first voltage and the second voltage.

Abstract: A semiconductor chip may have at least one p-channel field effect transistor (FET), at least one n-channel FET, a first and a second power supply terminal, wherein the at least one n-channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p-channel FET and the at least one p-channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel FET, a precharge circuit to precharge the circuit to a first state, and a detection circuit configured to output an alarm signal if the circuit enters a second state.

Abstract: According to certain aspects, a level shifter includes a first branch including a first pull-up transistor configured to pull up a first node, and a first pull-down transistor configured to pull down the first node. The level shifter also includes a second branch including a second pull-up transistor configured to pull up a second node, and a second pull-down transistor configured to pull down the second node. The level shifter further includes a third branch including a third pull-up transistor configured to pull up a third node, and a third pull-down transistor configured to pull down the third node. The first branch is cross coupled with the third branch, the second branch is cross coupled with the third branch, the first pull-down transistor has a first channel width, the second pull-down transistor has a second channel width, and the first channel width is greater than the second channel width.

Abstract: A constant current source, a stable time base and a capacitor are used to self-check operation of an analog-to-digital convertor (ADC) by charging the capacitor for a pre-determined amount of time to produce a voltage thereon. This voltage will be proportional to the amount of time that the capacitor was charged. Multiple points on the ADC transfer function can be verified in this self-check procedure simply by varying the amount of time for charging of the capacitor. Relative accuracy among test points may then be easily obtained. Absolute accuracy may be obtained by using an accurate clock reference for the time base, a known current source and capacitor value.

Abstract: A shift register circuit includes a set circuit, a first reset circuit, a first control circuit, and an output circuit. The output circuit is configured to change an active potential at the first node further away from an inactive potential in response to a first clock signal transferred to a signal output terminal being active, and the first control circuit is further configured to, responsive to the first clock signal transferred to the signal output terminal being active, restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage, the second reference voltage having a magnitude between an active input pulse and the inactive potential.

Abstract: The present disclosure relates to an apparatus including level shifter circuitry configured to convert a voltage between one or more multi-voltage domains. The apparatus may include an integrated circuit having a cross-coupled latch including a first weak transistor cross-coupled with a second weak transistor. The integrated circuit may further include a first strong transistor in parallel with the first weak transistor and a second strong transistor in parallel with the second weak transistor. The integrated circuit may further include an inverter configured to toggle at least one of the first weak transistor and the second weak transistor.

Abstract: The electric apparatus includes first and second electrically driven elements operating in response to receipt of electric signals whose polarities reverse periodically at mutually same periods, and a signal outputter outputting the electric signals respectively to the first and second electrically driven elements. The first and second electrically driven elements are arranged such that each of their element surfaces faces toward the element surface of the other electrically driven element or such that their element surfaces face toward a same plane from mutually opposite sides across the plane. The signal outputter outputs the electric signals such that, in each period of the electric signals, a time period in which their polarities are mutually opposite is longer than a time period in which their polarities are mutually identical.

Abstract: In a logic circuit including transistors with the same conductivity, a reduction in output voltage is prevented with use of at least three transistors and a capacitor. With use of an oxide semiconductor in a semiconductor layer of the transistor, a logic circuit with high output voltage and high withstand voltage is achieved. With use of the logic circuit, a semiconductor device with high output voltage and high withstand voltage is achieved.

Abstract: An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

Abstract: A thin film includes a substrate, a bottom gate, a channel layer, a source and a drain, and a top gate. The bottom gate is disposed on the substrate. The channel layer is disposed on the bottom gate. The source and the drain are disposed on two different sides of the channel layer. The top gate is disposed on the channel layer, wherein the channel layer is disposed between the bottom gate and the top gate, and the bottom gate and the top gate are electrically isolated from each other. A related method is also provided.

Abstract: A differential odd integer divider provides low power and compact sub-harmonics of an applied square or sinusoidal clock signal with self-aligned 50% duty cycle. The odd integer divider circuit includes a set of low power delay cells connected in a ring fashion. Each delay cell includes two differential dual port inputs connected to the gates of MOS transistors. For instance, these odd integer dividers include a series of low power latch circuits that are custom configured for minimum headroom and low power consumption. These output phasors can then be combined with an appropriate weight factor to provide a near-sinusoidal waveshape from the input square waveshape. Intrinsic 50% duty cycle maybe shortened or stretched by using combinatorial logic circuits.

Abstract: A semiconductor device includes a setting circuit and a reset circuit. The setting circuit includes a latch circuit having first and second inverters driven by a first power voltage whose level is fixed and a first transistor which is switched between an ON state and an OFF state on the basis of a level of a second power voltage whose level varies depending on a surrounding environment, and sets data corresponding to a reference voltage to the latch circuit in response to the first transistor being switched to the ON state. The reset circuit includes an N-type second transistor connected to an output of the first inverter and an input of the second inverter. The second transistor sets data corresponding to the reference voltage to the latch circuit in response to the second voltage being equal to or lower than a predetermined voltage value.

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

Abstract: A multi-bit flip-flop has first and second one-bit flip-flops. The multi-bit flip-flop employs inter-cell clock switch (CSW) sharing in which the first and second one-bit flip-flops share at least one clock switch. The multi-bit flip-flop may also employ intra-cell CSW sharing in which at least one of the first and second one-bit flip-flops shares at least one clock switch. The inter-cell CSW sharing enables implementation of multi-bit flip-flops with fewer clock switches and possibly fewer data devices, while reducing power consumption, including state retention power gating power reduction.

Abstract: A switching device driving apparatus for preventing arm short circuit is provided, including: a first switching device driving unit for receiving a control signal for controlling a first switching device and a second switching device so that they will not turn ON at the same time and outputting an ON/OFF drive signal to the first switching device; and a second switching device driving unit for receiving the control signal and outputting an ON/OFF drive signal to the second switching device, in which the first switching device driving unit outputs a drive signal for increasing the delay of the ON timing of the first switching device with respect to the OFF timing of the second switching device with increase in ambient temperature.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

Abstract: A programmable low power driver permits an output impedance of the driver to be programmed. Programmability permits the driver output impedance to match an impedance of a transmission line that is connected thereto. The low power driver includes a first driver output and a plurality of driver legs. The programmable low power driver is configured to electrically couple one or more driver legs of the plurality of driver legs to the first driver output to establish an output impedance for the driver.

Abstract: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

Abstract: According to an exemplary embodiment, a shunt circuit includes a floating shunt switch configured to bypass at least one load, for example at least one LED, among a plurality of series-connected loads, such as a plurality of series-connected LEDs in a lighting system, responsive to a high-side control signal. The at least one load has terminals connected across the shunt circuit. The shunt circuit further includes a high-voltage level-shift up circuit configured to shift a low-side control signal up to the high-side control signal using a voltage of at least one of the terminals of the at least one load. The floating shunt switch can be configured to bypass the at least one load responsive to a failure of the at least one load.

Abstract: An integrated circuit (IC) for driving a light emitting semiconductor device is provided. The IC includes an input stage configured to receive a first input signal with a first differential pair of bipolar transistors and a second input signal with a second differential pair of bipolar transistors and to provide a pre-driver output signal being a superposition of the first input signal and the second input signal and an output stage including a third differential pair of bipolar transistors for receiving the pre-driver output signal of the input stage and for driving the light emitting semiconductor device in response to the pre-driver output signal, wherein the IC is configured to pre-distort the pre-driver output signal of the input stage so as to compensate a signal distortion of the output stage.

Abstract: A semiconductor device is provided, which includes a switch having a first transistor and a logic circuit having an output terminal. The logic circuit includes a bootstrap circuit having at least one second transistor. The bootstrap circuit is electrically connected to the output terminal. The first transistor and the second transistor have the same conductivity type. Each of the first transistor and the second transistor includes an oxide semiconductor layer including a channel formation region and a pair of gate electrodes with the oxide semiconductor layer provided therebetween.

Abstract: The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function.

Abstract: To provide a semiconductor device including an inverter circuit whose driving frequency is increased by control of the threshold voltage of a transistor or a semiconductor device including an inveter circuit with low power consumption. An inverter circuit includes a first transistor and a second transistor each including a semiconductor film in which a channel is formed, a pair of gate electrodes between which the semiconductor film is placed, and source and drain electrodes in contact with the semiconductor film. Controlling potentials applied to the pair of gate electrodes makes the first transistor have normally-on characteristics and the second transistor have normally-off characteristics. Thus, the driving frequency of the inverter circuit is increased.

Abstract: A system includes an inverter element to gate forward current flow from a first signal source, and a reverse current inhibition element to block reverse current flow towards the first signal source from a second signal source.

Abstract: When a semiconductor device is provided with an inverter comprising a transistor having a first gate and a second gate, the semiconductor device does not require a circuit for generating a potential to be input to the second gate of the transistor and has a small number of wirings. Moreover, a semiconductor device having high reliability is provided. The semiconductor device includes a plurality of stages of circuits each provided with two inverter circuits in parallel. Two inverter circuits in a given stage output respective signals of opposite polarities, which is utilized for interchanging signals output from inverter circuits in the previous stage. Thus, an inverted signal is input to the second gate of the transistor included in each of two inverter circuits in the subsequent stage.

Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

Abstract: A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Abstract: Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. The first transistors included in the inverters located at either odd-number orders or even-number orders counted from an input terminal side of an inverter chain circuit become conductive when a pre-charge signal has a first state to pre-charge the other end of the first transistors, and become non-conductive when the pre-charge signal has a second state.

Abstract: A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: According to one embodiment, a switch array includes first and second switches provided in a switch unit. The first switch includes first and second memory cell transistors and a first pass transistor. A second switch includes third and fourth memory cell transistors and a second pass transistor. The first and second memory cell transistor is provided in a first active region. The first pass transistor is provided in a second active region in the substrate. The third and fourth memory cell transistor is provided in the first active region. The second pass transistor is provided in the second active region adjacent to the first pass transistor in the channel length direction. The first and second active regions are adjacent to each other in a channel width direction.

Abstract: As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a plurality of capacitors. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region.

Abstract: A circuit comprises an inverter, a first transistor, a second transistor, and at least one switching circuit. The inverter has a first node and a second node. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal, and a sixth terminal. The at least one switching circuit is configured to switch a connection of at least one of the first transistor and the second transistor to the inverter. The second terminal and the fifth terminal are coupled to the first node. The third terminal and the sixth terminal are coupled to the second node. The first transistor and the second transistor are configured to cause a plurality of time delays at the second node.

Abstract: In a particular embodiment, a method includes discharging a first dynamic node at a first discharge circuit of a first dynamic circuit structure in response to receiving an asserted discharge signal. The first dynamic circuit structure includes the first dynamic node at a first voltage level and a first keeper circuit that is disabled when the asserted discharge signal is received. The asserted discharge signal has a second voltage level that is different from the first voltage level. A second keeper circuit of a second dynamic circuit structure is enabled responsive to discharging the first dynamic node to maintain a second dynamic node of the second dynamic circuit structure at the first voltage level.

Abstract: A circuit comprises an inverter, a first transistor, a second transistor, and at least one switching circuit. The inverter has a first node and a second node. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal, and a sixth terminal. The at least one switching circuit is configured to switch a connection of at least one of the first transistor and the second transistor to the inverter. The second terminal and the fifth terminal are coupled to the first node. The third terminal and the sixth terminal are coupled to the second node. The first transistor and the second transistor are configured to cause a plurality of time delays at the second node.