Current Mode Logic (cml) Patents (Class 326/127)
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Patent number: 10812059Abstract: A comparator is disclosed, for comparing a first input voltage with a second input voltage and generating a corresponding output voltage. The comparator includes a follower stage coupled to a first supply rail and a second supply rail, a follower stage input terminal for the second input voltage, and a follower stage output terminal. The comparator also includes an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal for the first input voltage, and an inverter stage output terminal for providing an inverter stage output voltage having a first range. A signal conditioning means is coupled to the inverter stage output terminal and generates a comparator output voltage at a comparator output terminal having a second range larger than the first range.Type: GrantFiled: March 5, 2019Date of Patent: October 20, 2020Assignee: Pragmatic Printing LTDInventor: Joao De Oliveira
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Patent number: 10778040Abstract: A power transmitter is a device for wirelessly supplying power to a power receiver, including: a power converter configured to convert power supplied from a power source into direct current (DC) power; a DC/alternating current (AC) converter configured to convert the DC power into AC power; a capacitor configured to be provided at an input of the DC/AC converter; and a controller configured to perform a discharge control of the capacitor after the power converter stops, wherein the controller performs the discharge control by changing at least one of a driving frequency and a phase shift amount of the DC/AC converter so that power supplied to the DC/AC converter by the capacitor is equal to or lower than withstand power of the DC/AC converter.Type: GrantFiled: August 24, 2017Date of Patent: September 15, 2020Assignee: IHI CorporationInventor: Shiro Nagaoka
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Patent number: 10560099Abstract: A semiconductor apparatus includes an input selection circuit that selects one of a first input signal and a second input signal in response to a control signal, and outputs the selected input signal as a selection signal, wherein swing levels of the first input signal and the second input signal are different one another. The semiconductor apparatus also includes a conversion circuit that generates an output signal, in response to the selection signal, which swings to a level substantially identical to a level of the second input signal.Type: GrantFiled: December 31, 2018Date of Patent: February 11, 2020Assignee: SK hynix Inc.Inventors: Gi Moon Hong, Kyung Hoon Kim
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Patent number: 10411916Abstract: Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may generate a first bias current for a first differential transistor pair included in a CML transmitter, and a second current source may generate a second bias current for a second differential transistor pair. The first differential transistor pair may route the first bias current through either leg of the first differential transistor pair based on a polarity of an input signal and the second differential transistor pair may route the second bias current through either leg of the second differential transistor pair based on the polarity of the input signal. Based on a first polarity, the second bias current may be routed to a ground reference, and based on a second polarity, the second bias current may be routed through the first differential transistor pair to modify a load current internal to the CML transmitter.Type: GrantFiled: February 28, 2019Date of Patent: September 10, 2019Assignee: Micron Technology, Inc.Inventors: Jeremy Kuehlwein, Gregory A. King
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Patent number: 10277426Abstract: Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may generate a first bias current for a first differential transistor pair included in a CML transmitter, and a second current source may generate a second bias current for a second differential transistor pair. The first differential transistor pair may route the first bias current through either leg of the first differential transistor pair based on a polarity of an input signal and the second differential transistor pair may route the second bias current through either leg of the second differential transistor pair based on the polarity of the input signal. Based on a first polarity, the second bias current may be routed to a ground reference, and based on a second polarity, the second bias current may be routed through the first differential transistor pair to modify a load current internal to the CML transmitter.Type: GrantFiled: August 27, 2018Date of Patent: April 30, 2019Assignee: Micron Technology, Inc.Inventors: Jeremy Kuehlwein, Gregory A. King
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Patent number: 10256998Abstract: Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may generate a first bias current for a first differential transistor pair included in a CML transmitter, and a second current source may generate a second bias current for a second differential transistor pair. The first differential transistor pair may route the first bias current through either leg of the first differential transistor pair based on a polarity of an input signal and the second differential transistor pair may route the second bias current through either leg of the second differential transistor pair based on the polarity of the input signal. Based on a first polarity, the second bias current may be routed to a ground reference, and based on a second polarity, the second bias current may be routed through the first differential transistor pair to modify a load current internal to the CML transmitter.Type: GrantFiled: May 3, 2018Date of Patent: April 9, 2019Assignee: Micron Technology, Inc.Inventors: Jeremy Kuehlwein, Gregory A. King
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Patent number: 10243563Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.Type: GrantFiled: December 29, 2016Date of Patent: March 26, 2019Assignee: INTEL CORPORATIONInventors: Andrea Bonetti, Jaydeep P. Kulkarni, Carlos Tokunaga, Minki Cho, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Patent number: 9787310Abstract: In some embodiments, a method may include receiving an input signal at an input stage of a circuit and amplifying the input signal using an amplifier of the circuit to produce a level-shifted output signal. The method may further include selectively controlling switches of an active load coupled to the input stage based on the level-shifted output signal to turn off current flow between transitions in the input signal.Type: GrantFiled: December 17, 2014Date of Patent: October 10, 2017Assignee: Silicon Laboratories Inc.Inventors: Chao Yang, Praveen Kallam
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Patent number: 9294091Abstract: An integrated circuit and method for providing a differential transmission line driver are disclosed. One embodiment of the differential transmission line driver comprises a current mode logic (CML) stage, and a cross-coupled n-channel enhancement type metal-oxide semiconductor field-effect transistor (NMOS) stage, wherein the cross-coupled NMOS stage provides a feedback current to the CML stage, where each output voltage of the differential transmission line driver is characterized by symmetrical rising and falling edges.Type: GrantFiled: October 17, 2013Date of Patent: March 22, 2016Assignee: XILINX, INC.Inventors: Vassili Kireev, Hsung Jai Im
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Patent number: 9257983Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.Type: GrantFiled: October 30, 2014Date of Patent: February 9, 2016Assignee: Infineon Technologies Americas Corp.Inventors: Min Fang, Massimo Grasso, Niraj Ranjan
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Patent number: 9229502Abstract: Embodiments of an AC coupled bus charging system are disclosed that may allow for different charging currents. The charging system may include a charging circuit and a control circuit. The charging circuit may be operable to controllably select different charging currents dependent upon the output of the control circuit.Type: GrantFiled: October 11, 2012Date of Patent: January 5, 2016Assignee: Apple Inc.Inventor: Julian Vlaiko
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Patent number: 8937495Abstract: Emitter-coupled logic circuits and systems that include such circuits are provided. Some emitter-coupled logic circuits include a plurality of fT-doubler circuits. Each fT-doubler circuit includes a plurality of transistors coupled to one another in an arrangement such that the plurality of transistors are configured to behave as a single enhanced transistor that has an effective unity current gain frequency that is higher than if a single transistor were used in its place. The fT-doubler circuits are configured to increase an operating frequency capability of the emitter-coupled logic circuit. Some emitter-coupled logic circuits include a plurality of cascode amplifier circuits. Each cascode amplifier circuit includes multiple transistors. An emitter of at least one first transistor of the plurality of transistors is coupled to a collector of at least one second transistor of the plurality of transistors Some emitter-coupled logic circuits may include both fT-doubler circuits and cascode amplifier circuits.Type: GrantFiled: March 28, 2013Date of Patent: January 20, 2015Assignee: Rockwell Collins, Inc.Inventors: Russell D. Wyse, Mark A. Willi, Michael L. Hageman
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Patent number: 8841936Abstract: A differential output circuit has a current source, a voltage source, first paired transistors which, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and is always turned off in a second operating mode, second paired transistors which, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode, third paired transistors which, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, and is always turned on in the first operating mode, and paired impedances.Type: GrantFiled: February 15, 2013Date of Patent: September 23, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Yutaka Nakamura
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Patent number: 8823414Abstract: A multiple signal format output driver is configurable to provide a current-mode logic (CML) output signal in response to a CML value of one or more first values of the control signal. The output driver is configurable to provide a low-power, low-voltage positive emitter-coupled logic (low-power LVPECL) output signal in response to a low-power LVPECL value of the one or more first values of the control signal. The output driver is configurable to provide a low-voltage differential signaling (LVDS) output signal in response to an LVDS value of the one or more first values of the control signal. The output driver may be configurable to provide a LVPECL output signal in response to a second value of the control signal. The output driver may be configurable to provide a high-speed current steering logic (HCSL) output in response to a third value of the control signal.Type: GrantFiled: May 11, 2012Date of Patent: September 2, 2014Assignee: Silicon Laboratories Inc.Inventors: Rajesh Thirugnanam, Srisai Rao Seethamraju
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Patent number: 8786314Abstract: A contactless power transfer system, including a coil configured to supply or receive power contactlessly via magnetic coupling, a bridge circuit having two direct current (DC) terminals and two alternating current (AC) terminals, and a smoothing capacitor connected between the DC terminals. A load is connectable to either end of the smoothing capacitor. One of the AC terminals is connected to one end of the coil via a first capacitor. The other of the AC terminals is connected to the other end of the coil. The bridge circuit includes two serially-connected circuits each having upper and lower arms, each arm having a semiconductor switch and a diode in reverse parallel connection. A second capacitor is connected in parallel to the semiconductor switch of an upper arm, or of a lower arm, or to two semiconductor switches respectively of an upper arm and of a lower arms, of the bridge circuit.Type: GrantFiled: November 17, 2011Date of Patent: July 22, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Kouji Maruyama, Akio Toba, Ayako Ichinose, Michio Tamate
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Patent number: 8723712Abstract: A digital to analog converter including at least one current steering source and a master replica bias network. Each current steering source includes a data current source, two switches, two buffer devices, and two activation current sources. The switches are controlled by a data bit and its inverse for switching the source current between first and second control nodes. The buffer devices buffer the control nodes between corresponding output nodes. The activation current sources ensure that each buffer device remains active regardless of the state of the switches. The master replica bias network includes a replica buffer device coupled to a replica control node and a master buffer amplifier. The master buffer amplifier drives the first, second and replica buffer devices in parallel to maintain the first, second and replica control nodes at a common master control voltage to minimize noise and glitches at the output.Type: GrantFiled: January 16, 2013Date of Patent: May 13, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Mohammad Nizam U. Kabir, Brandt Braswell, Douglas A. Garrity
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Patent number: 8653856Abstract: A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.Type: GrantFiled: September 16, 2011Date of Patent: February 18, 2014Assignees: Texas Instruments Incorporated, Texas Instruments Deutschland GmbHInventors: Oliver Piepenstock, Andreas Bock, Bhavesh G. Bhakta
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Patent number: 8598910Abstract: In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.Type: GrantFiled: August 2, 2012Date of Patent: December 3, 2013Assignee: LSI CorporationInventors: John Leshchuk, Joseph A. Manzella, Walter A. Roper
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Patent number: 8466712Abstract: Embodiments of the present disclosure provide an integrated circuit, comprising a first feed forward equalizing (FFE) circuit configured to operate based on receipt of a first common mode voltage; a second FFE circuit coupled to the first FFE circuit, the second FFE circuit configured to operate based on receipt of a second common mode voltage that is different than the first common mode voltage; and a decision circuit coupled to both the first FFE circuit and the second FFE circuit, the decision circuit configured to selectively provide the first common mode voltage to the first FFE circuit or the second common mode voltage to the second FFE circuit.Type: GrantFiled: January 10, 2011Date of Patent: June 18, 2013Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Shimon Avitan, Liav Ben Artsi
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Patent number: 8436658Abstract: A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters and is detected using differential receiver. One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.Type: GrantFiled: April 2, 2008Date of Patent: May 7, 2013Assignee: Xilinx, Inc.Inventor: William C. Black
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Patent number: 8324936Abstract: Differential current driving type transmitter and receiver, and an interface system having the transmitter and receiver. The transmitter includes a current source, a current direction selecting block, and a balancing switch block. The current source sources currents to a pair of transmission lines or sinks currents flowing through the pair of transmission lines. The current direction selecting block transfers a current flowing from the current source to one transmission line of the pair of transmission lines and a current flowing through the other transmission line of the pair of transmission lines to the current source. The balancing switch block initializes the pair of transmission lines to a balanced state.Type: GrantFiled: July 7, 2009Date of Patent: December 4, 2012Assignee: Silicon Works Co., Ltd.Inventors: Jun Ho Kim, Young Soo Ryu, Ju Pyo Hong, Jung Hwan Choi
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Patent number: 8138793Abstract: An integrated circuit includes a CML swing reference voltage generating unit, a CML bias control voltage generating unit and a CML buffering unit. The CML swing reference voltage generating unit determines a level of a CML swing reference voltage in response to a frequency setting code and a CML bias control voltage. The CML bias control voltage generating unit compares the level of the CML swing reference voltage with a level of a CML target reference voltage and determines a level of the CML bias control voltage based on the comparison result. The CML buffering unit generates a CML output signal swinging in a CML region by buffering an input signal and determines a swing level of the CML output signal on the basis of the level of the CML swing reference voltage in response to the frequency setting code and the CML bias control voltage.Type: GrantFiled: December 29, 2010Date of Patent: March 20, 2012Assignee: Hynix SemiconductorInventor: Kwan-Dong Kim
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Patent number: 7965105Abstract: A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.Type: GrantFiled: May 25, 2010Date of Patent: June 21, 2011Assignee: Micron Technology, Inc.Inventor: Dragos Dimitriu
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Patent number: 7940075Abstract: Disclosed is a differential pre-emphasis driver. The driver includes a first current source supplying a first current, a second current source supplying a second current greater than the first current, a first select circuit for selectively connecting the first current source to a first output terminal or a second output terminal, and a second select circuit for selectively connecting the second current source to the first output terminal or the second output terminal. The first and second select circuits pre-emphasize a transmission signal by selectively combining the first output terminal, the second output terminal, the first current source and the second current source.Type: GrantFiled: November 9, 2009Date of Patent: May 10, 2011Assignee: Dongbu Hitek Co., Ltd.Inventors: Duk Hyo Lee, Byung Tak Jang
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Patent number: 7936186Abstract: Embodiments of the invention relate generally to the field of duty cycle correction, and more particularly to method and apparatus for correcting duty cycle of a CMOS level signal when converted from a Current-Mode-Logic (CML) to a CMOS level signal via a CML to CMOS converter. The converter comprises a first differential pair unit to receive a CML level signal; a second differential pair unit to receive the CML level signal; and an embedded differential biasing unit, coupled with the first and the second differential pair units, to adjust drive strength of the first and second differential pair units based on a duty cycle of the CML level signal. The method for correcting duty cycle of the CMOS level signal output comprises receiving by the first differential pair unit a CML level signal; receiving by the second differential pair unit the CML level signal; and adjusting drive strength of the first and the second differential pair units based on a duty cycle of the CMOS level signal.Type: GrantFiled: December 4, 2009Date of Patent: May 3, 2011Assignee: Intel CorporationInventors: Guluke Tong, Sitaraman V. Iyer
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Patent number: 7893719Abstract: A digital data transmitting device is disclosed having differential signaling circuitry, a current source controller and a pair of transistor-implemented current sources is disclosed. The current source controller generates a current source control signal based on a detected mode of operation of the differential signaling circuitry. The pair of transistor-implemented current sources selectively generate source currents to adjust the output voltage levels as the differential output terminals in response to the current source control signal. The digital data transmitting device may also include a current bulk biasing circuit that generates a current source bulk biasing signal such that when the differential signaling circuitry is in one mode of operation, the current source bulk biasing signal retards currents leakage across the pair of transistor-implemented current sources.Type: GrantFiled: December 6, 2007Date of Patent: February 22, 2011Assignee: ATI Technologies, ULCInventors: Chihou Lee, Junho Cho
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Patent number: 7849373Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.Type: GrantFiled: September 30, 2008Date of Patent: December 7, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Patent number: 7821300Abstract: A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.Type: GrantFiled: December 3, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Dan P. Bernard, John C. Schiff, Glen A. Wiedemeier
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Patent number: 7724037Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.Type: GrantFiled: January 13, 2009Date of Patent: May 25, 2010Assignee: ATI Technologies ULCInventors: Junho Cho, Nancy Chan, Ramesh Senthinathan, Stephen Yue, Richard W. Fung
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Patent number: 7710159Abstract: The invention relates to an electronic device that includes an MCML Muller-c element. The MCML Muller-c element has a first differential stage for operating in a trans-conductance state converting the differential input to a differential output current implementing the logical behavior of the MCML Muller-c element and a second stage operating as a trans-impedance stage being coupled to the first stage. Further, the MCML Muller-c element has peaking circuitry being coupled to the first stage, such that the peaking circuitry and the first stage provide a negative capacitance to the MCML Muller-c element for reducing the damping factor of the MCML Muller-c element.Type: GrantFiled: June 19, 2007Date of Patent: May 4, 2010Assignee: NXP B.V.Inventor: Suhas V. Shinde
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Patent number: 7683673Abstract: Differential signal transmission circuitry in which multiple differential signal transmission circuits are coupled in a stacked relationship between the power supply electrodes to minimize power dissipation by reusing the signal currents among the channels.Type: GrantFiled: May 24, 2007Date of Patent: March 23, 2010Assignee: National Semiconductor CorporationInventors: David J. Fensore, Alexander A. Alexeyev
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Patent number: 7675326Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.Type: GrantFiled: June 27, 2008Date of Patent: March 9, 2010Assignee: Altera CorporationInventors: Mei Luo, Sergey Shumarayev, Wilson Wong, Chong H. Lee
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Patent number: 7656198Abstract: In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a logic control, and a combination differential driver coupled to the logic control, wherein the logic control receives a control signal for configuring the combination differential driver as a Low Voltage Differential Signaling (LVDS) driver or as a Transition Minimized Differential Signaling (TMDS) driver.Type: GrantFiled: December 3, 2007Date of Patent: February 2, 2010Assignee: Xilinx, Inc.Inventors: Shidong Zhou, Yi-hui Hsieh
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Patent number: 7649381Abstract: A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.Type: GrantFiled: December 14, 2007Date of Patent: January 19, 2010Assignee: Hitachi, Ltd.Inventors: Hiroki Yamashita, Fumio Yuuki, Ryo Nemoto, Hisaaki Kanai, Keiichi Yamamoto
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Patent number: 7619448Abstract: A transmitter provides fast settling times, slew rate control, and power efficiency while reducing the need for large external capacitors. The transmitter typically includes a pre-driver, driver, and replica circuit. The pre-driver can shift the voltage level of an input signal to produce a shifted signal. The pre-driver can shift the voltage level in response to a selectable load resistance circuit and a voltage regulation feedback signal. The driver receives the shifted signal and generates a driver output signal in response to the received shifted signal. The replica circuit can be a scaled replica of the pre-driver and the driver using scaled components from the pre-driver and driver circuits. The scaled components can be used to generate the voltage regulation feedback signal. The generated voltage regulation feedback signal represents, for example, whether the output voltage of the driver output is above a reference voltage.Type: GrantFiled: December 17, 2007Date of Patent: November 17, 2009Assignee: OmniVision Technologies, Inc.Inventors: Charles Qingle Wu, Yun-Hak Koh
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Patent number: 7579872Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, wherein a resistance of the first converter is variable. A second converter couples to the first converter, the second converter is operable to receive a signal in the second type and convert the signal into the first type, wherein a resistance of the second converter is variable. The driver is operable to scale the resistance of the first and second converters to provide a constant ratio between the resistance of the first and second converters.Type: GrantFiled: May 31, 2006Date of Patent: August 25, 2009Assignee: Fujitsu LimitedInventor: Jian Hong Jiang
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Patent number: 7576567Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases a differential output voltage.Type: GrantFiled: May 31, 2006Date of Patent: August 18, 2009Assignee: Fujitsu LimitedInventor: Jian Hong Jiang
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Patent number: 7564270Abstract: A driver circuit is provided herein. In general, the driver circuit includes a driver portion, a common mode feedback portion and a current replication portion. The feedback portion receives a common mode voltage (vcm) from the driver portion and an alternative common mode voltage (vcm_alt) from the current replication portion. The feedback portion selects one of the common mode voltages for comparison with a reference voltage and generates a feedback bias signal (vcmfb) based on a voltage difference there between. When the driver circuit is enabled, the actual common mode voltage (vcm) is used to maintain the output common mode voltage around the reference voltage. When the driver circuit is disabled, the alternative common mode voltage (vcm_alt) is used to keep the bias signal (vcmfb) from drifting away.Type: GrantFiled: June 27, 2007Date of Patent: July 21, 2009Assignee: Cypress Semiconductor CorporationInventors: Xiaohu Zhang, George Ansel
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Patent number: 7564268Abstract: A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes first, second, third and fourth n-type metal oxide semiconductor (NMOS). The buffer also includes first and second bias switching NMOS. The first bias switching NMOS is coupled between the source of the third NMOS and ground, and the gate of the first bias switching NMOS is coupled to the output of the first logic gate. The second bias switching NMOS is electrically coupled between the source of the fourth NMOS and ground, and the gate of the second bias switching NMOS is coupled to the output of the second logic gate.Type: GrantFiled: November 7, 2006Date of Patent: July 21, 2009Assignee: Integrated Device Technology, incInventor: Brian J. Buell
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Publication number: 20090115457Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.Type: ApplicationFiled: January 13, 2009Publication date: May 7, 2009Applicant: ATI Technologies ULCInventors: Junho Cho, Nancy Chan, Ramesh Senthinathan, Stephen Yue, Richard W. Fung
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Patent number: 7501860Abstract: A differential input driver circuit (10, 50) includes first and second transistors (Q0, Q3) as input transistors and third and fourth transistors (Q1, Q2) as diode-connected, cross-coupled transistors. In one embodiment, first, second, third and fourth transistors are NPN bipolar transistors. The base terminals of the first and third transistors are connected while the base terminals of the second and fourth transistors are connected. The input transistors receive a pair of differential input signals (In+/?) at the emitter terminals (24, 26) and provides a pair of differential output signals (Vo+/?) at the collector terminals (16, 18). The emitter terminals of the diode-connected transistors (Q1, Q2) couple the input signal at the emitter terminal of the first transistor to the collector terminal of the second transistor and vice versa. The cross-coupling of the third and fourth transistors enables the input driver to operate effectively in single-ended to differential conversion mode.Type: GrantFiled: December 3, 2007Date of Patent: March 10, 2009Assignee: National Semiconductor CorporationInventors: Andrew Fitting, Michael Maida
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Patent number: 7498847Abstract: An output driver of a semiconductor memory device that operates in a differential mode and in a single mode is disclosed. The output driver includes a current supplying circuit that operates as a resistor in a single mode and as a current source in a differential mode. Accordingly, the semiconductor memory device including the output driver can have high test efficiency, since the number of test pins utilized during a test operation can be selectively reduced for low frequency tests.Type: GrantFiled: January 18, 2007Date of Patent: March 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Hwan-Wook Park
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Patent number: 7495477Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.Type: GrantFiled: July 31, 2007Date of Patent: February 24, 2009Assignee: ATI Technologies, Inc.Inventors: Junho Cho, Nancy Chan, Ramesh Senthinathan, Stephen Yue, Richard W. Fung
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Patent number: 7486103Abstract: A switching system capable of reducing the noise of the output signal is provided. The switching system includes a first switch and a second switch, wherein the first switch conducts a first signal according to a first control signal; the second switch conducts a second signal according to a second control signal. And the voltages of the first control signal and the second control signal are restricted within a voltage interval to reduce the noise produced during the switching of the switches.Type: GrantFiled: April 12, 2007Date of Patent: February 3, 2009Assignee: Young Lighting Technology CorporationInventors: Shian-Sung Shiu, Chung-Che Yu, Kuo-Wei Peng
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Patent number: 7474126Abstract: Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic gates. Such logic gates include two or more differential input pairs. The collectors of the first transistors in each of the differential pairs are all electrically coupled to an upper voltage via a first load resistor. Similarly, the collectors of the second transistors in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor. Depending upon the relative values selected for the first and second load resistors, the gate operates as an AND gate or an OR gate.Type: GrantFiled: January 25, 2007Date of Patent: January 6, 2009Assignee: Texas Instruments IncorporatedInventor: Robert F. Payne
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Patent number: 7474127Abstract: According to one embodiment of the invention, a method for receiving a first signal in a first plurality of switching elements from a second plurality of switching elements, receiving a second signal in second plurality of switching elements from first plurality of switching elements, alternatively converting a first logic signal by first plurality of switching elements based on received first signal, and a second logic signal by the second plurality of switching elements based on received second signal. According to another embodiment of the invention, a system comprising a first plurality of switching elements to convert a first logic signal based on a predetermined input from a second plurality of switching elements, second plurality of switching elements to convert a second logic signal based on a predetermined input received from first plurality of switching elements; first and second plurality of switching elements to alternatively convert first and second logic signals.Type: GrantFiled: January 6, 2006Date of Patent: January 6, 2009Assignee: Intel CorporationInventor: Ravindran Mohanavelu
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Patent number: 7463068Abstract: A circuit for protection of a transceiver input includes an input transistor and a first resistor connected between the drain of the input transistor and an input node. A plurality of reverse-biased diodes connected between a supply voltage and the input node. An output node is connected to the source of the input transistor. A first forward-biased diode connected between the power supply and the plurality of reverse-biased transistors. A second forward-biased diode and a second resistor are connected between the first forward biased transistor and the gate of the input transistor. A pre-driver circuit includes first and second transistors forming a differential pair and driven by a differential input voltage. A third transistor is connected between sources of the first and second transistors and ground. First and second resistors are connected to drains of the first and second transistors, respectively. A fourth transistor is connected between a power supply voltage and the first and second resistors.Type: GrantFiled: March 2, 2007Date of Patent: December 9, 2008Assignee: Broadcom CorporationInventors: Wee Teck Lee, Tu Yun, Tian Hwee Teo
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Patent number: 7429874Abstract: Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.Type: GrantFiled: June 13, 2006Date of Patent: September 30, 2008Assignee: Electronics and Telecommunications Research InstituteInventors: Sang Jin Byun, Hyun Kyu Yu
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Patent number: 7425847Abstract: A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.Type: GrantFiled: February 3, 2006Date of Patent: September 16, 2008Assignee: Micron Technology, Inc.Inventor: Dragos Dimitriu
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Patent number: 7408384Abstract: A drive circuit of a computer system is for driving a mode indicator. The computer system includes a first port and a second port. The mode indicator includes a first receiving end and a second receiving end. The drive circuit includes a first input end connected to the first port, a second input end connected to the second port, a first output end connected to the first receiving end, a second output end connected to the second receiving end. A power supply is connected to the first input end and the second input end via a first resistor and a second resistor respectively. The mode indicator is dichromatic and has two LEDs emitting non-matching colored light.Type: GrantFiled: December 19, 2005Date of Patent: August 5, 2008Assignees: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Tong Zhou, Jia-Hui Tu