Abstract: High speed CML logic gate systems for providing selected Boolean logic functions. Two halves of a substantially symmetric first system, having a relatively small number (14) of CMOS transistors, are used to generate any of the logic functions AND, NAND, OR and NOR. Two halves of a substantially symmetric second system having another small number (10) of transistors are used to generate any of the logic functions XOR, XNOR and NOT. In either system, the sum of currents passing through certain voltage-controlling gates is substantially constant.

Abstract: A single stack bipolar logic AND gate for low power applications comprising: a first differential pair of transistors, each transistor of the first differential pair having base, emitter and collector terminals, a base of a first transistor of the first differential pair receiving an input signal A and a base of the second transistor of the first differential pair receiving its complement signal {overscore (A)}, the emitters of each transistor of the first differential pair being connected at a common node to a first constant current source; a second differential pair of transistors, each transistor of the second differential pair having base, emitter and collector terminals, a base of a first transistor of the second differential pair receiving an input signal B and a base of the second transistor of the second differential pair receiving its complement signal {overscore (B)}, the emitters of each transistor of the second differential pair being connected at a common node to a second constant current source;

Abstract: A current mode logic (CML) circuit includes an emitter follower circuit, a CML gate, and a Schottky diode that is coupled between the emitter follower circuit and the CML gate. Methods and other systems are also provided.

Abstract: An output circuit has a data control circuit, a variable resistance circuit, a common-mode voltage detection circuit, an adjusting circuit. The data control circuit controls data included in an output signal according to an input signal, the variable resistance circuit is connected in series with the data control circuit between a first power supply line and a second power supply line. Further, the common-mode voltage detection circuit detects a common-mode voltage of the output signal, and the adjusting circuit adjusts a resistance of the variable resistance circuit according to an output of the common-mode voltage detection circuit. The common-mode voltage of the output signal is adjusted to equal an optional voltage, and an amplitude of the output signal is adjustable.

Abstract: A logic gate that includes a first differential amplifier and a feedback circuit. The first differential amplifier has a number of first (e.g., non-inverting) inputs and a second (e.g., inverting) input, receives and senses input signals applied to the non-inverting inputs, and provides a differential output that is a particular logic function (e.g., an ‘OR’) of the input signals. The non-inverting inputs may correspond to the gates of a number of transistors coupled in parallel to form an OR function. The feedback circuit detects the (e.g., non-inverting node of the) differential output and provides a control signal for the inverting input of the first differential amplifier. The logic gate typically further includes a second differential amplifier that senses and further drives the differential output.

Abstract: First and second differential transistor pairs, where each may be intentionally unbalanced or balanced, are provided. First and second variable current generators are coupled to control respective tail currents of the first and second differential pairs. A switch circuit is coupled to equalize the voltages of the respective tail current nodes. Applications of the amplifier circuit include sense amplifiers and comparators.

Abstract: A dual mode output driver circuit within the architecture of a IEEE 1394-1995 IEEE 1394b compliant physical layer (PHY) circuit address the deficiencies of driver incompatibility between the first standard, IEEE 1394-1995, and the latest standard, IEEE 1394b. This output driver circuit of a serial bus structure which directly couples to a cable in a system for digital data transfer to and from the cable over the bus structure includes a current source, a first sub-circuit portion, a second sub-circuit portion, a switch and an amplifier. The first sub-circuit portion includes a reference voltage node. The current source connects to both the first and second sub-circuit portions to provide current. The second sub-circuit portion includes an external voltage bias node and a common mode voltage node, where the external voltage bias node connects to the cable.

Abstract: A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract: In a current mode logic (CML) circuit, a high impedance state is implemented at the output for a bi-directional buffer. The output common mode voltage can be adjusted at the same time, which is particularly useful for a CML off-chip driver.

Abstract: In a current mode logic (CML) circuit, a high impedance state is implemented at the output for a bi-directional buffer. The output common mode voltage can be adjusted at the same time, which is particularly useful for a CML off-chip driver.

Abstract: The invention provides a logic circuit which has a sufficient load driving capacity even in its operation with a low power supply voltage and can operate at a high speed. In a next stage to a differential circuit having an output stage for which an emitter followers are used, a folding circuit in which a pair of transistors of a diode connection are used to raise the signal level of differential outputs of the differential circuit.

Abstract: A multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure.

Abstract: An interface circuit from Common Mode Logic to a low voltage, fixed common mode output, with high current drive. The CML signal is received, and then re-referenced to a low-voltage band-gap supply. The circuit is arranged to provide an output data signal referenced to a second positive reference voltage supply responsive to receipt of a common mode input data signal referenced to a first positive reference voltage supply. The circuit avoids use of vertical PNP transistors in the signal path.

Abstract: A selectable receiver includes a first receiver module for receiving first input signal type and a second receiver module, different from the first receiver module, for receiving a second input signal type, both receiver modules coupled to the same receiver inputs. An internal common mode voltage for the first signal type or for the second signal type, is provided by respective common mode voltage networks, to the first or to the second receiver module, to facilitate AC coupling with the appropriate DC common mode voltage required by the signal type. If direct coupled, the internal common mode voltage is effectively swamped out by the common mode voltage of the input signal. The first receiver module or the second receiver module, and the associated first common mode voltage or second common mode voltage, are selected in the receiver based on a control signal.

Abstract: The invention relates to a current mode device (CMD). The CMD comprises a first, a second and a third pairs of voltage controlled current sources (CCS). The first pair has an active load that is controlled by the third pair. The first pair provides a first and a second output signals that drive the second pair. The second pair generates a first digital output signal and a second output digital signal depending on a first input signal and on a second input signal, respectively. The CMD further comprises a first, a second and a third current sources that supply a first current C1 in the first pair, a second current C2 in the second pair and a third current in the third pair. The overall delay depends on a ratio between C1 and C2 and the sharpness of the edges of the signals depend on a ratio between C1 and C3, respectively.

Abstract: A data sampling system, including a data tracking circuit and a data latching circuit, that reduces the likelihood of metastability that arises through competition of the two circuits, where data sampling occurs in a transition time interval. A combined latching and weakened tracking circuit is provided in which the tracking operation cannot change an output signal from the latching operation after the latch resolves a valid logical state.

Abstract: A single stack bipolar logic AND gate for low power applications comprising: a first differential pair of transistors, each transistor of the first differential pair having base, emitter and collector terminals, a base of a first transistor of the first differential pair receiving an input signal A and a base of the second transistor of the first differential pair receiving its complement signal {overscore (A)}, the emitters of each transistor of the first differential pair being connected at a common node to a first constant current source; a second differential pair of transistors, each transistor of the second differential pair having base, emitter and collector terminals, a base of a first transistor of the second differential pair receiving an input signal B and a base of the second transistor of the second differential pair receiving its complement signal {overscore (B)}, the emitters of each transistor of the second differential pair being connected at a common node to a second constant current source;

Abstract: A differential signal current-mode logic (CML) circuit is provided which provides an equal delay output. Convention differential logic CML circuits have upper stage and lower stage transistors pairs. Input signals that are provided to the lower stage are necessarily delayed with respect to inputs provided to the upper stage. The present invention provides parallel upper stage sections so that each input signal is translated to the output through the same number of transistors. Thus, the delay associated with each input signal is made equal. Specific examples of exclusive OR, OR, and AND circuits are provided.

Abstract: The present invention is a technique for dynamic element matching used in digital-to-analog converters (DAC's). An analog-to-digital converter (ADC) converts an analog signal into a digital code. A current-mode randomizer randomizes the digital code based on a control word provided by a pseudo random number generator. A digital-to-analog converter (DAC) converts the randomized digital code into an analog signal.

Abstract: A complementary source coupled logic topology suitable for low voltage differential signaling is disclosed. The topology is referred to as complementary source coupled logic as it contains complementary differential paris and complementary source follows. The complementary differential pair provide low voltage swing, low gain, high bandwidth signaling with rail-to-rail input common-mode range. The complementary source followers combine and buffer the outputs of complementary differential pairs preserving the low voltage swing, low gain and high bandwidth.

Abstract: A high speed, multiple input restrictive OR circuit with fully differential inputs and output is used in applications in which only one input can be active at a time. N differential voltage inputs are converted into N corresponding differential current signals of unit current values. The current signals corresponding to active complement input signals are summed together, with a compensation current equal to (N−1) current units subtracted from the total. The resulting compensated complement currents together with any active input current form a single differential current that indicates the logic state at the input. This differential current is preferably converted to a buffered output differential voltage in an output stage. For high accuracy applications, a common unit reference current is used to generate both a scaled compensation current and unit input stage source currents.

Abstract: This invention relates to interfacing high speed, low voltage, data streams with CMOS circuits and, more specifically, to converting low voltage, differential, ECL signal levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability for larger system applications. This is accomplished primarily by making the first stage inverters 5 and 6 as geometrically small as possible and providing additional cross-coupled buffers 7 and 8 capable of driving large capacitive loads.

Abstract: A tristate circuit for driving three signal levels to a pin of a device-under-test is disclosed. The tristate circuit includes a driver having an output at a first signal level and adapted for coupling to the pin. A first switching unit couples to the output and responds to a programmed signal. The first switching unit operates to selectively alter the first signal level to a second signal level. A second switching unit connects serially to the first switch. The second switching unit responds to a second programmed signal and operates to cooperate with the first switch to alter the second signal level to a third signal level.

Abstract: It is common that the presence of a defect causes abnormal gate output voltage excursions in data buffers, AND gates, OR gates and multiplexers in current-mode logic circuits. A voltage excursion is detected by a voltage excursion detection apparatus which includes a built-in detector. The detector, which is little overhead, is used to monitor output swings of all gates (differential circuits) and flags all abnormal voltage excursions. These detection results cover classes of faults that cannot be tested by stuck-at testing methods only. The voltage detection apparatus works well below "at-speed" frequencies.

Abstract: A multiple input, low voltage, OR/NOR gate architecture based on a single-ended OR/NOR gate circuit, wherein a plurality of input transistors are connected in parallel. A reference transistor connects to the input transistors. A feedback means connects the NOR output signal to the base or gate of the reference transistor. The feedback means provides an effectively differential input for the multiple input circuit, without increasing circuit complexity, thereby providing enhanced noise margin characteristics.

Abstract: This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings.

Abstract: A phase meter and method of providing a voltage indicative of a phase difference between a reference signal and an input signal in which the amplitudes of the two signals are made approximately the same to cancel potential phase errors caused by different amplitudes, and the two signals are provided to two matched comparators, one receiving the input signal and the other receiving the reference signal. The two matched comparators are connected together so as to provide an output logic signal in accordance with a prescribed, unconventional, truth table. The output logic signal is a pulse whose duration is proportional to the phase difference. The output logic signal is converted to a voltage indicative of the phase difference between the reference signal and the input signal. The phase meter is relatively simple to make and a preferred embodiment measures phase shift directly with a 10 mV/degree output at up to 10 MHz.

Abstract: An emitter coupled logic gate (300) avoids the use of stacked transistors by utilizing a single-ended bias input and positive feedback (320) between first and second transistors (304, 306) to achieve an inverter function. The inverter (300) can also be configured as an OR gate (500) by adding a third transistor biased by second single-ended logic input. The OR gate (500) can be configured into an exclusive OR gate (901) by converting another set of single-ended bias inputs into what can be either differential or non-differential outputs (921, 923) to be used as inputs to OR gate (919).

Abstract: The invention relates to a logic circuit of the emitter-coupled type. For operation with a low supply Voltage, for example a single battery element, the bases of the transistors (Q1, Q2) forming a differential pair receive the input signal (Vi, Vi) via a coupling capacitance (C1, C2), a low-frequency bias being provided by means of MOS transistors (M1, M2) driven by input signals opposed to those applied to the corresponding bases, said MOS transistors being coupled to a line (3) at a voltage (vb) higher than the supply voltage (V1) supplied by a generator (10) provided for this function.

Abstract: A logic circuit has at least one first differential stage made of bipolar transistors operating in linear mode. The first differential stage is connected in a branch of a second differential stage biased by a current source. The second stage and the current source are made of MOS transistors.

Abstract: A new logic family is identified that achieves much better speeds than CML logic gates. This new logic family operates with multiple inputs and a single logic level, using differential pairs of transistors for each input transistor of the multiple input. This new logic family enables high speed operation, or higher speed, than the prior art, together with lower operating current and a power-delay enhancement significantly increased over the prior art.

Abstract: A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).

Abstract: In an active pull down ECL apparatus including a current switch formed by an input transistor and a reference transistor, an emitter follower controlled by a collector voltage of the input transistor or the reference transistor, and an active pull down circuit connected to the emitter follower, a resistor is connected to an emitter of the input transistor or the reference transistor.

Abstract: A BICMOS input stage includes a level shifting stage (35) and a level converter/buffer circuit (60). The input stage receives a single-ended GTL level input signal and a reference voltage, and in response, provides differential BICMOS level output signals. The input stage operates over a wide range of values for the reference voltage, does not require the generation of complex bias voltages, and provides well controlled output signals.

Abstract: An improved differential gain stage for a bipolar monolithic integrated circuit. The integrated circuit is formed from a semiconductor substrate, and the differential gain stage includes first and second bipolar transistors. The base of the first transistor and the base of the second transistor form a differential input for the gain stage comprising non-inverting and inverting inputs respectively. The collectors of the transistors form a differential output. The differential gain stage includes a capacitor stage comprising: a peaking capacitor, and first, second, third and fourth capacitor structures. The peaking capacitor is coupled between the emitters of the first and second transistors. The first and second capacitor structures are located at a first spaced relationship from the substrate and the first capacitor is coupled to the emitter of the first transistor and the second capacitor is coupled to the emitter of the second transistor.

Abstract: A multiplexer configuration includes at least one first and one second group of transistors each including one first, one second and at least one third transistor. Current sources are connected to a first supply potential terminal and emitters of the transistors of each respective one of the groups are connected to one another and to a respective one of the current sources. A first resistor has one terminal connected to a second supply potential terminal and has another terminal and collectors of the first transistors of each respective one of the groups are connected to one another and to the other terminal of the first resistor. An output terminal is connected to the other terminal of the first resistor. Bases of the second transistors of each respective one of the groups are input terminals for a respective data signal. Bases of the third transistors of each respective one of the groups are terminals for a respective selection signal. The selection signals are mutually complementary.

Abstract: A current mode logic switching stage, especially an output stage for driving capacitive loads, includes a differential amplifier configuration and at least two bipolar transistors, which are connected as an emitter follower circuit to the output of the differential amplifier configuration. The emitter of one of the bipolar transistors is connected with an output of the switching stage. A controllable current source, which is controlled by a comparison device, is connected between the output and a negative supply potential. The comparison device receives emitter signals of the bipolar transistors. The current source is controlled in such a way that it impresses a high current only during a negative output signal edge. The comparison device is formed with a current mirror.

Abstract: An integrated circuit device ECL test access port (TAP) is constructed for low static current requirements and low power consumption when the TAP is inactive. The ECL test access port may conform with IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture. An SCS logic circuit (50) is incorporated in the TAP controller coupled to the flip-flops (32,34,36,38) of the TAP controller n state finite machine for generating a current sink switch control signal (SCS) according to the state of the TAP controller. A current sink switch circuit (24) is coupled to respective current sinks of ECL gates incorporated in the boundary scan register (BSR/TDR1), design specific TAP data registers (DS/TDRs), TAP instruction register (TIR), and device identification register (DIR/TDR3). The current sink switch circuit (24) has an input coupled to the SCS logic circuit (50) to receive the current sink switch control signal (SCS).

Abstract: A circuit for measuring voltages in a three-phase installation, in particular an installation of the metalclad type, the circuit including for each of the phase conductors: a capacitive divider including a first capacitor connected firstly to said conductor and secondly to a second capacitor (C1, C2, C3) connected to ground, the circuit being characterized in that the voltage (v1, v2, v3) of each of the second capacitors (C'1, C'2, C'3) of the dividers is respectively applied firstly to the input of an inverter (I1, I2, I3) and secondly via a first resistance (R1, R2, R3) to the negative input of an operation amplifier (A1, A2, A3) which is also connected via second and third resistances (R21, R12, R13, and R31, R32, R23).