Abstract: This disclosure relates to apparatus and methods for radio-frequency (RF) switching circuits, and more particularly for a PIN diode driver circuit for high speed, high repetition rate and/or high power applications. The PIN diode driver may include a dual voltage reverse bias provided to the PIN diode, which dual voltage reverse bias may be provided by a first, relatively lower voltage, power supply and a second, relatively higher voltage, power supply. The relatively lower voltage is to discharge an intrinsic layer of the PIN diode at a lower voltage than during reverse bias of the PIN diode at the second relatively higher bias voltage in order to reduce overall power consumption.

Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region.

Abstract: A tunable RF filter, comprising: an emitter follower stage (2); and a common emitter stage (4); the common emitter stage (4) providing feedback to the emitter follower stage (2). The common emitter stage (4) may comprise a first transistor (Ti) being the only transistor of the common emitter stage (4); and the emitter follower stage (2) may comprise a second transistor (T2) being the only transistor of the emitter follower stage (2). A further tunable RF filter provides improved linearity, comprising: an emitter follower stage (22); a joint common emitter and emitter follower stage (24); and a gain stage (26); a common emitter output of the joint common emitter and emitter follower stage (24) providing feedback to the emitter follower stage (22), and an emitter follower output of the joint common emitter and emitter follower stage (24) providing an input to the gain stage (26).

Abstract: A semiconductor device having a plurality of cascaded IC's (14, 15, 16), wherein the matching impedance between a signal transmission path (12) connected to an external signal transmission path and an input-side or output-side IC (14, 16) is set at 50 ohms which is equal to the characteristics impedance of the external signal transmission path. The matching impedance between a internal signal transmission path (13) and an input-side or output-side IC or intermediate IC is set at 200 ohms which is higher than the 50 ohms. The semiconductor device reduces the current dissipation and can operate at a higher speed.

Abstract: A system within a complementary logic circuit having a true tree and a complement tree, for correcting an illegal non-complementary output caused by a defect in either tree. A complementary logic circuit has a true tree for producing a true signal and a complement tree for producing a complement signal. The true signal is utilized to generate a true output signal from the complementary logic circuit and the complement signal is utilized to generate a complement output signal from the complementary logic circuit. Multiplexing means within the true and complement trees are utilized to selectively replace the true (complement) signal with the complement (true) signal within the true (complement) tree, such that the complement (true) tree is utilized to correct the occurrence of a proscribed non-complementary condition at the output of the complementary logic circuit to diagnose a defect during diagnostic testing or to override a defect during normal runtime operation.

Abstract: A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to generate a true output signal from the complementary logic circuit. The complement tree produces a complement signal utilized to generate a complement output signal from the complementary logic circuit. Logic means coupled to the output of the complementary logic circuit detect an occurrence of a non-complementary output from the complementary logic circuit. Multiplexing means within the true tree is utilized to selectively replace the true signal with the complement signal within the true tree in response to detection by the logic means of a non-complementary output, such that a non-complementary output is seamlessly detected and rectified.

Abstract: A method and system for detecting faults within dual-rail complementary logic circuits. A method and system are disclosed for detecting faults within dual-rail complementary logic circuits. A dual-rail complementary logic circuit is coupled to an associated complementary fault detection circuit within an integrated circuit. Thereafter, the presence of a non-complementary logic signal can be detected at an output of the complementary fault detection circuit, in response to providing an input signal at an input of the dual-rail complementary logic circuit, such that the presence of a non-complementary logic signal at an output of the complementary fault detection circuit indicates the presence of a fault within the associated complementary logic circuit.

Abstract: A series-gated ECL driver, such as a series-gated ECL cut-off driver, is provided with settable output rise time and settable output fall time, in order to reduce noise at the output of the driver while limiting the delay resulting from such noise reduction. A method is also provided for so controlling an ECL driver. The driver includes at least two current switches fed by a current source. Each current switch includes a NOR side including one or more transistors, and an OR side including one or more transistors. The input to the NOR side of one such current switch can be buffered with an input emitter follower, and the output from that current switch can be buffered with an output emitter follower. A capacitance is connected across the one current switch and the current source, that is between the collector(s) and emitter(s) of the NOR side transistor(s) of that current switch, and the input side of the current source.

Abstract: A PNP bipolar transistor is connected to both ends of a resistive element of a Super Push-Pull Logic (SPL) circuit so as to place an emitter thereof at the side of a power supply source. Resistive elements and an NPN bipolar transistor forms a bias circuit for biasing a low voltage to a base of the PNP bipolar transistor. The base of the PNP bipolar transistor is connected to an emitter node of a NPN bipolar transistor through a capacitative load element. By this construction, the present invention can provide signal without any delay to turn on the PNP bipolar transistor. Therefore, the collector response speed of the SPL circuit can be increased.