Parasitic Prevention In Integrated Circuit Structure Patents (Class 326/15)
  • Patent number: 10770134
    Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chen Lin, Wei-Min Chan, Chih-Yu Lin, Shih-Lien Linus Lu, Yen-Huei Chen
  • Patent number: 10530612
    Abstract: A subscriber station for a bus system and a method for reducing line-related emissions in a bus system are provided. The subscriber station includes an edge controller for symmetrizing switching edges in the bus system. The edge controller includes an element for generating a setpoint voltage characteristic on a bus in the bus system and a current mirror for transmitting the generated setpoint voltage characteristic to the bus.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: January 7, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Axel Pannwitz, Bernd Hilgenberg, Steffen Walker, Ingo Hehemann
  • Patent number: 10284024
    Abstract: The invention relates to a method and an apparatus for detecting at least one interfering body in a system for inductive energy transmission, wherein the system includes at least one primary coil unit, wherein the apparatus includes at least one interfering body detector means, wherein the at least one interfering body detector means includes at least one field coil means and at least one detector coil means which is assigned to the at least one field coil means, wherein the apparatus includes at least one evaluation means, wherein the interfering body is detectable depending on the state of coupling and/or the change in the state of coupling, wherein the apparatus includes at least one compensation means.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: May 7, 2019
    Assignee: Bombardier Primove GmbH
    Inventors: Christoph Ludwig, Adrianus Johannes Steinfort, Wolfgang Ludwig
  • Patent number: 10050981
    Abstract: The present disclosure is directed to attack detection through signal delay monitoring. An example system may comprise at least one device including a physical interface. At least one signal delay monitor may determine whether a signal being transmitted to the device is received as expected at the physical interface and indicate a potential attack when the signal is determined to not be received as expected. Determining whether the signal is received as expected may include determining whether the signal is received within a window defining a time period in which receipt of the signal is expected. An example signal monitor may comprise at least a new data reception monitoring module and an expected reception window monitoring module. These modules may include logic to determine whether the signal is received within the window. An indication of a potential attack may trigger, for example, security-related actions in the system.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Eugene Kishinevsky, Siddhartha Chhabra
  • Patent number: 9966943
    Abstract: A system and method for a high-side power switch includes a gate driver configured to be coupled to a power switch, a voltage measurement circuit configured to be coupled directly to the power switch, a switch monitoring circuit configured to be coupled to the power switch, the switch monitoring circuit configured to measure an output current of the power switch, a current limitation circuit coupled to the gate driver and the switch monitoring circuit, the current limitation circuit configured to regulate gate-source voltage of the gate driver when the output current exceeds a threshold value, and a controller coupled to the current limitation circuit and the voltage measurement circuit, the controller configured to determine a mode of operation according to a startup voltage measured by the voltage measurement circuit during a startup sequence, the controller further configured to provide the threshold value to the current limitation circuit according to the mode of operation and a switch voltage measured by
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 8, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Christian Djelassi, Alexander Mayer, Robert Illing
  • Patent number: 9898625
    Abstract: A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: February 20, 2018
    Assignee: NXP USA, INC.
    Inventors: Alfredo Olmos, James R. Feddeler, Miten H. Nagda, Stefano Pietri
  • Patent number: 9859890
    Abstract: A method for protecting analog or mixed signal ICIP uses adjustment requirements of analog circuits to provide an obfuscated mechanism for preventing unauthorized use of an analog or mixed-signal IC (“AIC”) by disabling the AIC until application of an adjustment signal that is within a narrow enabling subrange. Embodiments significantly increase the adjustment range beyond the enabling subrange, and/or omit AIC tuning outputs that are not required for operation of the IC. Embodiments include “clipping” circuits that render the AIC outputs unresponsive to tuning signals outside of the enabling subrange. Information regarding the enabling subrange and/or a separate enabling IC can be provided to authorized users, and/or enabling bits of a digital adjustment input can be permanently set by the ICIP owner after AIC manufacture. The ICIP can be further protected by a security feature that can be unique to each AIC, and/or by using a two-foundry production method.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 2, 2018
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Christopher A Maxey, Thomas E Collins, III
  • Patent number: 9819258
    Abstract: Systems and methods for latch-up detection and mitigation. One aspect includes a method implemented in a system divided into a plurality of power blocks, where each power block is powered by a corresponding power rail and includes a voltage droop monitoring circuitry. The method comprises receiving frequency information from the plurality of voltage droop monitoring circuitries; normalizing the received frequency information from each of the plurality of voltage droop monitoring circuitries; creating a matrix of cross-correlation values based on the normalized frequency information between each pair of the plurality of power blocks; determining deviations in the cross-correlation values indicating an occurrence of voltage droop; determining an abnormal variation based on the determined deviations to identify a first power block, out of the plurality of power blocks, experiencing a latch-up event; and resetting power to the first power block without interrupting power to rest of the plurality of power blocks.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Clark Vandam, Suriya Kumar, Suraj Sindia, Ricardo Ascazubi, Curtis Shirota
  • Patent number: 9667061
    Abstract: A semiconductor element drive device includes a drive circuit which drives a semiconductor element configuring a power conversion device; an alarm generation circuit which generates alarm signals with pulse widths corresponding to protection factors in accordance with the outputs of detection circuits which detect information necessary for the operation of protecting the semiconductor element; an output circuit which externally outputs the alarm signals at a predetermined level; a protection cancellation circuit which generates a protection cancellation signal over a fixed period in accordance with the inverting output of a drive stop signal generation circuit, which stops the drive of the semiconductor element by the drive circuit in accordance with the outputs of the detection circuits, and with the output of the alarm generation circuit; and an output control circuit which changes the signal output level of the output circuit in accordance with the protection cancellation signal.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: May 30, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kiyoshi Sekigawa
  • Patent number: 9548726
    Abstract: A driver integrated circuit (IC) device. The driver device can include a front-end module, a pre-driver module, and a driver module coupled to a transmission line path. The pre-driver module can be coupled to the front-end module and can include one or more delay adjust capacitor modules, and one or more pull-down control modules. The driver module can be coupled to the pre-driver module, the driver module including one or more pull-down control logic modules. This driver device can configured in several implementations to provide control and programmability of a driver slew rate to maximize a signal integrity eye opening.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: January 17, 2017
    Assignee: INPHI CORPORATION
    Inventors: Cosmin Iorga, Jeffrey C. Yen
  • Patent number: 9425803
    Abstract: Methods and apparatuses for implementing a Physically Unclonable Function (PUF) and random number generator capabilities comprising providing a device under test comprising a plurality of bits comprising integrated circuits each including a capacitor; placing the bits in a first state with charge on selected bit capacitors; stopping bit refresh for a first predetermined time; re-enabling refresh for a second predetermined time to read and refresh charge on all bits; reading all bits and recording addresses of bits that have experienced bit flip from a first state to a second state comprising from “1” to “0” state; performing selecting a plurality of said recorded addresses to generate a PUF or cryptographic key; and performing an operation comprising a test or verification operation with said generated information PUF or key. Various hardware elements are also provided as well as machine readable instructions for implementing and controlling aspects of the invention.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 23, 2016
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Adam Duncan, Matthew Gadlage, Austin Roach, Matthew Kay
  • Patent number: 9013207
    Abstract: In some embodiments, provided is a processor chip including self deactivation logic to deactivate the processor chip after a threshold of qualified events have been monitored.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Yuri I. Krimon, David I. Poisner, Reinhard R. Steffens
  • Patent number: 8981810
    Abstract: A method, non-transitory computer readable medium, and apparatus for preventing accelerated aging of a physically unclonable function (PUF) circuit are disclosed. For example, the method monitors an environmental condition associated with the physically unclonable function circuit, detects a change in the environmental condition associated with the physically unclonable function circuit, and, in response to the change in the environmental condition, implements a security function for preventing the accelerated aging of the physically unclonable function circuit.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: March 17, 2015
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Austin H. Lesea
  • Patent number: 8928348
    Abstract: A current-mode-logic gate designed to have a first electronic path and a second electronic path. Each electronic path has a pair of transistors. The second electronic path is physically separated and identical to the first electronic path. In operation, a first input signal is transmitted through the first electronic path of the current-mode-logic gate to produce a first output signal. Similarly, a second input signal is transmitted through the second electronic path of the current-mode-logic gate to produce a second output signal.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: January 6, 2015
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Patrick Fleming, Bin Li, Lloyd Brown
  • Patent number: 8847621
    Abstract: A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: September 30, 2014
    Assignee: The Boeing Company
    Inventors: Ethan Cannon, Salim Rabaa, Josh Mackler
  • Patent number: 8823413
    Abstract: A device for sensing a binary signal includes a device configured to measure a signal level of the signal, a device configured to determine whether the measured signal level is “low” or “high”, a device configured to provide a variable input impedance, and a device configured to control the input impedance in response to the measured signal level. The variable input impedance may be provided by way of a transistor and a resistor, and by controlling the duty ratio of the transistor using pulse width modulation. Preferably, the input impedance is controlled to be low for low signal levels and to be high for high signal levels, which results in a more reliable sensing of binary signals. The device may be used for detecting the state of contact transducers suffering from parasitic resistances caused by moist and/or polluted environments. Further, a method of sensing a binary signal is provided.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: September 2, 2014
    Assignee: ABB Technology AG
    Inventors: Hans Björklund, Krister Nyberg, Tommy Segerbäck
  • Patent number: 8624624
    Abstract: Power isolation during time intervals of sensitive operations is disclosed. In one embodiment, a programmable chip package includes a programmable chip configured to perform a sensitive operation, and a switch configured to selectively couple a main power source to the programmable chip. The programmable chip package may also include an alternate power source and a controller that is configured to control the switch to decouple the main power source from the programmable chip during a time interval of the sensitive operation, wherein the programmable chip is configured to draw power from the alternate power source during the time interval. The controller is further configured to control the switch to couple the main power source to the programmable chip after the time interval.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: January 7, 2014
    Assignee: Lockheed Martin Corporation
    Inventors: David May, Burton Wolfe
  • Patent number: 8624622
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function, providing for the IC to continue the same functioning despite defects which may arise during operation.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 7, 2014
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Patent number: 8581617
    Abstract: Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: November 12, 2013
    Assignee: Altera Corporation
    Inventors: Dirk A. Reese, Bruce B. Pedersen
  • Patent number: 8513974
    Abstract: Systems and methods for reducing power distribution network noise are provided. For example, in one embodiment, a method includes determining delay variations of a user design via a delay sensor of an integrated circuit (IC). The delay variations are associated with voltage variations of the user design. Low frequency components of the voltage variations are filtered via control logic of the IC to obtain an AC response of the user design. An artificial current load is introduced to the IC to negate the AC response of the user design.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: August 20, 2013
    Assignee: Altera Corporation
    Inventor: John Curtis Van Dyken
  • Patent number: 8407653
    Abstract: Approaches for estimating a derating factor for a plurality of potential soft errors in a circuit implementation of a circuit design. A plurality of respective estimated toggle rates are determined for a plurality of circuit elements for implementing the circuit design. A derating factor of the circuit design is determined as a function of the estimated toggle rates of the plurality of circuit elements. The derating factor is an estimation of a fraction of the plurality of potential soft errors that would cause functional failure of the circuit design.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: March 26, 2013
    Assignee: Xilinx, Inc.
    Inventors: Paul R. Schumacher, Austin H. Lesea
  • Patent number: 8378710
    Abstract: Various embodiments relate to an anti-tampering circuit for a secure device including: a signal delay detector; a clock delay detector; a clock duty cycle detector; and a protection unit that receives an error indication from the signal delay detector, clock delay detector, and the clock duty cycle detector, wherein the protection unit indicates tampering to a secure device upon receiving the error indication.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: February 19, 2013
    Assignee: NXP B.V.
    Inventors: Ghiath Al-Kadi, Jan Hoogerbrugge, Massimo Ciacci
  • Patent number: 8232819
    Abstract: Disclosed is a closed-loop feedback system for controlling the soft error rate (SER) due to radiation strikes on electronic circuitry. A variable sensitivity soft error rate detector provides and output corresponding to the soft error rate. This output is supplied to a voltage control. The output of the voltage control is fed back to the sensitivity control of the sensor—thus forming a feedback loop. The output of the voltage control may be the power supply of the soft error rate sensor. The output of the soft error rate sensor may also be used to enable and disable fault tolerant schemes or alert a user.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: July 31, 2012
    Assignee: LSI Corporation
    Inventors: Mark F. Turner, Jeffrey S. Brown
  • Patent number: 8222915
    Abstract: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: July 17, 2012
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Clinton W. Kelly
  • Patent number: 8191021
    Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: May 29, 2012
    Assignee: Actel Corporation
    Inventor: Sana Rezgui
  • Patent number: 8174285
    Abstract: In order to protect an integrated circuit provided with a cryptoprocessor from attacks aiming to reveal secrets, it is anticipated to use a component sensitive to the activation of a parasitic (latchup) thyristor and/or to the activation of a parasitic bipolar transistor, or to design a circuit having this property. If the component is stressed due to the presence of this circuit, it is immediately deactivated, actually preventing the revelation of the secrets thereof.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: May 8, 2012
    Assignee: European Aeronautic Defence and Space Company EADS
    Inventors: Nadine Buard, Cedric Ruby, Florent Miller, Imad Lahoud
  • Patent number: 8035410
    Abstract: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: October 11, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiki Uemura, Yoshiharu Tosaka
  • Patent number: 7982489
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Grant
    Filed: September 27, 2009
    Date of Patent: July 19, 2011
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Patent number: 7948261
    Abstract: A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which each output of the at least one flip-flop circuit is input, wherein each of the flip-flop circuits includes a selector that selects a normal data signal in the normal operation mode, selects an inverted output of the flip-flop circuit in the low power consumption mode, based on an operation-mode switching signal that designates switching between the normal operation mode and the low power consumption mode, and inputs the selected signal to a data input terminal of the flip-flop circuit.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: May 24, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Kawakami
  • Patent number: 7948260
    Abstract: A method and apparatus for aligning the phases of digital clock signals are disclosed. For example, a phase alignment circuit according to one embodiment includes a frequency adjuster comprising a first plurality of inputs, where at least some of the first plurality of inputs are coupled to an output of a digital clock of an integrated circuit, a phase adjuster comprising a second plurality of inputs, where at least some of the second plurality of inputs are coupled to a plurality of outputs of the frequency adjuster, and an XOR gate comprising a third plurality of inputs, each of the third plurality of inputs being coupled to one of the plurality of outputs of the frequency adjuster.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: May 24, 2011
    Assignee: Xilinx, Inc.
    Inventor: Radimir Shilshtut
  • Patent number: 7944230
    Abstract: The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 17, 2011
    Assignee: University of South Florida
    Inventors: Nagarajan Ranganathan, Koustav Bhattacharya
  • Patent number: 7936179
    Abstract: A semiconductor integrated circuit includes: a ladder resistor; a ROM decoder; and a test circuit. The ladder resistor includes a plurality of resistors series-connected to each other and is supplied with a correction voltage at least one of both ends of the series connection and a plurality of connection points in the series connection to generate a plurality of gradation voltages at the plurality of connection points. The ROM decoder selects one of the plurality of gradation voltages generated by the ladder resistor, based on a supplied data signal. The test circuit measures a leakage current in the ROM decoder. The test circuit includes: a plurality of separation units, and a control unit. The plurality of separation units separates the series connection, which is respectively supplied with different power source voltages at both ends, at a certain portion, when the leakage current is measured. The control unit controls separation of the plurality of separation unit corresponding to the data signal.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: May 3, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hideyuki Tokuno
  • Patent number: 7928768
    Abstract: A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: April 19, 2011
    Assignee: Altera Corporation
    Inventors: Bruce B. Pedersen, Sivaraman Chokkalingam
  • Patent number: 7852108
    Abstract: In one embodiment of the present invention, a programmable interconnect circuit is provided. The programmable interconnect circuit includes first and second static random access memory cells, each having a first output and a second output. The second output is an inversion of the first output. First and second pass gates are each coupled to one of the first and second outputs of the respective first and second memory cells. First and second lock-state circuits are coupled to the respective first and second memory cells. In response to a configuration status signal and the first output of one of the memory cells being asserted to a low voltage, the respective lock-state circuit is configured to maintain the one of the outputs of the respective memory cell at the low voltage.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: December 14, 2010
    Assignee: Xilinx, Inc.
    Inventor: Austin H. Lesea
  • Patent number: 7804320
    Abstract: The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: September 28, 2010
    Assignee: University of South Florida
    Inventors: Nagarajan Ranganathan, Koustav Bhattacharya
  • Patent number: 7760006
    Abstract: Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: July 20, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Kevin P. Lavery, Jim D. Childers, Pravin P. Patel
  • Patent number: 7741877
    Abstract: An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: June 22, 2010
    Assignee: STMicroelectronics, SA
    Inventors: Philippe Roche, Francois Jacquet, Jean-Jacques De Jong
  • Patent number: 7741864
    Abstract: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, such as the type introduced through radiation or, more broadly, single-event effects (SEEs). SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits, among others.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: June 22, 2010
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Clinton W. Kelly
  • Patent number: 7719304
    Abstract: The present invention provides a radiation hardened flip-flop formed from a modified temporal latch and a modified dual interlocked storage cell (DICE) latch. The temporal latch is configured as the master latch and provides four output storage nodes, which represent outputs of the temporal latch. The DICE latch is configured as the slave latch and is made of two cross-coupled inverter latches, which together provide four DICE storage nodes. The four outputs of the temporal latch are used to write the four DICE storage nodes of the DICE latch. The temporal latch includes at least one feedback path that includes a delay element, which provides a delay.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: May 18, 2010
    Assignee: Arizona Board of Regents for and on behalf of Arizonia State University
    Inventors: Lawrence T. Clark, Jonathan E. Knudsen
  • Patent number: 7647543
    Abstract: An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: January 12, 2010
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Tak-kwong Ng, Jeffrey A. Herath
  • Publication number: 20090189643
    Abstract: A constant voltage generator device provides a first and a second transistor having their main current path coupled serially via a common terminal for providing a constant output voltage at the common terminal of said transistors. The device provides one or more potential dividers having a plurality of serially connected resistive elements. A first voltage is obtained from a first combination of resistive elements of the potential divider and a second voltage obtained from a second combination of resistive elements of the potential divider. The first and the second voltages are supplied to the first and the second voltage at the control terminals of the first and the second transistors, respectively.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 30, 2009
    Applicant: ST WIRELESS SA
    Inventor: Dharmaray M. Nedalgi
  • Publication number: 20090167343
    Abstract: Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic application where high threshold voltage devices are used to reduce leakage at the expense of reduced logic speed. Better performance is achieved than a high threshold voltage stack.
    Type: Application
    Filed: December 29, 2007
    Publication date: July 2, 2009
    Inventor: Andrew Marshall
  • Patent number: 7504851
    Abstract: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: March 17, 2009
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Clinton W. Kelly
  • Patent number: 7501849
    Abstract: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: March 10, 2009
    Assignee: Altera Corporation
    Inventor: Srinivas Perisetty
  • Patent number: 7499676
    Abstract: A low voltage differential signaling transceiver includes a transmitter and a receiver, the transmitter having a first terminal in signal communication with a transmission line, a source resistance in signal communication with the first terminal, a switch in signal communication with the source resistance and in switchable signal communication from ground or an input voltage, a voltage regulator in switchable signal communication with the switch for providing the input voltage to the switch, and a voltage controller in signal communication between the first terminal and the voltage regulator for controlling the input voltage to provide a controlled voltage to a receiver; and the receiver having an amplifier having a first input, a first pad in signal communication with the first input, a load resistance, and a second pad in signal communication with the load resistance, where the first and second pads are both in signal communication with one end of a first transmission line.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: March 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jac-Youl Lee, Jae-Suk Yu, Jong-Seon Kim
  • Patent number: 7427872
    Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: Theodore Z. Schoenborn, Andrew W. Martwick
  • Patent number: 7427871
    Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: September 23, 2008
    Assignee: Element CXI, LLC
    Inventors: Steven Hennick Kelem, Jaime C. Cummins, John L. Watson, Robert Plunkett, Stephen L. Wasson, Brian A. Box, Enno Wein, Charles A. Furciniti
  • Publication number: 20080150575
    Abstract: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present.
    Type: Application
    Filed: March 7, 2008
    Publication date: June 26, 2008
    Inventor: Srinivas Perisetty
  • Patent number: 7245159
    Abstract: A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: July 17, 2007
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Christian Jacobi, Hwa-Joon Oh, Silvia Melitta Mueller
  • Patent number: 7212027
    Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: May 1, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Atsuhiko Ishibashi, Yasuhiro Fujino