Abstract: A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.

Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.

Abstract: A process variation detector includes a pulse-signal generating unit that generates a pulse signal having a pulse width corresponding to a characteristic of a process variation in an integrated circuit based on a clock signal; and an output unit that generates a predetermined value, when the pulse signal indicates a specific process variation, by using a transistor of which a channel width and a gate length are set to an unbalanced state, and outputs the predetermined value.

Abstract: Structures and methods of reducing the susceptibility of programmable logic device (PLD) configuration memory cells to single event upsets (SEUs) by selectively adding metal-to-metal capacitors thereto. By adding capacitance to storage nodes in a memory cell, the susceptibility of the memory cell to SEUs is reduced. However, the performance of the memory cell also suffers. In PLD configuration memory cells, performance is not the most important factor. Therefore, for example, SEU-reducing capacitors can be selectively added to the PLD configuration memory cells while omitting the capacitors from user storage elements (e.g., block RAM) within the PLD. Thus, performance of the user storage elements is not adversely affected. Further, the use of metal-to-metal capacitors is well-suited to the configuration memory cells of a PLD, because these memory cells typically have additional area available for the capacitors above the programmable logic elements controlled by the associated configuration memory cells.

Abstract: A semiconductor device has an electrostatic protection diode in a signal input portion thereof and is accompanied by a parasitic transistor between the diode and an output control transistor. The semiconductor device further has a dummy transistor that is formed closer than the output control transistor to the electrostatic protection diode, and an output logic determining circuit that keeps the output signal at a predetermined logic level so long as the parasitic transistor formed between the electrostatic protection diode and the dummy transistor is on. With this configuration, malfunctioning caused by a parasitic transistor can be prevented without the use of an externally fitted component.

Abstract: A method includes providing a device under test (DUT) which has an input port and an output port. The DUT also has a squelch detector which is coupled to receive a signal from the input port. The DUT also has a receiver amplifier coupled to receive a signal from the input port. In addition, the DUT also has a transmitter to transmit data signals from the output port. The method further includes providing a loopback connection from the output port to the differential input port. The method also includes controlling the transmitter to transmit a test signal from the output port to the input port. The method includes monitoring at least one of respective outputs of the receiver amplifier and the squelch detector to determine whether a leakage condition exists in the DUT. Other embodiments are described and claimed.

Abstract: A wiring structure of a semiconductor device, includes a wiring layer formed on an insulating film, a width (W) of each wire in the wiring layer and a thickness (H) of the insulating film satisfying “W/H<1” a length (L) of each wiring in the wiring layer being equal to or longer than 1 mm.

Abstract: An apparatus and method for selectively enhancing the soft error rate (SER) immunity of a dynamic logic circuit. The apparatus includes a bootstrap capacitor coupled to a precharge input signal and a dynamic node of the dynamic logic circuit, and a device, such as an FET, for selectively connecting the bootstrap capacitor to the dynamic node.

Abstract: Programmable systems and devices that include programmable multiplexers designed to minimize the impact of single event upsets (SEUs) on triple modular redundancy (TMR) circuits. In a programmable routing multiplexer, each path through the multiplexer is controlled by a different configuration memory cell. A unidirectional buffer is included on each routing path through the multiplexer. Therefore, an SEU changing the state of any single memory cell does not short together any two input terminals of the multiplexer. Hence, when a TMR circuit is implemented using the multiplexer, an SEU affecting the multiplexer causes no more than one TMR module to become defective. The other two TMR modules together provide the correct output signal, outvoting the defective module, and the circuit continues to operate correctly.

Abstract: A global interconnect distribution system is disclosed. The global interconnect distribution system includes a global interconnect cell capable of producing at least two substantially identical output signals, and a global interconnect coupled to the cell for carrying one of the output signals. At least one wire is also coupled to the cell that is routed adjacent to the global interconnect for carrying the other output signal to provide active shielding for the global interconnect, thereby increasing signal integrity and signal transmission of the global interconnect.

Abstract: A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.

Abstract: An address signal is transferred from an address bus transmitting an address from an address generation circuit, to a real address bus connecting to a decoder for decoding an applied address signal, via a branch node, a branch address bus and contacts. The real address bus and the branch address bus are electrically connected at a plurality of points using the contacts. The branch address bus functions as a lining or backing signal line to the real address bus, and a line resistance and line capacitance of the real address bus can be equivalently reduced. A variation in signal propagation delay over an entire decoding circuits is suppressed.

Abstract: A processor includes an integer unit operable to execute integer instructions and a floating point unit operable to execute floating point instructions. The processor also includes at least one spare fill cell disposed in at least one portion of the processor that is not occupied by the integer unit and the floating point unit. The at least one spare fill cell includes at least one spare transistor configured as a capacitor and coupled to a voltage rail and a ground rail.

Abstract: A semiconductor device includes a signal line and two adjacent wirings formed on a first substrate layer, an adjacent wiring formed on a second substrate layer, and an adjacent wiring formed on a third substrate layer. A logical level on the signal line is set constant, a first line capacitance is formed between the signal line and one of the adjacent wirings on the first substrate layer, and a second line capacitance is formed between the signal line and the other of adjacent wirings on the first substrate layer. Also, a signal is supplied to the adjacent wiring on the second substrate layer and the adjacent wiring on the third substrate layer. As a result, noise from the other adjacent wirings to the signal line can be reduced.

Abstract: An integrated circuit that asymmetrically shields a signal to increase decoupling capacitance is provided. The signal is asymmetrically shielded based on a probability of the signal being at a specific value. Further, a computer system that uses asymmetrically shielding to increase performance is provided. Further, a method for increasing an amount of implicit decoupling capacitance on a circuit through asymmetric shielding is provided. Further, a method to increase component performance by increasing implicit decoupling capacitance is provided.

Abstract: A circuit includes a resistance-capacitance (RC) structure connected to a first set of transistors and a second set of transistors that perform the same logical function as the first set of transistors. The first set of transistors have thinner gate oxides than the second set of transistors. The RC structure drains an electric field from the first set of transistors, such that the first set of transistors are on only during initial transistor switching. In other words, the RC structure turns off the first set of transistors after transistor switching is completed. Also, the first set of transistors and the second set of transistors share common inputs and outputs. The first set of transistors exhibit higher tunneling currents than the second set of transistors. The thinner gate oxides of the first set of transistors cause the first set of transistors to exhibit higher device currents than the second set of transistors.

Abstract: A shield circuit includes shielding wires and a shielding wire driving circuit, the shielding wires being provided along a target wire that requires shielding, and the shielding wire driving circuit driving the shielding wires with a logical value corresponding to a logical value of at least one of inputs to a cell that drives the target wire.

Abstract: A method and apparatus for reducing leakage in dynamic Silicon-On-Insulator (SOI) logic circuits improves the performance of dynamic gates implemented in SOI technology. A bias generator is used to create a negative potential by using the pre-charge input signal to bootstrap a bulk capacitor charging circuit, shifting a positively charged bulk capacitor terminal to ground, causing a negative potential at the other terminal. A bias control circuit applies this negative potential to intermediate nodes of logic input ladders of a dynamic logic gate to reduce leakage and threshold lowering effects due to the voltage variation on the bodies of logic input transistors implemented in SOI logic.

Abstract: A semiconductor integrated circuit includes a plurality of signal wiring lines, and a plurality of shield wiring lines, each of which is arranged between adjacent two of the plurality of signal wiring lines. An interference preventing section is connected to the plurality of shield wiring lines, and supplies an inference preventing signal to two of the plurality of shield wiring lines adjacent to a specific one of the plurality of signal wiring lines. The inference preventing signal is switched to have a same phase as an input signal which is supplied to the specific signal wiring line.

Abstract: The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by eliminating the effects the sneak current discharging path by applying a contention free arrangement methodology to realize the dynamic logic circuit. The SOI MOS devices are arranged so as to eliminate the effects of electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.

Abstract: The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate node and a second evaluate node. Additionally, the logic device comprises a first input signal that has a first input wire and a second input wire where the first input wire corresponds to a first possible value of the first input signal and the second input wire corresponds to a second possible value of the first input signal. The logic device further comprises a first plurality of intermediate nodes that includes a first intermediate node. Additionally, the logic device includes a first plurality of transistors that further includes a first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal.

Abstract: In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor. An input is coupled to the domino silicon-n-insulator (SOI) field effect transistor. A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor. The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit couples the input to the domino silicon-on-insulator (SOI) field effect transistor. The output of the dynamic input circuit is low during the precharge mode. The output of the dynamic input circuit corresponds to the input during the evaluate mode. The output of the dynamic input circuit is used to gate the predischarging device.

Abstract: A CMOS logic circuit including (a) a PMOS transistor, (b) an NMOS transistor, (c) a first coupling capacitor electrically connected only between a gate and a substrate of the PMOS transistor, and (d) a second coupling capacitor electrically connected between a gate and drain of the NMOS transistor, wherein the PMOS and NMOS transistors include substrate voltages which are made higher than associated reference voltages during rising edges of signals transmitted to the gates, and made lower than the associated reference voltages during falling edges of the signals. The gates of the PMOS and NMOS transistors are electrically connected to each other, drains of the PMOS and NMOS transistors are electrically connected to each other, and an input signal is introduced into the electrically connected gates, and an output signal is taken through the electrically connected drains.

Abstract: A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.

Abstract: In an integrated circuit arrangement with an open-collector transistor of the npn type, the collector of the open-collector transistor is connected through a collector resistor with preferably low ohmic resistance to an open-collector output of the circuit arrangement to which an output voltage is applied, and, through a parasitic diode which is switched in the reverse direction when the output voltage has a positive value, to a ground terminal of the circuit arrangement. The emitter of the open-collector transistor is connected to the ground terminal of the circuit arrangement and the base of the open-collector transistor is connected to a base current source that generates a base current.

Abstract: A line driver (10) includes a first p-channel FET (12) and two n-channel FETs (14-16), wherein one of the n-channel FETs functions as a blocking FET (16). The p-channel FET (12) is coupled to the supply voltage (26) and the blocking FET (16), while the other n-channel FET (14) is coupled to a supply return (28) and the blocking FET (16). An output (30) is provided between the n-channel FET (14) and the blocking FET (16), while inputs (20-22) are provided to the p-channel FET (12) and the n-channel FET (16). In operation, the inputs (20-22) are supplied to the FETs at a given rate such that either the p-channel or the n-channel FET is "on". To ensure a maximum output swing when the p-channel FET is on, the blocking FET (16) is sourced by a charge pump (18).

Abstract: A transmitter end stage for a data transmission system comprising at least one control unit and data transmission lines, especially for a CAN bus system having at least one CAN controller and one CAN bus (CB) is proposed, characterized by the fact that the individual circuit elements of transmitter end stage 18 are integrated monolithically. As a result of the special layout and its circuit-design arrangement of the individual elements (3, 5; R1, D1, T1; R2, D2, T2; D10, D20) of the transmitter end stage, the effects of malfunctions, for example of short circuits of the data lines to ground or to the supply voltages, are reduced to a minimum. As a result of the special choice of pre-drivers (3, 5), minimum delay times are achieved, so that signals can be transmitted at a higher data rate.

Abstract: Data to be processed are transferred by connecting a one-way element having a reduced parasitic capacitance such as the Schottky diode between an output MOSFET having an open drain structure and an output terminal to be connected with a bus line terminated by an impedance element.

Abstract: A semiconductor integrated circuit device has a first wire for transmitting a first signal and a second wire adjacent to the first wire, for transmitting a second signal having the stronger probability of having an opposite phase to that of the first signal. A space between the first and second wires is wider than a standard wiring space, to reduce a delay in the operation speed of the device due to wiring capacitance produced between the first and second wires.

Abstract: A switch matrix including a number of rows of input conductors, a number of columns of output conductors, and switching devices joining selected ones of the input conductors to selected ones of the output conductors, the switching devices being programmable to make connections between input and output conductors, the switching devices joining conductors being positioned on a random basis.

Abstract: An improved differential gain stage for a bipolar monolithic integrated circuit. The integrated circuit is formed from a semiconductor substrate, and the differential gain stage includes first and second bipolar transistors. The base of the first transistor and the base of the second transistor form a differential input for the gain stage comprising non-inverting and inverting inputs respectively. The collectors of the transistors form a differential output. The differential gain stage includes a capacitor stage comprising: a peaking capacitor, and first, second, third and fourth capacitor structures. The peaking capacitor is coupled between the emitters of the first and second transistors. The first and second capacitor structures are located at a first spaced relationship from the substrate and the first capacitor is coupled to the emitter of the first transistor and the second capacitor is coupled to the emitter of the second transistor.