Abstract: A data processing apparatus has a number of data processors connected in a series by data lines so that data signals are processed in a preceding processor and communicated to a succeeding processor in the series. The apparatus has a number of control elements, where a control element has first and second inputs receiving processor status signals and an output sending a signal to enable processing. The control element output assumes a certain output state only if both inputs assume the state. The output, having assumed the state, holds the state, despite one of the inputs not holding the state, only if a certain one of the inputs does hold the state.

Abstract: In a method and apparatus for shifting the level of a signal a shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to changes in logic state of input signal and whose voltage level is shifted with respect to the input signal. The logic low state of the output signal is shifted to a certain voltage level above ground. A first switching device sets the voltage level of the logic low state. A feedback circuit feeds a signal derived from the output signal back to the switching device to precondition the shifter so that the speed of the output signal transition from one state to another is accelerated.

Abstract: An output buffer is disclosed for an integrated circuit having a varying number of simultaneously switching outputs. As fewer outputs on the integrated circuit are simultaneously switching, the output conductance of certain logic gates within each of the output buffers on the integrated circuit is increased by sharing intermediate nodes between each of the output buffers. Consequently, the speed of the output buffer increases as fewer of the outputs simultaneously switch and internally generated noise is small. Conversely, as additional outputs simultaneously switch, the output conductance of certain logic gates within the output buffer is decreased, resulting in reduced speed of the output buffers and a corresponding reduction in internally generated noise.

Abstract: An input logic signal buffer circuit includes a differential amplifier which is responsive to an input logic signal and to a reference signal, to produce an output logic signal at an output node thereof. The input logic signal buffer circuit also includes a bypass amplifier which is electrically connected between the output logic signal and the output node. The bypass amplifier supplies additional current to the output node in response to logic level transitions of the input logic signal. The bypass amplifier preferably is a field effect transistor, the gate of which is electrically connected to the input logic signal and the source and drain of which are serially connected between the output node and a current limiting resistor. Logic level transitions with reduced delays, particularly at low power supply voltages, are thereby provided.

Abstract: An apparatus and method is provided for precharging a conductor within a bus containing a plurality of conductors. The apparatus comprises a precharge circuit which drives an intermediate voltage between VDD and ground upon respective conductors. The precharge driver maintains the intermediate voltage within a range between a first voltage level and a second voltage level, the second voltage level being higher in magnitude than the first voltage level. The precharge voltage defined within an intermediate voltage range is chosen to consume minimal power within the precharge driver. An isolation device can be provided on each conductor for isolating the intermediate, precharged value from a receiver circuit input so as to minimize power consumption of the overall circuit. Precharging to an intermediate value causes logic-driven transitions within the bus to occur at a faster frequency than if the bus were precharged to full rail.

Abstract: A semiconductor integrated circuit device has a data selecting circuit connected to a first power supply terminal, a precharge circuit, connected to a second power supply terminal, for receiving a precharge signal, and a wiring line connected to a common connection point between the data selecting circuit and the precharge circuit. The data selecting circuit includes at least two, i.e., first and second data transmission circuits. A first input data signal and a first selecting signal are supplied to the first data transmission circuit. A second input data signal and a second selecting signal are supplied to the second data transmission circuit.

Abstract: A level shifting inverter is provided with first and second drivers which may be level shifting inverters, which each have a low enable input, a high enable input and an output. Each driver outputs a low voltage level or a second high voltage level(that is higher than a first high voltage level of an input signal) depending on enabling and disabling voltage levels received at the high and low enable inputs of each driver. The high enable input of the first and second drivers are connected in a cross-coupled feedback configuration. The input of the first driver receives a complement of the input signal whereas the input of the second driver receives the input signal. The level shifter also has transition driver circuitry. The transition driver circuitry has an input receiving the second high voltage level, a first biasing input receiving the input signal and a second biasing input receiving the complement of the input signal.

Abstract: Negative-resistance resonant tunnel diodes (RTDs) perform a complete set of logic functions with a single basic configuration. Inputs feed through Schottky diodes to a transfer RTD coupled to a clocked latch having two RTDs in series. Cascaded gates are driven synchronously by multiple clock phases or by asynchronous event signals. An XOR configuration also provides logical inversion.

Abstract: An intermediate potential setting circuit includes two MOS transistors having different conductivity types and connected in series between reference power supplies, first and second gate control units, respectively connected to gates of the transistors, for separately ON/OFF-controlling the transistors, a load capacitor connected between the connection node of the transistors and one of the reference power supplies, a control unit, connected between the connection node and the first and second gate control units, for feeding back a potential of the connection node to the first and second gate control units to selectively perform control to turn on the transistors, an external control unit for externally supplying a control signal to the first and second gate control units, and an output terminal, connected to the connection node, for extracting an intermediate potential output as a potential of the load capacitor.

Abstract: A differential transistor pair is used for a Low Voltage Transistor-Transistor Logic (LVTTL) input buffer to provide an input buffer for a modified and enhanced LVTTL specification. The differential input buffer accurately detects high and low voltages which are respectively lower and higher than existing specified LVTTL voltage levels, yet provides output voltages that are representative of intended logic levels. This provides the ability to use the improved input buffer with existing drivers at higher frequencies where the voltage swing provided by the existing drivers do not produce as large a voltage swing as that required by existing LVTTL specifications.

Abstract: The present invention is to provide an output circuit, for a semiconductor circuit, capable of increasing the rise or fall time of an output signal without reducing the operating frequency of the output circuit, and thus effectively preventing occurrence of a malfunction due to an undesired change in the output signal caused by ringing, noise, or reflection occurring at the transition of the output signal. In the structure of present invention, an output circuit for a semiconductor circuit includes an input circuit, an output circuit including a transistor, and a control signal control circuit that lies between the input circuit and output circuit, outputs a control signal for use in driving the transistor in the output circuit, and changes the control signal according to a function of time.

Abstract: A maintenance circuit for a bus (1) with a tristate driver (2) which includes a keeper circuit (3) having a first inverting logic gate (4) with an input connected to the bus (1) and a second inverting logic gate (5) with an input (6) connected to the output of the first logic gate (4). The output of the second logic gate (5) is restricted in current relative to that of tristate driver (2) and is connected directly to the bus (1). The keeper circuit (3) has a control input (7) for disabling positive feedback therein, such that the keeper circuit (3) acts as a pull-up or pull-down circuit.

Abstract: The semiconductor IC device has a circuit arrangement constituted by a first CMOS logic gate having input and output terminals, and a second CMOS logic gate which performs the same logic operation as that of the first CMOS logic gate and which has an input terminal connected to the input terminal of the first CMOS logic gate. The arrangement also requires a differentiator circuit which has an input terminal thereof connected to an output terminal of the second CMOS logic gate and has an output terminal connected to the output terminal of the first CMOS logic gate. With such an arrangement, the dependency of the effective gate propagation delay time on an output load is lowered. As a result, therefore, the arrangement can be effected using a low power supply voltage while securing a high operation speed as well as a low power consumption. The CMOS logic gates can also be facilitated in combination with NPN bipolar transistors which are connected therewith in an emitter follower circuit form.

Abstract: A logic circuit employing feedback controlled loads to increase the response time and minimize power consumption. A plurality of input circuits are provided, each having means for coupling a first signal to a second signal. A first load responsive to the second signal provides a means for pulling up the first signal and a second load responsive to the first signal provides a means for pulling down the second signal. A driver responsive to the first and second signals is provided for generating an output voltage.

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Abstract: A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.

Abstract: An input circuit (10) includes two inverters (12, 16) and an enable transistor (18). When a logic high enable signal is transmitted to a gate electrode of the enable transistor (18). The two inverters (12, 16) form a latch that holds the data at the input port (21) of the input circuit (10). When a logic low enable signal is transmitted to the gate electrode of the enable transistor (18), the latch formed by the two inverters (12, 16) is disabled, thereby allowing fast data transmission through the input circuit (10). When the voltage at the input port (21) is higher than a supply voltage of the input circuit (10), the enable transistor (18) switches off to protect a voltage supply coupled to the input circuit (10).

Abstract: A static logic circuit employs pull-down type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities higher than those of the logic transistors forming the power supply current path, and pull-up type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities lower than the logic transistors forming the power supply current path, and comprises logic series formed by alternately cascading the two types of the logic gates. The static logic circuit is provided with signal merged logic circuits each of which provides a signal having a high speed falling transient and a high speed rising transient by merging the output signals of the logic series.

Abstract: An output buffer circuit with low power pre-output driving capability uses existing output drivers and includes input inverters with three-state outputs interposed between the input and output stages and a feedback circuit with three-state outputs connected to the output stage. During normal data transmission, the input inverters buffer the incoming complementary data signals driving the pull-up and pull-down transistors in the output stage while the three-state outputs of the feedback circuit are turned off. Upon receiving an active pre-output control signal, the input inverters are disabled, thereby isolating the pull-up and pull-down transistors from the incoming complementary data signals, and the feedback circuit is enabled. The enabled feedback circuit monitors the signal level of the output signal from the output stage.

Abstract: An input/output circuit for increasing immunity to voltage spikes from voltage supplies is provided. The circuit includes a first pair of transistors each having their drains connected to an output terminal and their sources connected to voltage supplies. A mechanism is connected to electrically separated voltage supplies to alternately turn on one of the first pair of transistors responsive to an input signal. A transistor is utilized to provide feedback to limit the rise in a ground voltage supply as occurs during ground bounce.

Abstract: An object of the present invention is to provide a buffer circuit little sensitive to a deviation from a threshold voltage of each of transistors. In order to achieve the above object, the present invention provides a typical buffer circuit comprising the following components.

Abstract: Disclosed is an improved push-pull off-chip driver circuit. The circuit includes a push-pull amplifier including a pull-up transistor and a pull-down transistor, each provided with independent inputs and connected at the output node. The input to the pull-up transistor is provided by a transmission gate having an n-channel transistor connected in parallel with a p-channel transistor. A control transistor is coupled between the output node and the gate of the pull-up transistor to provide a protective bias. A feedback override circuit is coupled between the output node and the gate of the p-channel transmission gate transistor to selectively provide either Vout or a low level potential to that gate. The feedback override circuit improves the response time and noise immunity of a prior art off-chip driver in the active mode in a manner consistent with the objectives of protecting the gate oxides from high voltage stress and prevent leakage currents during the high-impedance mode.

Abstract: In an output buffer circuit so configured that a capacitor connected to a gate of an output driving MOS transistor and including a gate capacitance of the output driving MOS transistor is gradually charged through a resistor, so as to realize a slow rising or falling time, there is additionally provided a threshold voltage charging circuit for rapidly charging the capacitor to a threshold voltage level of the output driving MOS transistor when the output driving MOS transistor is to be turned on. With this arrangement, the propagation delay time of an output voltage can be minimized.

Abstract: Driving circuits (6) output driving signals to drive switching transistors (Q 15, Q16). A potential as the high level of the driving signal can be set lower than a power supply voltage (V.sub.DD) by connecting the sources of transistors (Q18, Q20) to a node (X). This configuration prevents an overshoot at a switching time and allows an improvement in a settling time. Therefore, a complementary current source circuit for a high-speed D/A converter can be provided.

Abstract: A data output buffer circuit for a semiconductor device for transferring read cell data to the peripheral circuits, comprising an input terminal for inputting the read cell data, a first NMOS transistor for transferring the data from the input terminal when it has a first logic level, a first PMOS transistor for transferring the data from the input terminal when it has a second logic level, a second PMOS transistor for transferring a high logic signal in response to an output signal from the first NMOS transistor, a second NMOS transistor for transferring a low logic signal in response to an output signal from the first PMOS transistor, and an output terminal for outputting the high logic signal from the second PMOS transistor or the low logic signal from the second NMOS transistor to the peripheral circuits.

Abstract: A CMOS circuit in which the threshold voltage of at least one MOS transistor of the CMOS circuit is altered is disclosed. By altering the threshold voltage the speed/power dissipation tradeoff can be modified to match the design criteria of a particular CMOS circuit. For example, to increase the pull-up speed of the PMOS transistor in the CMOS transistor pair of a CMOS circuit, the threshold voltage of selective MOS transistors is lowered. The altering can occur on a device level or a circuit level. A method for designing such CMOS logic circuits is also disclosed.

Abstract: The direction of a bidirectional buffer inserted along a bus line is dynamically controlled to be always away from the signal source. The signals which select a tristate buffer to turn on for driving the bus also affect or determine the direction of all buffers inserted in the bus line. Since only one tristate enable signal will be active, the direction which each bidirectional buffer should drive is dynamically determined by the presently active enable signal.

Abstract: There is disclosed an input circuit for a semiconductor integrated circuit device wherein a level shift circuit (LS1) adds a constant voltage to an input signal from an input signal terminal (3) and a reference voltage from a reference voltage terminal (4) to output signals, which are in turn amplified by means of a plurality of cascaded, first and second differential amplifier circuits (Dif1, Dif2), and then a difference between the amplified input signal and the amplified reference voltage is applied to a CMOS inverter circuit (In1), which in turn outputs a power supply potential (V.sub.DD) or a ground potential (V.sub.SS) in accordance with the difference, thereby achieving a high-speed operation in response to the binary input signal slightly varying in signal voltage and a normal operation independent of variation of the reference voltage. (FIG.

Abstract: A data output buffer rapidly transits an output data signal to improve the data reading speed of a semiconductor memory device. To do this, the data output buffer comprises a first input terminal for receiving true data, a second input terminal for receiving complementary data, a pull-up MOS transistor connected between a first power supply and an output line and being driven by the true data from the first input terminal, a pull-down MOS transistor connected between a second power supply and the output line and being driven by the complementary data from the second input terminal, a reference logic voltage generator for supplying a reference logic voltage to the output line, and a controller for driving the reference logic voltage generator, by the true data from the first input terminal and the complementary data from the second input terminal to be complementary to the pull-up MOS transistor and the pull-down MOS transistor.

Abstract: A method of state splitting in a state machine includes determining a number N of logic levels, i.e. CLB levels, for each state in a state machine. Number N is equal to N.sub.i-1 +log.sub.k f.sub.i wherein "k" is the number of input lines to a CLB, "i" is a particular node in a particular hierarchial level in the Boolean logic, and "f" is the number of fanin transitions to the particular node. An average number N(AV) as well as a maximum number N(MAX) of CLBs to implement the states in the state machine are also determined. Then, predetermined exit criteria are checked. One exit criterion includes determining that the maximum number N(MAX) is not associated with a state register, but is instead associated with an output, for example. Another exit criterion includes providing a ratio by dividing the maximum number N(MAX) by the average number N(AV). If the ratio is less than or equal to a split-factor, then this exit criterion is met. In one embodiment, the split factor is between 1.5 and 2.0.

Abstract: The gates (11) of the exclusive OR type having two inputs (A, B) are disposed in tree structure in successive layers of an integrated circuit beginning with an input layer which receives the input signals of the tree. The output of each gate is connected to an input of a gate in the adjacent layer. Each gate includes two cells (11a, 11b) that switch substantially simultaneously in response to two respective complementary signals (A, NA; B, NB) from one of the two inputs and that supply respective output signals that are representative of the complementary functions (XOR, NXOR) of the exclusive OR type. This makes it possible to obtain propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagated may be.

Abstract: A buffer apparatus having a low output impedance includes a first transistor having one terminal coupled to a voltage source, the other terminal coupled to an output terminal of the buffer, and a gate which receives an input signal of the buffer; a second transistor having one terminal coupled to the output terminal of the buffer and a gate which receives the input signal of the buffer; a current sensing circuitry, which is coupled to the other terminal of the second transistor, for sensing a current of the second transistor and amplifying an input current which flows to the second transistor; a voltage driving circuitry, which is formed between the output terminal of the buffer and a ground voltage, for decreasing an output voltage of the buffer by passing the current from the output terminal to the ground voltage according to a control signal which is applied to the voltage driving circuitry.

Abstract: A current switching circuit (10) receives an input signal having one of an upper and a lower signal level. First (60) and second (70) transistors switch an output (115) between the upper and the lower signal level in response to the input signal. A first high resistance path (80) is selectively coupled via a gate (75) between the first transistor (60) and a first potential. A second high resistance path (90) is selectively coupled via a gate (85) between the second transistor (70) and a second potential. A control input (20) causes a logic arrangement (22) to control the gates (75, 85) thereby selectively coupling the high resistance paths (80, 90) to the first (60) and second (70) transistors such that they can switch the output at a first and a second switching speed.

Abstract: In an output circuit, a signal /.phi. opposite in phase to a signal /EN inputted through an input terminal 3 is generated by an inverter 1, and a signal .phi. in phase with the signal /EN is generated by two inverters 8 and 2. When the input signal /EN changes from a high level to a low level, a bipolar NPN transistor 35 is turned on instantaneously to decide an output terminal 5 at the low level forcedly. On the other hand, when the signal /EN changes from the low level to the high level, an NPN transistor 10 is turned on in advance of the other circuits to decide the output terminal 5 at the high level forcedly. Accordingly, it is possible to roughly equalize a delay time (from when the level of the input signal /EN changes at the input terminal 3 to when the level of the signal /.phi. changes at an output terminal 4) to another delay time (to when the level of the signal .phi. changes at the output terminal 5), thus realizing an ideal phase relationship between the two signals/.phi. and .phi.

Abstract: A technique is provided for switching circuitry in a manner which allows the circuit to respond quickly to changes in some critical input signals expected to arrive last. In the preferred embodiment the circuits of this invention are provided in triple logic column form. A circuit will typically include at least two logic columns, each having three portions serially coupled between a high and a low potential source. The middle portion of each logic column is connected to the output node and to receive the critical input signal expected to arrive last, or the input signal with the critical timing requirement. The upper and lower portions of each logic column are connected to receive the remaining input signals, that is those input signals not expected to be changing at the time the critical input signal is received. Thus, the state of the upper and lower portions of the logic column can be "set-up" in advance, in readiness for the critical input condition.

Abstract: An output buffer circuit is provided, which enables to reduce the delay of a digital output signal with respect to an input digital signal. The output buffer circuit includes first and second FETs serially connected to each other. A gate of the first FET is applied with a first digital input signal. A gate of the second FET is applied with a second digital input signal. The first and second FETs operate to be opposite or complementary in logic state to each other. A digital output signal is taken out from a connection point of the first and second FETs. The circuit further includes a current source for causing a bias current having the same direction or polarity as that of a drain current of the first FET to flow through the first FET in the pseudo-OFF state. A turn-on speed of the first FET from the pseudo-OFF state to the ON state is enhanced by the bias current.

Abstract: A pre-charge load device to pre-charge an input on a sense amplifier is coupled between a positive voltage rail and the input to the sense amplifier and is biased by a bias network coupled between the positive voltage rail and the sense amplifier input to adapt the sense amplifier slew rate in relation to large or unpredictable capacitive impedance changes on the sense amplifier input.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A complementary pipelined logic circuit includes (a) a logic unit that processes a plurality of complementary inputs into a pair of complementary outputs, (b) a load circuit that is connected to a voltage supply node to establish complementary outputs having a voltage swing greater than the output voltage swing of the logic unit, and (c) a control circuit that interfaces between the logic unit and the load circuit and responds to a clock input by controlling the logic state of the load circuit's outputs in accordance with the logic state of the logic unit's outputs. The load circuit is preferably implemented as a regenerative latching circuit that pulls the output voltage swing up to the full supply voltage value. The logic unit and control circuit are preferably implemented with N-channel devices for high speed and compactness, while the latching load circuit is preferably implemented with P-channel devices to obtain a full scale voltage pullup.

Abstract: A self-timed control circuit for self-resetting CMOS logic circuitry provides handshaking between macros to ensure that all data inputted to a particular macro is maintained by the source macros until all data inputs have been received. A data output signal from a macro is maintained until the macro receives a complete signal from all receiving macros indicating that the receiving macros have received all data inputs supplied to them.

Abstract: An output preconditioning circuit with an output level latch is provided to precondition the output to an intermediate level and to clamp the output to that level before the actual data from a memory cell arrives at the output. Since the actual data has to charge or discharge the output from some intermediate level rather than the maximum output swing level or the minimum output swing level, as in the normal case, this results in a reduced delay in charging or discharging the output. The output preconditioning circuit which may be coupled to a heavy load or a light load can eliminate oscillation of the output because of the output level latch.

Abstract: The turn-off delay time of a low-side driver (output power transistor), may be independently reduced and eventually made identical to the turn-on delay time by employing an auxiliary current generator that may be controlled by the same switching signal that controls a current generator employed for discharging the control node of the low-side driver, in order to provide an augmented discharging current during a first phase (only) of a turn-off process. The contribution to the capacitance discharge current provided by said third current generator is automatically interrupted by means responsive to the voltage present on the driving node of the low-side driver, when it approaches saturation.

Abstract: A word line driver circuit operable for receiving address signals from a decoder circuit and for gating these address signals to be outputted as a word line signal to one or more memory cells within a RAM. The driver circuit prevents oscillations of the outputted word line signal by not allowing any internal nodes between circuit elements to have a floating potential. This function is provided by a plurality of circuit elements arranged in a unique manner so that the internal nodes are not allowed to float.

Abstract: Logic circuitry utilizing the advantages of static and dynamic design techniques utilize feed-forward from the inputs to the logic circuit and feed-back from the output of the logic circuit in order to provide a RESET signal to precharge the logic circuit to a predetermined state. This technique also provides for initialization of the circuit before the arrival of data input signals.

Abstract: The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are connected along the common signal line between the input pull down transistors and an output. A feedback element connects an output of the second inverter to an input of the first inverter. The inverters are configured to maintain the input of the first inverter at a first intermediate voltage level of V.sub.cc -2 Vt. Input signals received by the input transistors cause the voltage on the signal line to be pulled from the first intermediate level toward Vss. The first inverter responds by generating an output signal which swings from a low voltage of V.sub.ss towards a second intermediate level of V.sub.cc -0.7 Vt. The second inverter responds by generating an output signal which swings between the high level of V.sub.cc and a low level of V.sub.ss.

Abstract: A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.

Abstract: A driver circuit has a single feedback transistor in the driver transistor well to provide a momentary feedback from source to gate and maintain conductance of the driver transistor during turnoff of the driver transistor and thus reduce ringing oscillation at the transistor source output. An enable/disable signal is applied to control conduction circuitry and the driver transistor and force the output to a high impedance state when the circuit is disabled. Clocked operation of the driver circuit is provided with circuitry merged with a latch. A terminal for receiving a global i.sub.dd test signal controls circuitry removing power to the driver circuit and applying a ground potential to the driver output in response to the global i.sub.dd test signal.

Abstract: An input buffer circuit for converting a TTL(TTL:Transistor transistor logic) level signal supplied from an outside into an internal CMOS level signal. The input buffer circuit comprises a power voltage terminal supplied with a power voltage, a power voltage sensing signal generator for detecting a level of the power voltage by inputting as source power the power voltage supplied to the power voltage terminal and for outputting a power voltage sensing signal respondent to the detected level, and switching means for convening an external signal into an internal signal and for performing an switching operation in response to a level of the power voltage sensing signal positioned on an output path to output the convened signal.

Abstract: A bi-mode circuit for driving an output load selectively couples the output load to a supply voltage source or to a low discharge voltage source such as ground using switches which are controlled by an input buffer in response to an input signal. A high input signal closes a first switch to provide a biasing current to first and second current amplifiers to turn on a first output transistor which couples the output load to the low reference voltage to discharge the output load. Conversely, a low input signal closes a second switch to provide the biasing current to a third current amplifier to turn on a second output transistor which couples the output load to the supply voltage source. When the input signal becomes high, rapid pulldown of a capacitive output load is achieved using a high internal pre-drive current provided by the first and second current amplifiers, in a first mode of operation.

Abstract: An All-N-Logic (ANL) high-speed single-phase dynamic CMOS logic utilizing all-N-logic blocks. According to a first embodiment, a 2:1 frequency divider is provided using the ANL CMOS logic of the present invention. According to a second embodiment, a pipelines 8-bit carry generator is provided utilizing five stacked NMOS gates.